Active-semi PAC5223 Technisches Datenblatt

PRODUCT USER GUIDE

PAC5223

Power Application Controller®

Multi-Mode Power ManagerTM

Configura le Analog Front EndTM

Application Specific Power DriversTM

ARM© Cortex®-M0 Controller Core

www.active-semi.com

PAC5223 User Guide

Power Application Controller

TABLE OF CONTENTS

1. Styles and Formatting Conventions................................................................................................................. 24

1.1. Overview.................................................................................................................................................. 24

1.2. Number Representation........................................................................................................................... 24

1.3. Formatting Styles..................................................................................................................................... 24

2. Memory and Register Map............................................................................................................................... 2

2.1. Memory Map............................................................................................................................................ 2

2.2. Register Map............................................................................................................................................ 26

3. Information Block............................................................................................................................................. 39

3.1. Register.................................................................................................................................................... 39

3.1.1. Register Map.................................................................................................................................... 39

3.1.2. ROSC11........................................................................................................................................... 39

3.1.3. ADCGAIN......................................................................................................................................... 39

3.1.4. ADCOFF.......................................................................................................................................... 39

3.1. . FTTEMP........................................................................................................................................... 40

3.1.6. TEMPS............................................................................................................................................. 40

3.1.7. CLKREF........................................................................................................................................... 40

3.1.8. PACIDR............................................................................................................................................ 40

3.2. Details of Operation................................................................................................................................. 40

3.2.1. Overview.......................................................................................................................................... 40

4. System Clock Control....................................................................................................................................... 41

4.1. Register.................................................................................................................................................... 41

4.1.1. Register Map.................................................................................................................................... 41

4.1.2. CCSCTL........................................................................................................................................... 41

4.1.3. PLLCTL............................................................................................................................................ 42

4.1.4. OSCCTL.......................................................................................................................................... 42

4.1. . XTALCTL.......................................................................................................................................... 42

4.2. Details of Operation................................................................................................................................. 43

4.2.1. Block Diagram.................................................................................................................................. 43

4.2.2. Configuration.................................................................................................................................... 43

4.2.3. ROSC............................................................................................................................................... 44

4.2.4. CLKREF........................................................................................................................................... 44

4.2. . XTAL................................................................................................................................................ 44

4.2.6. EXTCLK........................................................................................................................................... 44

4.2.7. PLL................................................................................................................................................... 44

4.2.8. FRCLK............................................................................................................................................. 4

4.2.9. FCLK................................................................................................................................................ 4

4.2.10. HCLK............................................................................................................................................. 4

4.2.11. ACLK.............................................................................................................................................. 4

4.2.12. Clock Gating................................................................................................................................... 4

. Watchdog Timer............................................................................................................................................... 46

.1. Register.................................................................................................................................................... 46

.1.1. Register Map.................................................................................................................................... 46

.1.2. WDTCTL.......................................................................................................................................... 46

.1.3. WDTCDV......................................................................................................................................... 47

.1.4. WDTCTR......................................................................................................................................... 47

.2. Details of Operation................................................................................................................................. 48

.2.1. Block Diagram.................................................................................................................................. 48

.2.2. Configuration.................................................................................................................................... 48

.2.3. Watchdog Timer............................................................................................................................... 48

.2.4. Access WDT Registers.................................................................................................................... 48

.2. . WDT Clock Setting........................................................................................................................... 48

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.2.6. General Purpose Timer Mode.......................................................................................................... 48

.2.7. Watchdog Timer Mode..................................................................................................................... 49

6. GPIO Port A..................................................................................................................................................... 0

6.1. Register.................................................................................................................................................... 0

6.1.1. Register Map.................................................................................................................................... 0

6.1.2. GPIOAO........................................................................................................................................... 0

6.1.3. GPIOAOUTEN................................................................................................................................. 1

6.1.4. GPIOADS......................................................................................................................................... 1

6.1. . GPIOAPU......................................................................................................................................... 2

6.1.6. GPIOAPD......................................................................................................................................... 3

6.1.7. GPIOAIN.......................................................................................................................................... 3

6.1.8. GPIOAPSEL..................................................................................................................................... 4

6.1.9. GPIOAINTP......................................................................................................................................

6.1.10. GPIOAINTE....................................................................................................................................

6.1.11. GPIOAINTF.................................................................................................................................... 6

6.1.12. GPIOAINTM................................................................................................................................... 7

6.2. Details of Operation................................................................................................................................. 8

6.2.1. Block Diagram.................................................................................................................................. 8

6.2.2. Configuration.................................................................................................................................... 8

6.2.3. GPIO A Block................................................................................................................................... 8

6.2.4. Input................................................................................................................................................. 8

6.2. . Output and Output Enable............................................................................................................... 8

6.2.6. Output Drive Strength...................................................................................................................... 9

6.2.7. Weak Pull Up and Pull Down........................................................................................................... 9

6.2.8. Peripheral Select.............................................................................................................................. 9

6.2.9. Interrupt............................................................................................................................................ 9

7. GPIO Port B..................................................................................................................................................... 60

7.1. Register.................................................................................................................................................... 60

7.1.1. Register Map.................................................................................................................................... 60

7.1.2. GPIOBOUT...................................................................................................................................... 60

7.1.3. GPIOBOUTEN................................................................................................................................. 60

7.1.4. GPIOBDS......................................................................................................................................... 61

7.1. . GPIOBPU......................................................................................................................................... 61

7.1.6. GPIOBPD......................................................................................................................................... 62

7.1.7. GPIOBIN.......................................................................................................................................... 62

7.1.8. GPIOBPSEL..................................................................................................................................... 62

7.1.9. GPIOBINTP...................................................................................................................................... 63

7.1.10. GPIOBINTE.................................................................................................................................... 64

7.1.11. GPIOBINTF.................................................................................................................................... 64

7.1.12. GPIOBINTM................................................................................................................................... 6

7.2. Details of Operation................................................................................................................................. 66

7.2.1. Block Diagram.................................................................................................................................. 66

7.2.2. Configuration.................................................................................................................................... 66

7.2.3. GPIO B Block................................................................................................................................... 66

7.2.4. Input................................................................................................................................................. 66

7.2. . Output and Output Enable............................................................................................................... 66

7.2.6. Output Drive Strength...................................................................................................................... 66

7.2.7. Weak Pull Up and Pull Down........................................................................................................... 67

7.2.8. Peripheral Select.............................................................................................................................. 67

7.2.9. Interrupt............................................................................................................................................ 67

8. GPIO Port C..................................................................................................................................................... 68

8.1. Register.................................................................................................................................................... 68

8.1.1. Register Map.................................................................................................................................... 68

8.1.2. GPIOCOUT...................................................................................................................................... 68

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8.1.3. GPIOCOUTEN................................................................................................................................. 69

8.1.4. GPIOCIN.......................................................................................................................................... 69

8.1. . GPIOCINE....................................................................................................................................... 70

8.1.6. GPIOCINTP..................................................................................................................................... 71

8.1.7. GPIOCINTE..................................................................................................................................... 71

8.1.8. GPIOCINTF...................................................................................................................................... 72

8.1.9. GPIOCINTM..................................................................................................................................... 72

8.2. Details of Operation................................................................................................................................. 74

8.2.1. Block Diagram.................................................................................................................................. 74

8.2.2. Configuration.................................................................................................................................... 74

8.2.3. GPIO C Block................................................................................................................................... 74

8.2.4. Analog Input..................................................................................................................................... 74

8.2. . Output and Output Enable............................................................................................................... 74

8.2.6. Interrupt............................................................................................................................................ 74

9. GPIO Port D..................................................................................................................................................... 76

9.1. Register.................................................................................................................................................... 76

9.1.1. Register Map.................................................................................................................................... 76

9.1.2. GPIODO........................................................................................................................................... 76

9.1.3. GPIODOUTEN................................................................................................................................. 77

9.1.4. GPIODDS........................................................................................................................................ 77

9.1. . GPIODPU........................................................................................................................................ 78

9.1.6. GPIODPD........................................................................................................................................ 79

9.1.7. GPIODIN.......................................................................................................................................... 79

9.1.8. GPIODPSEL.................................................................................................................................... 80

9.1.9. GPIODINTP..................................................................................................................................... 81

9.1.10. GPIODINTE................................................................................................................................... 81

9.1.11. GPIODINTF.................................................................................................................................... 82

9.1.12. GPIODINTM................................................................................................................................... 82

9.2. Details of Operation................................................................................................................................. 84

9.2.1. Block Diagram.................................................................................................................................. 84

9.2.2. Configuration.................................................................................................................................... 84

9.2.3. GPIO D Block................................................................................................................................... 84

9.2.4. Input................................................................................................................................................. 84

9.2. . Output and Output Enable............................................................................................................... 84

9.2.6. Output Drive Strength...................................................................................................................... 8

9.2.7. Weak Pull Up and Pull Down........................................................................................................... 8

9.2.8. Peripheral Select.............................................................................................................................. 8

9.2.9. Interrupt............................................................................................................................................ 8

10. GPIO Port E................................................................................................................................................... 86

10.1. Register.................................................................................................................................................. 86

10.1.1. Register Map.................................................................................................................................. 86

10.1.2. GPIOEOUT.................................................................................................................................... 86

10.1.3. GPIOEOUTEN............................................................................................................................... 87

10.1.4. GPIOEDS....................................................................................................................................... 87

10.1. . GPIOEPU....................................................................................................................................... 88

10.1.6. GPIOEPD....................................................................................................................................... 89

10.1.7. GPIOEIN........................................................................................................................................ 89

10.1.8. GPIOEPSEL................................................................................................................................... 90

10.1.9. GPIOEINTP.................................................................................................................................... 91

10.1.10. GPIOEINTE.................................................................................................................................. 91

10.1.11. GPIOEINTF.................................................................................................................................. 92

10.1.12. GPIOEINTM................................................................................................................................. 92

10.2. Details of Operation............................................................................................................................... 94

10.2.1. Block Diagram................................................................................................................................ 94

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10.2.2. Configuration.................................................................................................................................. 94

10.2.3. GPIO E Block................................................................................................................................. 94

10.2.4. Input............................................................................................................................................... 94

10.2. . Output and Output Enable............................................................................................................. 94

10.2.6. Output Drive Strength.................................................................................................................... 94

10.2.7. Weak Pull Up and Pull Down......................................................................................................... 9

10.2.8. Peripheral Select............................................................................................................................ 9

10.2.9. Interrupt.......................................................................................................................................... 9

11. General Purpose Timer.................................................................................................................................. 96

11.1. Register.................................................................................................................................................. 96

11.1.1. Register Map.................................................................................................................................. 96

11.1.2. RTCCTL......................................................................................................................................... 96

11.1.3. RTCCDV........................................................................................................................................ 97

11.1.4. RTCCTR......................................................................................................................................... 97

11.2. Details of Operation................................................................................................................................ 98

11.2.1. Block Diagram................................................................................................................................ 98

11.2.2. Configuration.................................................................................................................................. 98

11.2.3. General Purpose Timer.................................................................................................................. 98

11.2.4. Access GPT Registers.................................................................................................................... 98

11.2. . GPT Clock...................................................................................................................................... 98

11.2.6. General Purpose Timer Mode........................................................................................................ 98

12. Timer A........................................................................................................................................................... 99

12.1. Register.................................................................................................................................................. 99

12.1.1. Register Map.................................................................................................................................. 99

12.1.2. TACTL.......................................................................................................................................... 100

12.1.3. TAPRD......................................................................................................................................... 101

12.1.4. TACTR......................................................................................................................................... 101

12.1. . TACC0CTRL................................................................................................................................ 101

12.1.6. TACC0CTR.................................................................................................................................. 101

12.1.7. TACC1CTRL................................................................................................................................ 102

12.1.8. TACC1CTR.................................................................................................................................. 102

12.1.9. TACC2CTRL................................................................................................................................ 102

12.1.10. TACC2CTR................................................................................................................................ 103

12.1.11. TACC3CTRL............................................................................................................................... 103

12.1.12. TACC3CTR................................................................................................................................ 103

12.1.13. TACC4CTRL.............................................................................................................................. 103

12.1.14. TACC4CTR................................................................................................................................ 104

12.1.1 . TACC CTRL.............................................................................................................................. 104

12.1.16. TACC CTR................................................................................................................................ 104

12.1.17. TACC6CTRL.............................................................................................................................. 10

12.1.18. TACC6CTR................................................................................................................................ 10

12.1.19. TACC7CTRL.............................................................................................................................. 10

12.1.20. TACC7CTR................................................................................................................................ 106

12.1.21. DTGA0CTL................................................................................................................................ 106

12.1.22. DTGA0LED................................................................................................................................ 106

12.1.23. DTGA0TED................................................................................................................................ 106

12.1.24. DTGA1CTL................................................................................................................................ 107

12.1.2 . DTGA1LED................................................................................................................................ 107

12.1.26. DTGA1TED................................................................................................................................ 107

12.1.27. DTGA2CTL................................................................................................................................ 107

12.1.28. DTGA2LED................................................................................................................................ 108

12.1.29. DTGA2TED................................................................................................................................ 108

12.1.30. DTGA3CTL................................................................................................................................ 108

12.1.31. DTGA3LED................................................................................................................................ 109

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12.1.32. DTGA3TED................................................................................................................................ 109

12.2. Details of Operation.............................................................................................................................. 110

12.2.1. Block Diagram.............................................................................................................................. 110

12.2.2. Configuration............................................................................................................................... 110

12.2.3. Timer A Block................................................................................................................................ 110

12.2.4. Timer............................................................................................................................................ 110

12.2. . Register update............................................................................................................................ 111

12.2.6. Timer Modes................................................................................................................................. 111

12.2.7. Single Shot Mode......................................................................................................................... 111

12.2.8. Input Clock And Pre-Scaler...........................................................................................................111

12.2.9. Timer Synchronization.................................................................................................................. 111

12.2.10. PWM/Compare Units.................................................................................................................. 112

12.2.11. Timer and PWM/Capture Interrupt.............................................................................................. 113

12.2.12. Dead-Time Generator................................................................................................................. 114

12.2.13. PWM Output and Capture Input Pin Selection...........................................................................116

13. Timer B......................................................................................................................................................... 117

13.1. Register................................................................................................................................................ 117

13.1.1. Register Map................................................................................................................................ 117

13.1.2. TBCTL.......................................................................................................................................... 117

13.1.3. TBPRD......................................................................................................................................... 118

13.1.4. TBCTR......................................................................................................................................... 118

13.1. . TBCC0CTRL................................................................................................................................ 118

13.1.6. TBCC0CTR.................................................................................................................................. 119

13.1.7. TBCC1CTRL................................................................................................................................ 119

13.1.8. TBCC1CTR.................................................................................................................................. 119

13.1.9. TBCC2CTRL................................................................................................................................ 120

13.1.10. TBCC2CTR................................................................................................................................ 120

13.1.11. TBCC3CTRL.............................................................................................................................. 120

13.1.12. TBCC3CTR................................................................................................................................ 121

13.1.13. DTGB0CTL................................................................................................................................ 121

13.1.14. DTGB0LED................................................................................................................................ 121

13.1.1 . DTGB0TED................................................................................................................................ 122

13.2. Details of Operation............................................................................................................................. 123

13.2.1. Block Diagram.............................................................................................................................. 123

13.2.2. Configuration................................................................................................................................ 123

13.2.3. Timer B Block............................................................................................................................... 123

13.2.4. Timer............................................................................................................................................ 123

13.2. . Register update............................................................................................................................ 124

13.2.6. Timer Modes................................................................................................................................ 124

13.2.7. Single Shot Mode......................................................................................................................... 124

13.2.8. Input Clock And Pre-Scaler..........................................................................................................124

13.2.9. Timer Synchronization.................................................................................................................. 124

13.2.10. PWM/Compare Units................................................................................................................. 12

13.2.11. Timer and PWM/Capture Interrupt..............................................................................................126

13.2.12. Dead-Time Generator................................................................................................................ 127

13.2.13. PWM Output and Capture Input Pin Selection...........................................................................129

14. Timer C......................................................................................................................................................... 130

14.1. Register................................................................................................................................................ 130

14.1.1. Register Map................................................................................................................................ 130

14.1.2. TCCTL.......................................................................................................................................... 130

14.1.3. TCPRD......................................................................................................................................... 131

14.1.4. TCCTR......................................................................................................................................... 131

14.1. . TCCC0CTRL................................................................................................................................ 131

14.1.6. TCCC0CTR.................................................................................................................................. 132

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14.1.7. TCCC1CTRL................................................................................................................................ 132

14.1.8. TCCC1CTR.................................................................................................................................. 132

14.1.9. DTGC0CTL.................................................................................................................................. 133

14.1.10. DTGC0LED................................................................................................................................ 133

14.1.11. DTGC0TED................................................................................................................................ 133

14.2. Details of Operation............................................................................................................................. 134

14.2.1. Block Diagram.............................................................................................................................. 134

14.2.2. Configuration............................................................................................................................... 134

14.2.3. Timer C Block............................................................................................................................... 134

14.2.4. Timer............................................................................................................................................ 134

14.2. . Register update............................................................................................................................ 13

14.2.6. Timer Modes................................................................................................................................ 13

14.2.7. Single Shot Mode......................................................................................................................... 13

14.2.8. Input clock and Pre-scaler............................................................................................................ 13

14.2.9. Timer synchronization.................................................................................................................. 13

14.2.10. PWM/Compare Units................................................................................................................. 136

14.2.11. Timer and PWM/Capture Interrupt..............................................................................................137

14.2.12. Dead-Time Generator................................................................................................................ 138

14.2.13. PWM Output and Capture Input Pin Selection...........................................................................140

1 . Timer D......................................................................................................................................................... 141

1 .1. Register................................................................................................................................................ 141

1 .1.1. Register Map................................................................................................................................ 141

1 .1.2. TDCTL.......................................................................................................................................... 141

1 .1.3. TDPRD......................................................................................................................................... 142

1 .1.4. TDCTR......................................................................................................................................... 142

1 .1. . TDCC0CTL.................................................................................................................................. 142

1 .1.6. TDCC0CTR.................................................................................................................................. 143

1 .1.7. TDCC1CTRL................................................................................................................................ 143

1 .1.8. TDCC1CTR.................................................................................................................................. 143

1 .1.9. DTGD0CTL.................................................................................................................................. 144

1 .1.10. DTGD0LED................................................................................................................................ 144

1 .1.11. DTGD0TED................................................................................................................................ 144

1 .2. Details of Operation............................................................................................................................. 14

1 .2.1. Block Diagram.............................................................................................................................. 14

1 .2.2. Configuration............................................................................................................................... 14

1 .2.3. Timer D Block............................................................................................................................... 14

1 .2.4. Timer............................................................................................................................................ 14

1 .2. . Register Update........................................................................................................................... 146

1 .2.6. Timer Modes................................................................................................................................ 146

1 .2.7. Single Shot Mode......................................................................................................................... 146

1 .2.8. Input Clock And Pre-Scaler..........................................................................................................146

1 .2.9. Timer Synchronization.................................................................................................................. 146

1 .2.10. PWM/Compare Units................................................................................................................. 147

1 .2.11. Timer and PWM/Capture Interrupt..............................................................................................148

1 .2.12. Dead-Time Generator................................................................................................................ 148

1 .2.13. PWM Output and Capture Input Pin Selection...........................................................................1 0

16. FLASH Memory Controller........................................................................................................................... 1 1

16.1. Register................................................................................................................................................ 1 1

16.1.1. Register Map................................................................................................................................ 1 1

16.1.2. FLASHLOCK................................................................................................................................ 1 1

16.1.3. FLASHCTL................................................................................................................................... 1 2

16.1.4. FLASHPAGE................................................................................................................................ 1 2

16.1. . FLASHPERASE........................................................................................................................... 1 3

16.1.6. SWDACCESS.............................................................................................................................. 1 3

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16.1.7. FLASHWSTATE........................................................................................................................... 1 3

16.1.8. FLASHBWRITE............................................................................................................................ 1 3

16.1.9. FLASHBWDATA........................................................................................................................... 1 4

16.2. Details of Operation............................................................................................................................. 1

16.2.1. Block Diagram.............................................................................................................................. 1

16.2.2. Configuration................................................................................................................................ 1

16.2.3. FLASH Memory............................................................................................................................ 1

16.2.4. Writing to FLASH Controller Registers.........................................................................................1

16.2. . FLASH Wait State........................................................................................................................ 1

16.2.6. FLASH Page Erase...................................................................................................................... 1 6

16.2.7. Write to FLASH............................................................................................................................ 1 6

16.2.8. Buffered Write to FLASH.............................................................................................................. 1 6

16.2.9. SWD Debug Access Disable........................................................................................................ 1 7

17. ADC and AUTO SEQUENCER.................................................................................................................... 1 8

17.1. Register................................................................................................................................................ 1 8

17.1.1. Register Map................................................................................................................................ 1 8

17.1.2. EMUXCTL.................................................................................................................................... 1 9

17.1.3. EMUXDATA.................................................................................................................................. 160

17.1.4. ADCCTL....................................................................................................................................... 161

17.1. . ADCCR........................................................................................................................................ 161

17.1.6. ADCINT........................................................................................................................................ 162

17.1.7. AS0CTL........................................................................................................................................ 163

17.1.8. AS0S0.......................................................................................................................................... 164

17.1.9. AS0R0.......................................................................................................................................... 164

17.1.10. AS0S1........................................................................................................................................ 164

17.1.11. AS0R1........................................................................................................................................ 16

17.1.12. AS0S2........................................................................................................................................ 16

17.1.13. AS0R2........................................................................................................................................ 16

17.1.14. AS0S3........................................................................................................................................ 166

17.1.1 . AS0R3........................................................................................................................................ 166

17.1.16. AS0S4........................................................................................................................................ 166

17.1.17. AS0R4........................................................................................................................................ 167

17.1.18. AS0S ........................................................................................................................................ 167

17.1.19. AS0R ........................................................................................................................................ 167

17.1.20. AS0S6........................................................................................................................................ 168

17.1.21. AS0R6........................................................................................................................................ 168

17.1.22. AS0S7........................................................................................................................................ 168

17.1.23. AS0R7........................................................................................................................................ 169

17.1.24. AS1CTL...................................................................................................................................... 169

17.1.2 . AS1S0........................................................................................................................................ 170

17.1.26. AS1R0........................................................................................................................................ 170

17.1.27. AS1S1........................................................................................................................................ 171

17.1.28. AS1R1........................................................................................................................................ 171

17.1.29. AS1S2........................................................................................................................................ 171

17.1.30. AS1R2........................................................................................................................................ 172

17.1.31. AS1S3........................................................................................................................................ 172

17.1.32. AS1R3........................................................................................................................................ 172

17.1.33. AS1S4........................................................................................................................................ 173

17.1.34. AS1R4........................................................................................................................................ 173

17.1.3 . AS1S ........................................................................................................................................ 173

17.1.36. AS1R ........................................................................................................................................ 174

17.1.37. AS1S6........................................................................................................................................ 174

17.1.38. AS1R6........................................................................................................................................ 174

17.1.39. AS1S7........................................................................................................................................ 17

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17.1.40. AS1R7........................................................................................................................................ 17

17.2. Details of Operation............................................................................................................................. 17

17.2.1. Block Diagram.............................................................................................................................. 17

17.3. Details of Operation............................................................................................................................. 17

17.3.1. Basic Configuration...................................................................................................................... 17

17.3.2. ADC, Autosequencer and EMUX..................................................................................................176

17.3.3. Clock Setting................................................................................................................................ 176

17.3.4. ADC.............................................................................................................................................. 177

17.3. . EMUX........................................................................................................................................... 177

17.3.6. Auto Sequencer ASC0, ASC1......................................................................................................177

18. I2C................................................................................................................................................................ 182

18.1. Register................................................................................................................................................ 182

18.1.1. Register Map................................................................................................................................ 182

18.1.2. I2CCFG........................................................................................................................................ 182

18.1.3. I2CSTATUS.................................................................................................................................. 182

18.1.4. I2CIE............................................................................................................................................ 184

18.1. . I2CMCTRL................................................................................................................................... 184

18.1.6. I2CMRXDATA.............................................................................................................................. 18

18.1.7. I2CMTXDATA............................................................................................................................... 18

18.1.8. I2CBAUD..................................................................................................................................... 18

18.1.9. I2CSLRXDATA............................................................................................................................. 18

18.1.10. I2CSLTXDATA............................................................................................................................ 186

18.1.11. I2CADDR.................................................................................................................................... 186

18.2. Details of Operation............................................................................................................................. 187

18.2.1. Block Diagram.............................................................................................................................. 187

18.2.2. Configuration............................................................................................................................... 187

18.2.3. I2C............................................................................................................................................... 187

18.2.4. I2C Clock setting.......................................................................................................................... 187

18.2. . I2C Addressing............................................................................................................................. 188

18.2.6. I2C Master Read Transactions.....................................................................................................188

19. UART........................................................................................................................................................... 191

19.1. Register................................................................................................................................................ 191

19.1.1. Register Map................................................................................................................................ 191

19.1.2. UARTRXTX/UARTDL_L............................................................................................................... 191

19.1.3. UARTIER/UARTDL_H..................................................................................................................192

19.1.4. UARTIIR....................................................................................................................................... 192

19.1. . UARTLCR.................................................................................................................................... 193

19.1.6. UARTMCR................................................................................................................................... 193

19.1.7. UARTLSR.................................................................................................................................... 193

19.1.8. UARTSP....................................................................................................................................... 194

19.1.9. UARTFCTL2................................................................................................................................ 194

19.1.10. UARTIER2................................................................................................................................. 19

19.1.11. UARTDL_L2............................................................................................................................... 19

19.1.12. UARTDL_H2.............................................................................................................................. 19

19.1.13. UARTFD_F................................................................................................................................ 19

19.1.14. UARTSTAT................................................................................................................................. 19

19.2. Details of Operation............................................................................................................................. 197

19.2.1. Block Diagram.............................................................................................................................. 197

19.2.2. Configuration............................................................................................................................... 197

19.2.3. UART........................................................................................................................................... 197

19.2.4. UART Clock Rate Setting.............................................................................................................197

19.2. . Data settings................................................................................................................................ 199

19.2.6. FIFO Settings............................................................................................................................... 199

19.2.7. Error Checking on Received Data................................................................................................199

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Power Application Controller

20. SOC Bus bridge........................................................................................................................................... 200

20.1. Register................................................................................................................................................ 200

20.1.1. Register Map................................................................................................................................ 200

20.1.2. SOCBCTL.................................................................................................................................... 200

20.1.3. SOCBCFG................................................................................................................................... 200

20.1.4. SOCBCLKDIV.............................................................................................................................. 201

20.1. . SOCBSTAT.................................................................................................................................. 201

20.1.6. SOCBCSSTR............................................................................................................................... 202

20.1.7. SOCBD........................................................................................................................................ 203

20.1.8. SOCBINT_EN.............................................................................................................................. 203

20.2. Details of Operation............................................................................................................................. 204

20.2.1. Block Diagram.............................................................................................................................. 204

20.2.2. Configuration............................................................................................................................... 204

20.2.3. SOC Bridge.................................................................................................................................. 204

20.2.4. SOC Bridge Clock Rate Setting................................................................................................... 204

20.2. . Enable and Setup of SOC Bridge................................................................................................. 20

20.2.6. SOC Interrupt............................................................................................................................... 20

20.2.7. SOC Bridge Protocol.................................................................................................................... 20

20.2.8. Reading from SOC Bridge........................................................................................................... 20

20.2.9. Writing to SOC Bridge.................................................................................................................. 20

21. SPI............................................................................................................................................................... 206

21.1. Register................................................................................................................................................ 206

21.1.1. Register Map................................................................................................................................ 206

21.1.2. SPICTL........................................................................................................................................ 206

21.1.3. SPICFG........................................................................................................................................ 207

21.1.4. SPICLKDIV.................................................................................................................................. 208

21.1. . SPISTAT....................................................................................................................................... 208

21.1.6. SPICSSTR................................................................................................................................... 210

21.1.7. SPID............................................................................................................................................. 211

21.1.8. SPIINT_EN................................................................................................................................... 211

21.2. Details of Operation............................................................................................................................. 212

21.2.1. Block Diagram.............................................................................................................................. 212

21.2.2. Configuration............................................................................................................................... 212

21.2.3. SPI............................................................................................................................................... 212

21.2.4. SPI Clock Rate Setting................................................................................................................. 212

21.2. . Master Slave Mode...................................................................................................................... 213

21.2.6. Clock Phase, Polarity................................................................................................................... 213

21.2.7. SPI Early Data Transmit............................................................................................................... 213

21.2.8. Data Format................................................................................................................................. 214

21.2.9. Chip Select Settings..................................................................................................................... 21

21.2.10. Auto Retransmit Data Word........................................................................................................ 21

21.2.11. Loop Back Mode........................................................................................................................ 21

21.2.12. SPI Interrupt............................................................................................................................... 216

21.2.13. SPI Enable................................................................................................................................. 216

22. Multi-Mode Power Manager......................................................................................................................... 217

22.1. Register................................................................................................................................................ 217

22.1.1. Register Map................................................................................................................................ 217

22.1.2. SYSTAT........................................................................................................................................ 217

22.1.3. DEVID.......................................................................................................................................... 218

22.1.4. VERID.......................................................................................................................................... 218

22.1. . PWRCTL...................................................................................................................................... 218

22.1.6. PWRSTAT.................................................................................................................................... 219

22.1.7. PSTATSET................................................................................................................................... 219

22.1.8. IMOD............................................................................................................................................ 220

- 10 - Rev 18‒March 4, 2018