TABLE OF CONTENTS
Section Title Page
1Introduction ............................................................................................................1
1.1 General........................................................................................................................................1
1.2 How This Manual is Organized.................................................................................................2
1.3 Applicable Documents ..............................................................................................................2
1.3.1 Industry Documents.................................................................................................................2
1.3.2 Product Specific Documents....................................................................................................2
2Instalation ...............................................................................................................3
2.1 Preparation and Precaution for Installation ............................................................................3
2.2 Installation Instructions.............................................................................................................3
2.3 Connecting to Other Devices....................................................................................................4
2.3.1 AFDX Connection....................................................................................................................5
2.3.2 Trigger, Discrete and IRIG Connector.....................................................................................5
2.3.3 AXC-FDX-2 Rear I/O Interface................................................................................................7
3Structure of the AXC-FDX-2...................................................................................9
3.1 System on Chip (SoC) .............................................................................................................11
3.1.1 Ethernet MAC Features.........................................................................................................11
3.1.2 PCI-Express Bus and DMA Engine.......................................................................................11
3.1.3 IRIG- and Time Code Section................................................................................................12
3.1.3.1 IRIG-B Synchronization Unit.........................................................................................12
3.1.3.2 Timecode Encoder/Decoder .........................................................................................12
3.1.4 Application Specific Processor ..............................................................................................13
3.1.5 BIU Processor........................................................................................................................13
3.1.6 Memory Interface...................................................................................................................13
3.2 Gigabit Ethernet Phyter...........................................................................................................13
3.3 External Trigger Inputs and Outputs .....................................................................................14
3.4 User programmable Discrete I/O............................................................................................14
4Technical Data......................................................................................................17
5NOTES...................................................................................................................21
5.1 Acronyms..................................................................................................................................21
6Certificate of Volatility..........................................................................................23
