Alinx KINTEX-7 FPGA Bedienungsanleitung

KINTEX-7 FPGA

Development Board

AV7K300

User Manual

KINTEX-7 FPGA Development Board AV7K300 User Manual

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Version Record

Version

Date

Release By

Rev 1.1

2022-09-07

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Table of Contents

Version Record ............................................................................................. 2

Part 1: FPGA Development Board Introduction ...........................................5

Part 2: AC7K325B Core Board .....................................................................8

Part 2.1: AC7K325 Core Board Introduction ........................................ 8

Part 2.2: FPGA Chip ..............................................................................9

Part 2.3: DDR3 DRAM ........................................................................ 10

Part 2.4: QSPI Flash ........................................................................... 14

Part 2.5: Clock Configuration ..............................................................15

Part 2.5.1: 200Mhz Active Differential clock .......................................15

Part 2.5.2: GTX Reference Clock ....................................................... 16

Part 2.6: LED Light on Core Board .....................................................17

Part 2.7: Power Supply ....................................................................... 17

Part 2.8: Size Dimension .................................................................... 19

Part 2.9: Board to Board Connectors pin assignment ....................... 19

Part 3: Carrier Board .................................................................................. 27

Part 3.1: Carrier Board Introduction ....................................................27

Part 3.2: SFP Interface ....................................................................... 28

Part 3.3.: PCIe Card Slot .................................................................... 29

Part 3.4: SDI Output Interface ............................................................ 31

Part 3.5: SDI Input Interface............................................................... 33

Part 3.6: USB to Serial Port ................................................................ 34

Part 3.7: SD Card Slot ........................................................................ 34

Part 3.9: 40-Pin Expansion Port ......................................................... 35

Part 3.9: Keys and LEDs .....................................................................37

Part 3.10: JTAG debug port ................................................................ 39

Part 3.11: Power Supply ..................................................................... 39

Part 3.12: Size Dimension .................................................................. 41

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The AV7K300 FPGA development board, it is the XILINX KINTEX-7 FPGA

development platform.

The AV7K300 FPGA development platform uses XILINX's KINTEX-7 chip

XC7K325 solution. The FPGA development board mounts four pieces of

512MB high-speed DDR3 SDRAM chips, and a 128Mb QSPI FLASH chip.

In the design of expansion board, we have extended a wealth of interfaces

for users, such as 1 PCIex8 interface, 4 SFP interface, 2 SDI Output Interface,

2 SDI Input Interface,1 UART serial port, 1 SD card slot, 2 40-pin expansion

ports. It meets users' requirements for high-speed data exchange, data storage,

video transmission processing and industrial control. It is a "professional"

FPGA development platform, for high-speed data transmission and exchange,

pre-verification and post-application of data processing is possible. This

product is very suitable for students, engineers and other groups engaged in

KINTEX-7FPGA development.

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Part 1: FPGA Development Board Introduction

The entire structure of the development board is designed by inheriting our

usual core board + expansion board model. Use high-speed inter-board

connectors to connect between the core board and the expansion board.

The core board is the smallest system mainly composed of XC7K325 + 4

DDR3 + QSPI FLASH. Adopt Xilinx's KINTEX-7 series chip, model

XC7K325TFFG900. Four DDR3 memory chips are connected to the HP port of

the FPGA chip. Each DDR3 has a capacity of up to 512M bytes, forming a

64-bit data bandwidth. A 128Mb QSPI FLASH is used to statically store the

configuration file of the FPGA chip or other user data.

The carrier board expands a wealth of peripheral interfaces for the core

board, including 1 PCIex8 interface, 4 SFP interfaces, 2 SDI Output interface, 2

SDI Input interface, 2 40-pin expansion interface and some keys LEDs.

Figure 1-1: The Schematic Diagram of the AV7K300

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Through this diagram, you can see the interfaces and functions that the

AV7K300 FPGA Development Board contains:

FPGA Core Board

The smallest system consisting of XC7K325 + 4 DDR3 + QSPI FLASH,

there are two crystal oscillators to provide the clock, a single-ended

200MHz crystal oscillator provides the DDR control reference clock of

the FPGA logic, and the other differential 125MHz crystal oscillator

provides the GTX transceiver reference clock.

PCIe x8 interface

It supports the PCI Express 2.0 standard, provides a standard PCIe x8

high-speed data transmission interface, and the single-channel

communication rate can be as high as 5GBaud.

4 SFP interfaces

The four high-speed transceivers of the GTX transceiver of the FPGA

are connected to the transmission and reception of four optical modules

to realize four high-speed optical fiber communication interfaces. Each

fiber optic data communication receives and transmits at speeds of up

to 10 Gb/s.

SDI Video Output

2 channels of SDI video output interface, used SEMTECH's GV8500

SDI driver chip, which supports different formats of data output HDcctv

1.0, HD-SDI (ST 292), 3G_SDI (ST-424) and SD_SDI (ST259).

SDI Video Input

2 channels of SDI video input interface, used SEMTECH's GV8601 SDI

equalizer chip, which supports different formats of data input HDcctv 1.0,

HD-SDI (ST 292), 3G_SDI (ST-424) and SD_SDI (ST259). The input

interface is adaptive to video reception at three rates.

USB Uart Interface

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1 Uart to USB interface, used for communication with computer,

convenient for users to debug. The serial port chip adopts Silicon Labs

CP2102GM USB-UART chip, and the USB interface adopts MINI USB

interface.

Micro SD slot

1 Micro SD card slot, used to store operating system image and file

system.

40-pin expansion port

Two 40-pin 0.1 spacing pitch expansion port can be connected to

various ALINX modules (binocular camera, TFT LCD screen,

high-speed AD module, etc.). Expansion ports include 1 5V power

supply, 2 3.3V power supplies, 3 ground, and 34 IO ports.

JTAG Interface

A 10-pin 0.1 spacing standard JTAG ports for FPGA program download

and debugging. Users can debug and download FPGA through XILINX

down loader.

LED Light

7 LEDs, 2 LEDs on the core board and 7 LEDs on the carrier board. 1

power indicator on the core board; 1 DONE configuration indicator.

There are 1 power indicator light, 4 user indicator lights and 2 serial

port indicator lights on the carrier board.

Key

4 user keys on the carrier board

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Part 2: AC7K325B Core Board

Part 2.1: AC7K325 Core Board Introduction

AC7K325B (core board model, the same below) FPGA core board, it is

based on XILINX Kintex-7 XC7K325 series chip XC7K325TFFG900100T. The

core board uses 4 Micron's 512MB DDR3 chips MT41J256M16HA-125, with a

total capacity of 2GB. In addition, a 128MBit QSPI FLASH is also integrated on

the core board for boot storage configuration and system files.

The four board-to-board connectors of the core board AC7K325B expand

276 IOs, of which 92 IO levels of BANK17 and BANK18 can be modified by

replacing the LDO chip on the core board to meet the user's requirement of no

level interface; In addition, the core board also extended 16 pairs of high-speed

transceiver GTX interfaces. For users who need a lot of IO, this core board will

be a good choice. And the IO connection part, the FPGA chip to the interface

between the equal length and differential processing, and the core board size is

only 80 * 60 (mm), very suitable for secondary development.

Figure 2.1-1: AC7K325B Core Board (Front View)

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Part 2.2: FPGA Chip

As mentioned above, the FPGA model we use is XC7K325T-2FFG900I,

which belongs to Xilinx's KINTEX-7 series. The speed grade is 2, and the

temperature grade is industry grade. This model is a FGG900 package with

900 pins. Xilinx KINTEX-7 FPGA chip naming rules as below

Figure 2.2-1: The Specific Chip Model Definition of Kintex-7 Series

Figure 2.2-2: FPGA chip on board

The main parameters of the FPGA chip XC7K325T are as follows

Name

Specific parameters

Logic Cells

326,080

Slices

50,950

CLB flip-flops

407,600

Block RAM（kb）

16,020

DSP Slices

840

PCIe Gen2

XADC

1 XADC, 12bit, 1Mbps AD

GTP Transceiver

16 GTP, 12.5Gb/s max

Speed Grade

-2

Temperature Grade

Industrial

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Part 2.3: DDR3 DRAM

The FPGA core board AC7K325B is equipped with four Micron 4Gbit

(512MB) DDR3 chips, model MT41J256M16HA-125 (compatible with

MT41K256M16HA-125). Four DDR3 SDRAMs make up a 64-bit bus width.

Because 4 DDR3 chips are connected to the HP port of the FPGA, the

maximum operating speed of DDR3 SDRAM can reach 800MHz (data rate

1600Mbps). Four DDR3 memory systems are directly connected to the

BANK32, BANK33, and BANK34 interfaces of the FPGA. The specific

configuration of DDR3 SDRAM is shown in Table 2.3-1 below.

Bit Number

Chip Model

Capacity

Factory

U4,U5, U6, U7

MT41K256M16HA-125 or

MT41J256M16HA-125

256M x 16bit

Micron

Table 2.3-1: DDR3 SDRAM Configuration

The hardware design of DDR3 requires strict consideration of signal

integrity. We have fully considered the matching resistor/terminal resistance,

trace impedance control, and trace length control in circuit design and PCB

design to ensure high-speed and stable operation of DDR3.

Figure 2.3-1: The DDR3 DRAM Schematic

DDR3 DRAM pin assignment:

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