Allegro APEK85110-D1-E Bedienungsanleitung
APEK85110D1-E-UM
Description
The Allegro APEK85110-D1-E Half-Bridge Driver Switch Board is a demo board containing two AHV85110 GaN FET driv-
ers and two GaN FETs in a half-bridge configuration.
Figure 1: APEK85110 Evaluation Board
The APEK85110 can be used to perform double pulse tests (see Double Pulse Test section) or to interface the half bridge to
an existing LC power section, as shown below.
The isolated AHV85110 driver does not require secondary-side power or bootstrap components. Gate drive power is supplied
to the secondary side from the primary-side supply voltage, VDRV. The amplitude of the gate drive can be varied by varying
VDRV between 7 and 15 V.
Half-Bridge Driver Switch Board User Manual
APEK85110-D1-E
August 30, 2022
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Allegro MicroSystems
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www.allegromicro.com
DANGER
DO NOT TOUCH THE BOARD WHEN IT IS ENERGIZED AND ALLOW ALL COMPONENTS TO DISCHARGE
COMPLETELY PRIOR HANDLING THE BOARD.
HIGH VOLTAGE CAN BE EXPOSED ON THE BOARD WHEN IT IS CONNECTED TO POWER SOURCE. EVEN
BRIEF CONTACT DURING OPERATION MAY RESULT IN SEVERE INJURY OR DEATH.
Ensure that appropriate safety procedures are followed. This evaluation kit is designed for engineering evaluation
in a controlled lab environment and should be handled by qualified personnel ONLY. Never leave the board
operating unattended.
WARNING
Some components can be hot during and after operation. There is NO built-in electrical or thermal protection on
this evaluation kit. The operating voltage, current, and component temperature should be monitored closely during
operation to prevent device damage.
CAUTION
This product contains parts that are susceptible to damage by electrostatic discharge (ESD). Always follow ESD
prevention procedures when handling the product.
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955 Perimeter Road
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Quick Start Guide
Figure 2: APEK85110 Quick Start
1. Apply VDRV = 12 V
2. Link pins EN_PU and EN (if not using external Enable control)
3. Apply input gate signals, with adequate dead time, to the IN_L and IN_H inputs.
4. Convenient test points are located on the test board as shown above. A suitable dierential oscilloscope should be used to monitor
the high-side gate signal from VGH to VSW.
Gate Pull-Up and Pull-Down Resistors
The AHV85110 gate driver has independent outputs for the gate pull-up and gate pull-down allowing control of the on and off rise and
fall times.
The default values for these resistors are:
• OUTPU: R1 and R5 = 10 Ω
• OUTPD: R3 and R7 = 1 Ω
These values can be modified to suit the application.
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Enable and Start Sequence
The AHV85110 has an open-drain enable pin (EN) to facilitate a system level wired-AND startup.
When the enable pin is externally pulled low, the driver is forced into a low-power mode. The driver output is pulled low in this mode.
In the event of an internal fault condition, such as UVLO, this pin is actively pulled low internally by the driver. During normal opera-
tion, the pin is released by the driver, and must be pulled high with an external pull-high resistor. This functionality can be used by the
PWM controller to indicate that it can start sending IN pulses to the driver. It is typically wired-AND with the controller enable pin as
shown in Figure 3.
The APEK85110 evaluation board provides direct access to the EN pin on connector CONN1. Internally the board contains a 100 kΩ
pull-up resistor connected from VDRV to the EN_PU pin on connector CONN1—see schematic in Figure 12. If external control of the
enable function is not required, pins EN and EN_PU must be linked together on CONN1 to make use of the internal 100 kΩ pull-up
resistor to enable the driver. If the EN pin is left floating, the drivers will not respond to INL or INH input signals.
Figure 3: AHV85110 Wired-AND Enable
The start up sequence of the AHV85110 is shown in Figure 4. Time tSTART is defined as the time after which VDRV reaches the
UVLO rising level to the AHV85110 releasing the EN internal pull down.
IMPORTANT: the IN signal must not be applied before the EN pin has been released.
Figure 4: AHV85110 Start-Up Sequence
AHV85110
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Measurement Points
The APEK85110 evaluation board contains convenient test points for monitoring the high- and low-side gate drives as well as the
switch node as shown in Figure 5.
When measuring VGS_H, use a differential probe with suitable ratings for the applied bus voltage. The APEK85110 evaluation board
uses a bipolar gate drive arrangement as shown in Figure 6. When measuring VGS, both gate drives are measured relative to the source
of their associated GaN FET. Therefore, the off-state voltage will be negative.
It is important to use a low-inductance scope probe ground lead as shown to avoid pickup of spurious switching noise.
Figure 5: Measurements Points
Bipolar Gate Drive
Due to the high rate of change of voltages and currents in power switching circuits, unwanted inductor currents and capacitor voltage
drops can be created.
One such example is the false turn on of a FET due to a dv/dt event. In a half-bridge circuit, after the low-side FET has been turned
off and a suitable dead-time has elapsed, the high-side FET is turned on. This produces a rapidly changing switch node voltage at the
drain of the low-side FET. This voltage will produce a capacitor current,
iCGD = CGD × (dVDS_L / dt)
flowing in the gate-drain capacitance, CGD, and driver output. It will cause the voltage on the gate of the low-side FET to rise. If this
voltage spike peaks beyond the threshold voltage, VTH, the FET will conduct. Considering that the high-side FET is also conducting,
this can result in a potentially destructive shoot-through event.
The APEK85110 evaluation board uses a bipolar gate drive arrangement which is useful to mitigate against the effects of gate-drain
capacitor currents. The secondary supply voltage, VSEC, is a function of the primary supply voltage, VDRV. The zener diode, CR1, will
regulate the positive turn-on voltage of the GaN FET. During the turn-off of period, the gate voltage will be negative with a value of:
VGS_OFF = VSEC – VZENER. VSEC is typically 9 V.
This negative VGS_OFF voltage allows more margin before the threshold voltage can be reached.
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955 Perimeter Road
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Figure 6: Bipolar Gate Drive Schematic
Propagation Delay
• VDRV = 12 V
• Input = 100 kHz
• RPU = 10 Ω, RPD = 1 Ω
• Power train unloaded, i.e., VHV+ = 0 V.
Figure 7: Typical Driver Output at 100 kHz
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955 Perimeter Road
Manchester, NH 03103-3353 U.S.A.
www.allegromicro.com
Double Pulse Test
Theory
The double pulse test is used to evaluate the switching characteristics of a power switch under hard switching but in a safe manner.
For a low-side switch, the set up is as shown below:
AHV85110
AHV85110
RPU
RPD
RPU
RPD
VBUS
C
L
IDS
1 2 3
1
2
3
Figure 8: Double Pulse Test
The low-side switch is driven with two pulses as shown below. The high-side switch can be held off or driven with the inverse of the
low-side gate switch (with adequate dead time).
Figure 9: Double Pulse Test Waveforms
An inductor is placed in parallel with the high-side switch. The goal of this inductor is to establish the test level current in the low-side
switch at the end of the first on pulse (1). The magnitude of the test level current at the end of period 1 is given by:
IL= (VBUS × tON_1) / L
During period 2, the inductor current will naturally decay. The duration of period 2 should not be too long that inductor current devi-
ates significantly from the desired test level.
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955 Perimeter Road
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www.allegromicro.com
During period 3, the inductor current will again rise. Period 3 should not be so long that the inductor current rises to an excessive
level.
The falling edge of pulse 1 is used to examine the hard turn-off characteristics of the switch. The rising edge of pulse 3 is used to
examine the hard turn-on characteristics of the switch. By only applying these two pulses, the switches are only on for a very short
time and should not overheat.
Test Results
Components
Drivers: Allegro AHV85110
Inductor: 49 µH, 360 mΩ Air Core
RPU:10 Ω
RPD:1 Ω
DPT Result 100 V, 15 A
Figure 10: DPT 100 V, 15 A
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955 Perimeter Road
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www.allegromicro.com
DPT Result 400V – 62A
Figure 11: DPT 400 V, 62 A
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955 Perimeter Road
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www.allegromicro.com
APEK85110 SCHEMATIC
Figure 12: APEK85110 Schematic
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