AMD XILINX T2 Telco Bedienungsanleitung

T2 Telco Accelerator Card

User Guide

UG1496 (v1.0) June 15, 2022

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Table of Contents

Chapter 1: Introduction.............................................................................................. 3

Hardware Overview.....................................................................................................................4

Software Overview...................................................................................................................... 5

Zynq UltraScale+ RFSoC Specification.......................................................................................5

Chapter 2: Features....................................................................................................... 7

Chapter 3: Pin Mapping...............................................................................................9

PCIe Interface.............................................................................................................................. 9

DDR4 PL Interface..................................................................................................................... 11

DDR4 PS Interface..................................................................................................................... 15

Special Functions.......................................................................................................................18

Chapter 4: Maintenance Port.................................................................................21

Chapter 5: Power...........................................................................................................22

Chapter 6: Xilinx Design Constraints (XDC) File.......................................... 23

Appendix A: Regulatory Compliance Statements...................................... 24

FCC Class A Products.................................................................................................................24

Safety.......................................................................................................................................... 24

EMC Compliance........................................................................................................................25

FCC Class A User Information..................................................................................................25

VCCI Class A Statement............................................................................................................ 26

Appendix B: Additional Resources and Legal Notices............................. 27

Xilinx Resources.........................................................................................................................27

Documentation Navigator and Design Hubs.........................................................................27

References..................................................................................................................................28

Revision History.........................................................................................................................28

Please Read: Important Legal Notices................................................................................... 28

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T2 Telco Accelerator Card User Guide 2

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Chapter 1

Introduction

The Xilinx® T2 Telco accelerator card, shown in the following gure, is a single slot, half height,

half length (HHHL) plug-in card. It is compliant with PCI Express® technology, supporng PCIe

Gen3 x16 and Gen4 x8 bifurcated rates on the host interface.

Figure 1: T2 Telco Accelerator Card

The card features a 16 nm Zynq® UltraScale+™ RFSoC ZU48DR device supporng the following

targeted applicaons:

• 5G NR physical layer funconal ooad, including but not limited to:

○Low-density parity check (LDPC) encoding and decoding

○Rate matching and dematching

○Code block (CB) and CB group (CBG) processing with HARQ buer management logic in

lookaside mode

• 4G LTE physical layer funconal ooad, including but not limited to:

○Turbo encoding and decoding

○Rate matching and dematching

Chapter 1: Introduction

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○CB processing with HARQ buer management in lookaside mode

Note: The Zynq UltraScale+ RFSoC ZU48DR device also supports concurrent 4G LTE/5G NR L1 ooad,

assuming that the necessary hardware resources are available.

The T2 card value proposion is in ooading CPU intensive encode and decode computaons

involving LDPC operaons, thereby reducing costly CPU resources. The Zynq UltraScale+ RFSoC

has hard IP blocks for SD-FEC (eight SD-FEC cores per device) which can be congured to run

LDPC encode and decode operaons.

Hardware Overview

The following high-level block diagram of the T2 card provides an overview of the hardware

features.

Figure 2: T2 Card High-Level Block Diagram

Zynq UltraScale+ RFSoC

SC MSP432

Power

Supply

Unit

NOR

Flash

PL DDR

Controller

(Bank 67,

68, 69)

PS MIO

(Bank

500)

PL GTY PCIe 4

(Bank 128, 129, 130, 131)

HHHL Single Slot

PCIe Gen3 x16 /

PCIe Gen4 x8 Bifurcated

XCZU48DR- 2FSVG1517E

PS DDR

Controller

(Bank 504)

Debug Connector

1GB

DDR4

x16

1GB

DDR4

x16

1GB

DDR4

x16

ECC x8

1GB

DDR4

x16

1GB

DDR4

x16

1GB

DDR4

x16

ECC x8

OSC

50 MHz

OSC

300 MHz

12V 3.3V

8x SD-FEC

(LDPC/Turbo)

X25345-051221

The T2 card hardware features are as follows:

• Zynq UltraScale+ RFSoC device targeng L1 channel coding

• NOR ash (2x 256 MB in dual QSPI mode) for ZU48DR Zynq UltraScale+ RFSoC image

storage

Chapter 1: Introduction

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• 4 GB of DDR4 programmable logic (PL) memory

• 2 GB of DDR4 processor system (PS) memory

• MSP432-based satellite controller (SC) for card monitoring and telemetry

• PCIe Gen 3 x16 or Gen 4 x8 bifurcated host interface

• Low prole (HHHL) single slot (111.15 mm x 167.65 mm) form factor with a 60W power

envelope

• DMB II maintenance and debug port for card maintenance and developer support funcons

Note: The proprietary DMB II interface requires a Xilinx ADK dongle.

Software Overview

The T2 card has a factory image installed that together with the provided host soware

installaon supports the following funcons:

• PCIe Gen3 x16 interface

• User ash image update

• SC rmware update

• DDR4 PL BERT performance and diagnoscs test

• DDR4 PS BERT performance and diagnoscs test

• PCIe performance and diagnoscs test

• In-band telemetry

Zynq UltraScale+ RFSoC Specification

The Zynq UltraScale+ RFSoC device on the T2 card is a XCZU48DR-2FSVG1517E. A comparison

of the features of this device relave to other devices in the same family is shown in the

following gure. Refer to the Zynq® UltraScale+™ RFSoC Product Selecon Guide for further

details.

Chapter 1: Introduction

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Figure 3: Zynq® UltraScale+™ RFSoC XCZU48DR Device

Chapter 1: Introduction

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Chapter 2

Features

The main features of the T2 card are as follows:

•Card over-stress protecon: The T2 card has a card protecon circuit that iniates a fatal

shutdown if either temperature or power consumpon thresholds are crossed.

Before this threshold is reached, however, the SC signals to the Zynq UltraScale+ RFSoC to

reduce the 5G workload power immediately. This indicaon is accomplished using the

RF_CPU_RST and RF_RST_REQ handshake signals.

The precise threshold levels have been determined through tesng and factory sengs to

ensure card safety. They cannot be changed.

•Out-of-band telemetry: Telemetry data for the card is provided to the server board

management controller (BMC) over the PCIe SM bus from the T2 SC. The PLDM over MCTP

protocol is used for this communicaon between server BMC and T2 SC, and implements a

thermal closed loop control mechanism for card cooling.

All required telemetry data, including board temperatures and power consumpon, is

available.

•In-band telemetry: Telemetry data for the card is also available in-band over PCIe. The

following telemetry data is available:

• Zynq UltraScale+ RFSoC

• Board inlet temperature

• Board outlet temperature

• DDR4 vicinity temperature

• PCIe 12V current

• In-band SC rmware update

Note: The PCIe 3.3V current is characterized (2.6A) but not measured.

•In-band FPGA ash update: Updang the user ash image in-band over PCIe is supported

using the flash_app ulity provided in the host soware installaon. Details are found

within the T2 Telco Accelerator Card Installaon Guide (UG1527).

Some design components must be designed into the Zynq UltraScale+ RFSoC PL and PS to

support this funcon.

Chapter 2: Features

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•Developer support: Developer support features for the Zynq UltraScale+ RFSoC on the T2

card are provided through the maintenance port. See Chapter 4: Maintenance Port for details.

•LED: A green power-on LED is present on the I/O bracket to indicate the card is powered and

in operaon.

Chapter 2: Features

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Chapter 3

Pin Mapping

This chapter presents the pin mapping for the ZU48DR Zynq® UltraScale+™ RFSoC on the T2

card.

PCIe Interface

The PCIe® interface on the T2 card has 16 lanes and can operate in Gen 3 x16 mode or Gen 4

x8x8 bifurcated mode.

Using the PCIe Interface

• The PCIe interface is supported with a dedicated IP block that must be instanated in the

design.

• PCIe lane reversal is in use.

• The server slot used with the T2 card must be a x16 capable and congured correctly for card

detecon and use. The Gen 4 x8x8 mode of operaon requires x8 bifurcaon to be enabled,

whereas Gen 3 x16 requires x16 mode.

PCIe Interface Pins

The following table summarizes the ZU48DR PCIe interface pin map.

Table 1: PCIe Interface Pin Map

Pin Number Signal Name Description I/O

W34 PCIE_RF_LOWER_REFCLK_N PCIe Lower Diff Clock (N) I

W33 PCIE_RF_LOWER_REFCLK_P PCIe Lower Diff Clock (P) I

P32 PCIE_RF_UPPER_REFCLK_N PCIe Upper Diff Clock (N) I

P31 PCIE_RF_UPPER_REFCLK_P PCIe Upper Diff Clock (P) I

AJ13 PCIE_RF_PERST_LS PCIe Reset I

AA39 PCIE_RX0_N PCIe RX Data 0 (N) I

AA38 PCIE_RX0_P PCIe RX Data 0 (P) I

W39 PCIE_RX1_N PCIe RX Data 1 (N) I

W38 PCIE_RX1_P PCIe RX Data 1 (P) I

Chapter 3: Pin Mapping

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Table 1: PCIe Interface Pin Map (cont'd)

Pin Number Signal Name Description I/O

U39 PCIE_RX2_N PCIe RX Data 2 (N) I

U38 PCIE_RX2_P PCIe RX Data 2 (P) I

R39 PCIE_RX3_N PCIe RX Data 3 (N) I

R38 PCIE_RX3_P PCIe RX Data 3 (P) I

N39 PCIE_RX4_N PCIe RX Data 4 (N) I

N38 PCIE_RX4_P PCIe RX Data 4 (P) I

M37 PCIE_RX5_N PCIe RX Data 5 (N) I

M36 PCIE_RX5_P PCIe RX Data 5 (P) I

L39 PCIE_RX6_N PCIe RX Data 6 (N) I

L38 PCIE_RX6_P PCIe RX Data 6 (P) I

K37 PCIE_RX7_N PCIe RX Data 7 (N) I

K36 PCIE_RX7_P PCIe RX Data 7 (P) I

J39 PCIE_RX8_N PCIe RX Data 8 (N) I

J38 PCIE_RX8_P PCIe RX Data 8 (P) I

H37 PCIE_RX9_N PCIe RX Data 9 (N) I

H36 PCIE_RX9_P PCIe RX Data 9 (P) I

G39 PCIE_RX10_N PCIe RX Data 10 (N) I

G38 PCIE_RX10_P PCIe RX Data 10 (P) I

F37 PCIE_RX11_N PCIe RX Data 11 (N) I

F36 PCIE_RX11_P PCIe RX Data 11 (P) I

E39 PCIE_RX12_N PCIe RX Data 12 (N) I

E38 PCIE_RX12_P PCIe RX Data 12 (P) I

D37 PCIE_RX13_N PCIe RX Data 13 (N) I

D36 PCIE_RX13_P PCIe RX Data 13 (P) I

C39 PCIE_RX14_N PCIe RX Data 14 (N) I

C38 PCIE_RX14_P PCIe RX Data 14 (P) I

B37 PCIE_RX15_N PCIe RX Data 15 (N) I

B36 PCIE_RX15_P PCIe RX Data 15 (P) I

Y36 PCIE_TX0_N PCIe TX Data 0 (N) O

Y35 PCIE_TX0_P PCIe TX Data 0 (P) O

V36 PCIE_TX1_N PCIe TX Data 1 (N) O

V35 PCIE_TX1_P PCIe TX Data 1 (P) O

T36 PCIE_TX2_N PCIe TX Data 2 (N) O

T35 PCIE_TX2_P PCIe TX Data 2 (P) O

R34 PCIE_TX3_N PCIe TX Data 3 (N) O

R33 PCIE_TX3_P PCIe TX Data 3 (P) O

P36 PCIE_TX4_N PCIe TX Data 4 (N) O

P35 PCIE_TX4_P PCIe TX Data 4 (P) O

N34 PCIE_TX5_N PCIe TX Data 5 (N) O

Chapter 3: Pin Mapping

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