EES3 Hardware Interface Description
Figures
8
EES3_HD_v01.100b Page 7 of 118 2009-08-12
Confidential / Released
Figures
Figure 1: EES3 system overview .................................................................................. 21
Figure 2: EES3 block diagram....................................................................................... 22
Figure 3: Power supply limits during transmit burst....................................................... 25
Figure 4: Position of reference points BATT+and GND ................................................ 26
Figure 5: Powerup with operating voltage at BATT+ applied before activating IGT...... 28
Figure 6: Powerup with IGT held low before switching on operating voltage at BATT+ 29
Figure 7: Timing of IGT if used as ON/OFF switch ....................................................... 30
Figure 8: Signal states during turn-off procedure.......................................................... 35
Figure 9: Battery pack circuit diagram........................................................................... 42
Figure 10: Power saving and paging............................................................................... 47
Figure 11: Timing of CTSx signal (if CFUN= 7)............................................................... 48
Figure 12: Timing of RTSx signal (if CFUN = 9).............................................................. 48
Figure 13: RTC supply from capacitor............................................................................. 50
Figure 14: RTC supply from rechargeable battery .......................................................... 50
Figure 15: RTC supply from non-chargeable battery ...................................................... 50
Figure 16: Serial interface ASC0..................................................................................... 52
Figure 17: Serial interface ASC1..................................................................................... 54
Figure 18: USB circuit ..................................................................................................... 55
Figure 19: I2C interface connected to VCC of application ............................................... 56
Figure 20: I2C interface connected to VEXT line of EES3............................................... 56
Figure 21: SPI interface................................................................................................... 57
Figure 22: Characteristics of SPI modes......................................................................... 58
Figure 23: Audio block diagram....................................................................................... 59
Figure 24: Single ended microphone input...................................................................... 61
Figure 25: Differential microphone input ......................................................................... 62
Figure 26: Line input configuration with OpAmp ............................................................. 63
Figure 27: Differential loudspeaker configuration............................................................ 64
Figure 28: Master PCM interface Application.................................................................. 66
Figure 29: Short Frame PCM timing................................................................................ 66
Figure 30: Long Frame PCM timing ................................................................................ 67
Figure 31: Slave PCM interface application .................................................................... 68
Figure 32: Slave PCM Timing, Short Frame selected..................................................... 68
Figure 33: Slave PCM Timing, Long Frame selected...................................................... 68
Figure 34: SYNC signal during transmit burst................................................................. 69
Figure 35: LED Circuit (Example).................................................................................... 70
Figure 36: Incoming voice/fax/data call........................................................................... 71
Figure 37: URC transmission .......................................................................................... 71
Figure 38: Antenna pads................................................................................................. 72
Figure 39: 4 layer PCB stack for EES3 interface board .................................................. 73
Figure 40: RF line on interface board. All dimensions are given in mm .......................... 75
Figure 41: Numbering plan for connecting pads (bottom view)....................................... 80
Figure 42: Audio programming model............................................................................. 93
Figure 43: EES3– top view............................................................................................ 100
Figure 44: Dimensions of EES3 (all dimensions in mm) ............................................... 101
Figure 45: Land pattern (bottom view) .......................................................................... 102
Figure 46: Recommended stencil design (bottom view) ............................................... 103
Figure 47: Reflow Profile............................................................................................... 104
Figure 48: Carrier tape .................................................................................................. 107
Figure 49: Reel direction ............................................................................................... 107
Figure 50: Barcode label on tape reel ........................................................................... 108
