The LK/ACT LED’s are repeated on the front as 1 (port 1)…6 (port 6), whereas on the side as LA1…LA6. There is
another set of LEDs on the front for 10 and 100 to indicate the data rate and a set to indicate duplex for ports 1
and 2 only. 10/100 indicates the speed for copper ports, whereas F/H indicates Full and Half duplex for fiber ports
only. There is a power (PWR) LED to indicate that the unit is turned ON. The fiber ports on the DFG48044X Edge
switches are multi-mode or single-mode with an C, T or small form factor connector (MTRJ multi mode or LC
single-mode). The external DC power plug connector and/or “jack” and the internal DC input terminal is provided
on the rear of the unit.
2.3 Frame Buffering and Latency
The DFG48044X eries Edge witches are store-and-forward switches. Each frame (or packet) is loaded into the
witch’s memory and inspected before forwarding can occur. This technique ensures that all forwarded frames are
of a valid length and have the correct CRC, i.e. they are good packets. This eliminates propagation of bad packets,
enabling all of the available bandwidth to be used for valid information.
While other switching technologies such as "cut-through" or "express" impose minimal frame latency, they will also
permit bad frames to propagate to the Ethernet network. The "cut-through" technique permits collision fragment
frames, which are a result of late collisions, to be forwarded--which add to the network traffic. There is no way to
filter frames with a bad CRC (the entire frame must be present in order for CRC to be calculated). ince collisions
and bad packets are more likely when traffic is heavy, store-and-forward switch technology enables more
bandwidth to be available for good packets when the traffic load is greatest.
To minimize the possibility of dropping frames on congested ports, each DFG48044X eries Edge witch
dynamically allocates buffer space from 128KB memory pool, ensuring that heavily used ports receive very large
buffer space for packet storage. (Many other switches have their packet buffer storage space divided evenly across
all ports, resulting in a small, fixed number of packets to be stored per port. When the port buffer fills up, dropped
packets result.) This dynamic buffer allocation provides the capability for the maximum resources of the
DFG48044X eries unit to be applied to all traffic loads, even when the traffic activity is unbalanced across the
ports. ince the traffic on an operating network is constantly varying in packet density per port and in aggregate
density, the DFG48044X eries Edge witches are constantly adapting internally to provide maximum network
performance with the least dropped packets.
When the witch detects that its free buffer queue space is low, the witch sends industry standard (full-
duplex only) PAU E packets out to the devices sending packets to cause “flow control”. This tells the sending
devices to temporarily stop sending traffic, which allows a traffic catch-up to occur without dropping packets. Then,
normal packet buffering and processing resumes. This flow-control sequence occurs in a small fraction of a second
and is transparent to an observer.
Another feature implemented is a collision-based flow-control mechanism at half-duplex only. When the
witch detects that its free buffer queue space is low, it prevents more frames from entering by forcing a collision
signal on all receiving half-duplex ports in order to stop incoming traffic. The latency (the time the frame spends
in the witch before it is sent along or forwarded to its destination) of the DFG48044X eries Edge witches varies
with the port-speed types. The length of the frame is a variable as it is with all store-and-forward switches. For 10
Mb-to-10 Mb, 10 Mb-to-100Mb or 100Mb-to-10 Mb forwarding, the latency is 15 microseconds plus the packet time
of 10 Mb. For 100Mb-to-100Mb forwarding, the latency is 5 microseconds plus the packet time of 100Mb.
