Figures
Figure 1: Block diagram of the DA1468x minimal design ..................................................................... 7
Figure 2: Minimal design for DA14681-01 WLCSP53 package............................................................ 8
Figure 3: Minimal design for DA14681-01 AQFN60 package............................................................... 9
Figure 4: Minimal design for DA14683-00 WLCSP53 package.......................................................... 10
Figure 5: Minimal design for DA14683-00 AQFN60 package............................................................. 11
Figure 6: The power section of the DA1468x...................................................................................... 12
Figure 7: 4.7µF- 6.3V capacitance change for 0402 (purple) and 0603 (blue)................................... 14
Figure 8: DA1468x power management unit block diagram ............................................................... 15
Figure 9: V14, V18, V18P rails discharging by HW Reset.................................................................. 16
Figure 10: Discharging rails FSM timing ............................................................................................. 16
Figure 11: SIMO BUCK DC/DC Block Diagram.................................................................................. 17
Figure 12: PAD I/O configuration ........................................................................................................ 19
Figure 13: 16 MHz or 32 MHz crystal oscillator, recommended operating conditions........................ 21
Figure 14: Connection of the crystal (left) and external 16 MHz clock (right) for AQFN package ...... 21
Figure 15: 32.768 KHz crystal oscillator, recommended operating conditions ................................... 23
Figure 16: Clock output, P10_MODE_REG - PUPD and PID selection ............................................. 25
Figure 17: Clock output, GPIO_CLK_SEL - FUNC_CLK_SEL, clock selection.................................. 25
Figure 18: Recommended topology for USB functionality .................................................................. 27
Figure 19: Relation between damping and step-response of a series LC resonator.......................... 28
Figure 20: used USB circuit for testing................................................................................................ 28
Figure 21: Step response with 60 cm (left) and 150 cm (right) cable (non USB-cable). A damping
network of 0.39 Ω and 10 μF capacitor on VBUS is used................................................................... 29
Figure 22: Step response with 300 cm cable (non USB-cable) and the same damping network as
above (0.39 Ω and 10 μF capacitor on VBUS).................................................................................... 29
Figure 23: Step response of VBUS with 0.39 Ωand 10 μF for a 1.5 m USB cable............................ 30
Figure 24: Wakeup from Hibernation by VBUS voltage using GPIO trigger....................................... 31
Figure 25: GPIO set as Input (no pull)................................................................................................. 31
Figure 26: RF matching circuit must be placed as close as possible to the antenna ........................ 32
Figure 27: WLCSP53 PCB stackup..................................................................................................... 33
Figure 28: WLCSP53 PCB layout, top side......................................................................................... 34
Figure 29: WLCSP53 PCB layout, layer 2........................................................................................... 35
Figure 30: WLCSP53 PCB layout, layer 3, reference GND ................................................................ 35
Figure 31: Ground connectivity Top (left) and layer 2 (right)............................................................... 36
Figure 32: AQFN60 PCB stackup ....................................................................................................... 37
Figure 33: AQFN60 PCB layout, top layer .......................................................................................... 38
Figure 34: AQFN60 PCB layout, layer2, reference ground................................................................. 39
Figure 35: PCB footprint data.............................................................................................................. 40
Figure 36: Recommend of stencil opening of thermal......................................................................... 42
Figure 37: Reflow profile for solder paste SAC305............................................................................. 43
Tables
Table 1: DA14680/14682 and DA14681/14683 chip options................................................................ 5
Table 2 CHIP_REVISION_REG (0x50003204)..................................................................................... 6
Table 3 CHIP_TEST1_REG (Minor revision)........................................................................................ 6
Table 4 Chip revision numbering........................................................................................................... 6
Table 5: Suggested decoupling capacitors for the power section....................................................... 13
Table 6: SIMO DC/DC inductor examples and characteristics ........................................................... 13
Table 7: DA1468x supply rail capabilities overview ............................................................................ 15
Table 8: 16 MHz crystal examples and characteristics....................................................................... 22
Table 9: 32 MHz crystal examples and characteristics....................................................................... 22
Table 10: 32.768 KHz crystal examples and characteristics............................................................... 23
Table 11: Default UART pins............................................................................................................... 25
Table 12: JTAG pins............................................................................................................................ 25
