ESPROS Epc10 Series Bedienungsanleitung

Reference Manual epc10x

Reference Manual

epc100

epc101

Functional Block diagram epc70x LST

Voltage Regulator

Parameter

Memory

2- ire COM

Interface

2- ire COM

Interface

VDD33

20.10.2010

Page 1

...

File:

This document is confidential and protected by la and international trades. It must not be sho n to any third party nor be copied in any form ithout our ritten permission.

LED

VLED

VDD18

Signal

Processor

SPI

Controller

GND

VDD

LED

SCK

Characteristics subject to change without notice

Page 1/26 Reference Manua epc100 - V2.2

Reference Manual epc10x

Table of Contents

1. Introduction.................................................................................................................................................... 3

2. Light Curtain Principle..................................................................................................................................

2.1 System Overvie ........................................................................................................................................................................................... 4

2.2 Light Curtain Receiver Edge..........................................................................................................................................................................6

2.3 Light Curtain Emitter Edge.............................................................................................................................................................................6

3. 2-Wire Bus...................................................................................................................................................... 7

3.1 General Description....................................................................................................................................................................................... 7

3.2 Bus Wire Considerations............................................................................................................................................................................... 8

3.3 Bus Signal Waveform.................................................................................................................................................................................... 9

. Parameter Memory...................................................................................................................................... 10

4.1 Receiver Parameters (epc100)....................................................................................................................................................................11

4.2 Sample Receiver Parameter Setting........................................................................................................................................................... 13

4.3 Transmitter Parameters (epc101)................................................................................................................................................................14

4.4 Sample Transmitter Parameter Setting....................................................................................................................................................... 16

5. Timing........................................................................................................................................................... 17

5.1 Overvie ...................................................................................................................................................................................................... 17

5.2 Timing Details.............................................................................................................................................................................................. 17

5.3 Special Cases.............................................................................................................................................................................................. 18

6. SPI Interface................................................................................................................................................. 19

6.1 Timing Specifications...................................................................................................................................................................................19

6.2 General Description..................................................................................................................................................................................... 19

6.3 Command List..............................................................................................................................................................................................20

6.4 Detailed Command Descriptions................................................................................................................................................................. 21

7. Address Programming................................................................................................................................ 2

7.1 General Description..................................................................................................................................................................................... 24

7.2 Programming Procedure..............................................................................................................................................................................25

8. Considerations for Safety Applications..................................................................................................... 26

8.1 Data Integrity on the 2-Wire Po er-Bus...................................................................................................................................................... 26

8.2 Residual Error Rate..................................................................................................................................................................................... 26

8.3 Error Cases..................................................................................................................................................................................................26

8.4 Error Codes..................................................................................................................................................................................................26

Characteristics subject to change without notice

Page 2/26 Reference Manua epc100 - V2.2

Reference Manual epc10x

1. Introduction

The epc10x chip set is a general purpose CMOS integrated circuit for light-curtain applications. epc100 is used on the

receiver side (Rx) hereas epc 101 is on the emitter side (Tx). Up to 1023 devices may be connected to t o respectively

four ires in parallel. Each device can be individually addressed by an epc100 chip hich acts as the interface bet een a

microcontroller and the 2- ire bus. It manages the bus traffic bet een the microcontroller and the individual Rx and Tx

elements. Programmable fuses i.e. for the address, sensitivity, LED light pulse idth, etc. allo the device to be paramet -

rized in the final system (OTP memory).

The microcontroller activates the Tx elements and reads the status of the Rx in a sequential manner. The status of the Rx

elements can be 'no light pulse received', 'lo level light pulse received' and 'high level light pulse received'.

Each chip can be put into 'standby mode' or 'operating mode' to reduce po er consumption. During 'standby mode', po er

consumption is reduced and the photo diode is shorted. In the 'operation mode', the device is active and ready to receive a

light pulse generated by an LED in the emitter side of the light curtain.

During a normal scan, the microcontroller addresses one device after the other and fetches the result ith a delay of three

scan periods. Thus, the microcontroller has to manage the emitter light pulses on the emitter edge of the light curtain as

ell. This function is supported by the epc101 device hich is the counterpart of epc100 (refer to a separate data sheet and

reference manual).

This Manual describes the various operation and programming modes in order to use Rx and interface chip epc100 and the

Tx chip epc101.

Characteristics subject to change without notice

Page 3/26 Reference Manua epc100 - V2.2

Reference Manual epc10x

2. Light Curtain Principle

2.1 System Overview

A light curtain consist of an emitter edge (Tx) and a receiver edge (Rx). The Tx edge contains a number of light emitters,

typically infrared LEDs hich emit their light to ards the Rx edge. The Rx edge contains typically the same number of photo

receivers like the number of emitters in the Tx edge. Typical numbers of receivers or emitters are 10, 24, 40 or every figure

bet een 1 and up to 1023 are possible, depending on the application. The follo ing dra ing sho s a typical light curtain

setup.

Characteristics subject to change without notice

Page 4/26 Reference Manua epc100 - V2.2

Figure 1: Light curtain principle

Micro

Controller

Out

2-Wire Bus

epc101 ith LED

epc100 ith PD

light cone

generated by the

LED active light beam

light beam

number

Tx edge

➊

➋

➌

➍

➎

➏

➐

➑

➒

➓

Bus

Interface

(epc100)

Bus

Interface

(epc100)

Rx edge

Bus Termination

50Ω, 100nF

SPI-Interface

Reference Manual epc10x

The left side of Figure 1 sho s the Tx edge containing 10 emitter elements. Each emitter element consist of an epc101 chip

ith an LED and a fe other components. Each of the Tx elements is connected to a 2- ire bus1, hich is fed to the Rx

edge on the right side of Figure 1. The Rx edge contains 10 receiver elements, consisting of an epc100 chip ith a photo

diode and a fe passive components. A microcontroller hich is typically but not necessarily located in the receiver edge

controls the 2- ire bus through an epc100 chip. This chip acts as a bus controller. Because every Tx and Rx element has a

unique address, the microcontroller has individual access to all bus components.

Each of the Tx elements sends light, typically infrared light, in a cone to ards the Rx edge. The emitted light of one LED

illuminates usually more than one receiver element because of a rather ide cone angle2 and a small distance bet een the

individual elements in the edge3. If all emitters ould be active at the same time, small objects bet een the Tx and Rx edge

ould not be detected because of light bypassing. Thus, a sequential operation mode has to be established. This sequential

operation is typically like this:

1. The first Rx (Rx1) element is turned on (active mode).

2. Then, the first Tx (Tx1) element is activated so it sends a short light pulse to ards the Rx edge, forming the active light

beam ➊.

3. If there is no obstacle bet een Tx1 and Rx1, Rx1 receives this light pulse and stores it into a local memory.

4. The microcontroller reads out the content of the memory in Rx1 and stores the value (light beam interrupted or not inter-

rupted) into its data memory.

5. Finally, Rx1 is turned off (standby mode).

This sequence, hich is also called 'scan', is repeated until all beams are checked and their status is stored in the beam

status memory of the microcontroller. The last step is to analyze the beam status memory by the microcontroller. If all

beams have the status 'not interrupted', the output of the light curtain can be set to this state. If one ore more beams are

interrupted, the output of the light curtain is set to the status 'interrupted'.

The above mentioned sequence is repeated until po er is s itched off. Because of the fact, that an object can enter into the

light grid right after a beam has been checked ith the above mentioned procedure, up to t o full scan sequences are

necessary to reliably detect an object. Thus, the overall maximum response time of the light curtain ill be

tR=2∗n∗tbeamteval 

(1)

here

tR= response time of the light curtain

n = number of elements or light beams

tbeam = time to evaluate one beam

teval = time to evaluate the beam status memory and generate the output signal

For further reference in optical design considerations please refer to the application note AN01.

1 If the LED pulse current is rather high, i.e. 1 A, t o separate bus ires for the LED supply current are needed. Please refer to the data

sheet of epc101 for detailed information.

2 Typical cone angles are bet een 5° and 40°, depending on the application.

3 The spacing bet een the individual elements of a light curtain is also called 'grid spacing' and is typically in a range of a fe millimeters up

to hundreds of millimeters.

Characteristics subject to change without notice

Page 5/26 Reference Manua epc100 - V2.2

Reference Manual epc10x

2.2 Light Curtain Receiver Edge

Figure 2 sho s the epc100 in the light curtain application on the receiver side. It can be used in t o main functions:

1. Sensor device R1 .. Rn: It senses the current pulse from the photo diode and transmits the information to the interface

device over the 2- ire bus.

2. Interface device IF: It interfaces the serial bus from the microprocessor ith the 2- ire bus.

From the point of vie of the microcontroller, the hole system looks like a single device ith several addressable photo

diodes: the microcontroller activates one photo diode and fetches the results after a predefined time. During a normal scan,

the microcontroller addresses one device after the other and fetches the result ith a delay of three scan periods.

2.3 Light Curtain Emitter Edge

On the emitter side, the epc101 controls the LEDs as the epc100 does for the photo diodes.

TP is a test point used for programming the epc101 chip ith the parameters needed in the application. This test point has to

be physically accessed during final assembly of the emitter edge.

In the circuit in Figure 3, the LED current is defined by a common current source in the ILED line. The resistor RLED limits the

current through the LED and is not needed in non-safety applications. If such a resistor is inserted, a failure mode can be

detected, if more than one LED is active due to a short circuit or a failure in the epc100. It is also possible to have a common

voltage supply and to generate the LED current by a resistor.

Characteristics subject to change without notice

Page 6/26 Reference Manua epc100 - V2.2

Figure 2: epc100 in the light curtain application as receivers and the interface chip to the microcontroller

VDDVDDVDD

VDD33 IF

epc100

GND

SCK

µC

GND

VDD µC

VDDR

VDD33 R1

epc100

GND

26.05.2011

Page 1

File:

This document is confidential and protected by la and international trades. It must not be sho n to any third party nor be copied in any form ithout our ritten permission.

VDD18

VDD33 R2

epc100

GND

VDD18

VDD33 Rn

VDD

epc100

GND

VDD18

Rx Element 1 Rx Element 2 Rx Element n

Bus Termination

RTE

100nF

RTE

ITE

Figure 3: epc101 in the Tx edge application

AN epc101 light curtain Transmitter LST

VDD33

VDDR

epc100

GND

SCK

µC

GND

VDD µC

VDDR

VDD

epc101

GND

LED

VDD33

RLED

+ ILED

- ILED

26.05.2011

Page 1

File:

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Tx Element 1

RLED

Tx Element 2

VDD

VDD33

epc101

GND

LED

RLED

Tx Element n

VDD

VDD33

epc101

GND

LED

Bus Termination

RTE

100nF

TP TP

RTE

ITE

Reference Manual epc10x

3. 2-Wire Bus

3.1 General Descripti n

The 2- ire bus and the po er supply utilize the same t o ires. The data is transmitted by modulating the current on the

po er-line. The modulated current, together ith the resistor in the po er supply, produce a voltage signal on the line. All

devices receive this signal. The system is designed to operate ith a line impedance of 50Ω (±5%). An inductor in parallel of

the resistor or a DC regulator ith a lo pass feedback shape the pulses and keep the the DC voltage drop over the resistor

lo . The required corner frequency of this L/R-filter is listed in the table belo .

The communication interface has been designed to be used for line lengths of up to 100m and ith up to 1023 sensor

devices. For line lengths of up to 3m it is possible to operate the line ithout termination4. Above this length the line has to

be terminated by a resistor of 50Ω (±5%) hich is equal to the line impedance and a capacitor of 100nF in series.

The data rate on the 2- ire bus is set by the parameter DRATE. It also defines TSCANmin (refer to Chapter Timing on page 17)

and the required inductor according to Table 1. The maximum data rate allo ed on the 2- ire bis is depending on the bus

length. The longer the bus ire, the lo er the data rate. Table 1 sho s the possible bus ire length according to the data

rate.

DRATE k Data Rate on

the 2-Wire Bus

Minimal Data Rate

Required on SPI

Interface

Corner

Frequency

L/R

Inductor

ITE

Bus Wire

Length5

00 8 250 kbit/s 300 kbit/s 0.5 MHz 16µH 12 … 100m

01 4 500 kbit/s 600 kbit/s 1 MHz 8µH 6 … 12m

10 2 1 Mbit/s 1.2 Mbit/s 2 MHz 4µH 3 … 6m

11 1 2 Mbit/s 2.4 Mbit/s 4 MHz 2µH ≤ 3m

Table 1: Data rate of the 2- ire communication

The default value of DRATE is 00. The parameter DRATE has to be identical for all devices on one physical 2- ire bus.

The SPI bus should be faster than the 2- ire bus, other ise the communication does not ork. Since the command length

dependent on the command type, the delay time to the next command has to be adjusted to the previous command. The

time delay can be calculated ith the given data length in Table 11 on page 20.

The parameter CDET defines the optimal signal amplitude for the receiver. The maximum rate at pin VDD (5.5V) should not

be exceeded and signals hich are smaller than 70% of the recommended values are not detected.

Since the command length is dependent on the command type, the delay time to the next command has to be adjusted to

the previous command. The time delay can be calculated ith the given data length in Table 11 on page 20. The data

handling chain of the 2- ire communication channel is sho n in Figure 4.

Figure 5 sho s the different messages ith the parity bits. From the interface to the sensor/transmitter device the “normal command” is used

except for the register rite command. In the other direction only the register readout has a different format. Notice the different start bits

4 Dependent on the electro-mechanical design and the bus location of the edge, the termination net ork can be necessary. It is in the

responsibility of the system designer that the data integrity on the bus is guaranteed. Data integrity can be tested by readout bus

transmission errors. It is strongly recommended to do that during type qualification during EMI qualification tests.

5 The effective length is dependent on the electro-mechanical design of the edge. The values in the table are indicative only.

Characteristics subject to change without notice

Page 7/26 Reference Manua epc100 - V2.2

Command Data

Original

Message

Parity Bits

added

Manchester

Encoder

Current

Sink

Line

Filter

A/D

Converter

Manchester

Decoder +

Error Detection

Error Correction

Received

Message

Command Data

ReceiverTransmitter

Figure 4: Data handling

Reference Manual epc10x

hich identify the direction of the transmission: 00 for the direction interface to sensor devices and 01 in the other direction. Bet een the

telegrams, an idle time of 2 clock periods are need to detect the start of the transmission.

Figure 5: Message Structure

3.2 Bus Wire C nsiderati ns

The electromechanical design of a system using multiple epc10x devices on a t isted pair cable ith an impedance of

typically 100 Ohms has an impact on the overall impedance of the system. Figure 6 sho s the change of the cable

impedance ith smaller element pitch.

On the source side the termination is done by the resistor RTE (see Figure 2), on the other side it is highly recommended to

terminate the bus line ith an AC terminator net ork (sho n in Figure 7) hich matches the overall impedance of the

system according to Figure 6. In order to avoid high DC currents in the termination resistor, a capacitor of 100nF should be

connected in series to the termination resistor. The interface device has to be placed near the L/R circuit (<1m).

Characteristics subject to change without notice

Page 8/26 Reference Manua epc100 - V2.2

Figure 7: Bus termination net ork

RTE

100nF

Figure 6: Line impedance as a function of the

element pitch on a 100 Ohm t isted pair cable

1.0

1.8

3.2

5.6

10.0

17.8

31.6

56.2

100.0

100

120

Pitch [cm]

Impedance [Ohm]

A0A1A2A3A4A5A6A7A8A9C0C1C2P0P1P2P3P4P5P6P7P8P9

Device Address Command Parity Bits

A0A1A2A8A9

C0C1C2P0P1P8P9R0R1R2R3R4D0D1D14 D15 P0P1P8P9

Device Address

Command Parity Bits Parity BitsDataRegister

P0P1P8P9

Parity Bits

D0D1D9D10

Data

A0A1A2A8A9

Device Address

R0R1R2R3R4D0D1D14 D15 P0P1P8P9

Parity BitsDataRegister

Normal Command

Write Command

Results

C0C1C2

A0A1A2A8A9

Device Address

R0R1R2R3R4

P0P1P8P9

Parity BitsCommand

Read Command

Reference Manual epc10x

Another aspect is the distribution velocity of the electrical signals on the 2- ire bus. Since the bus ire itself as ell as the

individual elements on the bus present a significant capacitance, the distribution velocity decreases ith the number of

elements and the pitch bet een the elements.

It is important that the overall delay is less than 50% of the clock period of the transmission. E.g. if the system is operated

ith 2 MBit/s data rate, the max. accepted delay must not be more than 125ns. Figure 8 sho s, that a system operated at

the full speed of 2 Mbit/s, a cable length of up to 5m are possible ith an element pitch do n to 1cm.

Example:

If e have a system that contains 100 elements in a pitch of 10cm, the total bus length is 10m. According to Figure 8, the

delay time of a proper terminated bus is a little bit more than 100ns. Thus, such a system can be operated ith the full

speed of 2MBit/s. Ho ever, e recommend to limit the bus length to the values stated in Table 1.

3.3 Bus Signal Wavef rm

Figure 9 pictures the Manchester encoding and the signal on the bus. The signal on the bus can be monitored ith an oscil-

loscope and should look like in the dra ing.

CDET is the threshold set in the 2- ire communication receiver of the chip to detect the communication signal on the bus.

This parameter, described in Table 6 and Table 10, can be adjusted to match the specific system requirements. Thus, the

voltage s ing VS of the communication signal on the bus shall match this setting. A good principle is that the voltage s ing

VS measured on the bus should be min. 25% and max. 150% above the CDET value.

Example:

If CDET is set to 200mV, the voltage s ing VS should be in a range of 250 to 500 mV. Ideal for this setting is a s ing

voltage VS of 400mV.

Attention:

Make sure that the voltage s ing VS is in the given tolerance range at every physical location of the bus. Due to reflections

in the cable, losses of the ires (capacitive, inductive, and resistive), and the high band idth of the communication signals,

significant differences can occur.

Characteristics subject to change without notice

Page 9/26 Reference Manua epc100 - V2.2

Message

Manchester

Signal on Bus

TDataRate

CDET

Figure 9: Manchester encoded signal on the bus

Figure 8: Delay vs Pitch. Parameter: Line length [m]

1 1.78 3.16 5.62 10 17.7831.6256.23 100

100

316

1000

100

Pitch [cm]

Delay [ns]

Reference Manual epc10x

. Parameter Memory

The devices epc100 and epc101 contain a memory to store the application parameters. The follo ing classes of data are

stored on each device:

Unique chip ID and chip adjustments (factory set)

Physical device address in the application, representing the beam number

Application parameters

This data can be permanently stored in a read-only memory6 and is mirrored in a volatile memory7. At po er up, the data

(except the chip ID) is copied from the ROM to the RAM. During operation, the data from the RAM is used. Both memories

are organized in 16 registers at 16 bits each. The data can be accessed on a 16-bit register base. The follo ing table sho s

the memory organization:

Non-Volatile Memory Address

Range

(Register no.)

Volatile Memory Address

Range

(Register no.)

Description

0 - 3 16 – 19 Application parameters

4 - 6 20 – 22 Trim values, factory set

7 23 Device Address

8 – 15 - Chip ID, factory set

- 24 – 31 For factory test purpose. Read only.

Table 2: Memory map overvie

As sho n in the table above, registers 0 – 3 and 7 are used for configuring the chip in the application. Before the devices

can be used in a given light curtain system, the required application parameters and the physical address of the chip in the

system have to be stored into the devices memories. The follo ing table sho s a parameter memory overvie :

Parameters in hite fields only shall be programmed. Never change the memory content of gray marked cells. Because only

complete registers can be programmed, the bits hich are gray marked must be set to zero.

The RAM can only be ritten, if the corresponding ROM memory hasn’t been ritten before or if the volatile mode is active

(VMODE, refer to Table 3 on page 10 and Table 7 on page 14). The last bit of each 16-bit ROM register serves as rite

inhibit bit. To rite to the ROM, the microcontroller has to rite to the RAM first. From there, the microcontroller can first

double check the data integrity. When a memory section is verified, the content can be transferred from the RAM memory

using the command PROG to the ROM (refer to chapter 6.4.8 Command PROG).

The device is fully operational as ell ithout programming the ROM but data ill be lost at po er do n. Operating the

chips in this mode is helpful during the development of the product. Ho ever, in the final application, the parameters must

be stored into the ROM memory.

6 The non-volatile memory is a one-time-programmable memory (OTP). Once the memory is programmed, the programmed values cannot

be over ritten anymore! This memory type is hereinafter called ROM.

7 Hereinafter called RAM.

Characteristics subject to change without notice

Page 10/26 Reference Manua epc100 - V2.2

Figure 10: Detailed memory map

Bit #

ROM RAM 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0

0 16 VMODE MODE SOFF DRATE TSTMP TPULSE POL FUSEBIT

1 17 TPER FUSEBIT

2 18 TSET SENS IVCOFF SLO SENSH SENSN / VTHRLED FUSEBIT

3 19 CDET C2X FUSEBIT

4 20 FUSEBIT

Trimming

5 21 FUSEBIT

6 22 FUSEBIT

7 23 Address FUSEBIT Device Address

8 24 Lot no. LSB FUSEBIT

Chip ID

9 25 Lot no. MSB FUSEBIT

10 26 Chip ID FUSEBIT

11 27 Factory use only FUSEBIT

12 28 Revision no. FUSEBIT

13 29 no function FUSEBIT

14 30 no function FUSEBIT

15 31 no function FUSEBIT

Application

parameters

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