FLY SDP100 Bedienungsanleitung
MODEL SDP100 VERSION V_1.00
PREPARED BY H/W DATE 25/05/2007
SUBJECT TECHNICAL MANUAL PAGE 1/70
Baseband section
This document provides a description of the baseband section of the SDP100. Most design decisions are explained,
but no detailed calculations are included. Total chip solutions(MT6228, MT6305BN, MT6120) except for RF
Power Amplifier(RF3166) are from MediaTek, Taiwan.
I. MT6228 ( GSM/GPRS Baseband Processor )
1. System OverView
The Revolutionary MT6228 is a leading edge single-Chip solution for GSM/GPRS mobile phones targeting the emerging
applications in digital audio and video. Based on 32bit ARM7EJ-STM RISC processor, MT6228 not only features high
performance GPRS Class 12 MODEM, but also provides comprehensive and advanced solutions for handheld multi-
media. But, the SDP100 can only support GPRS Class 8.
The Figure 1 is shown Typical Application for MT6228.
Figure 1 : Typical Application for MT6228
1.1 Platform Feature
SDP100 TECHNICAL MANUAL Page 3.1
MODEL SDP100 VERSION V_1.00
PREPARED BY H/W DATE 25/05/2007
SUBJECT TECHNICAL MANUAL PAGE 2/70
zGeneral
-. Integrated voice-band, audio-band and base-band analog front ends.
-. TFBGA 13mm x 13mm, 314balls, 0.65mm pitch package.
zMCU Subsystem
-. ARM7EJ-S 32bit RISC processor
-. High Performance Multi-layer AMBA bus
-. Java hardware acceleration for fast Java-based games and applets.
-.Operating frequency : 25/52/104Mhz
-. Dedicated DMA Bus
-. 14 DMA channels
-. 1M bits on-chip SRAM
-. 1M bits MCU dedicated Tightly Coupled memory
-. 256K bits CODE cache
-. 64K bits DATA cache
-. On-chip boot ROM for factory flash programming
-. Watchdog timer for system crash recovery
-. 3sets of General purpose timer
-. Circuit Switch Data coprocessor
-. Division coprocessor
-. PPP Framer coprocessor
zExternal Memory Interface
-. Supports up to 4 external devices
-. Supports 8-bit or 16-bit memory components with maximum size of up to 64M bytes each.
-. Supports Mobile RAM and Cellular RAM
-. Supports Flash and SRAM/PSRAM with page mode or burst mode
-. Industry standard Parallel LCD interface
-. Supports Multi-media companion chips with 8/16bits data width.
-. Flexible I/O voltage of 1.8V ~ 2.8V for memory interface.
zUser Interface
-. 6-row x 7-column keypad controller with hardware scanner.
-. Supports multiple key presses for gaming.
-. SIM/USIM controller with hardware T=0/T=1 protocol control.
-. Real Time Clock(RTC) operating with a separate power supply.
-. General Purpose I/Os (GPIOs)
-. 2sets of Pulse Width Modulation(PWM) output.
-. Alerter Output with enhanced PWM or PDM.
-. 8 external interrupt lines.
zSecurity
-. Cipher : supports AES, DES/3DES
SDP100 TECHNICAL MANUAL Page 3.2
MODEL SDP100 VERSION V_1.00
PREPARED BY H/W DATE 25/05/2007
SUBJECT TECHNICAL MANUAL PAGE 3/70
-. Hash : Supports MD5, SHA-1
-. Supports security key and 2kit chip unique ID
zConnectivity
-. 3 UARTs with hardware flow control and speed up to 921600pbs.
-. IrDA modulator/Demodulator with hardware framer. Supports SIR/MIR/FIR operating Speeds.
-. Full speed USB 1.1 OTG capability. Support Device mode, limited host mode and dual-role OTG mode.
-. Multi Media Card, Secure Digital Memory Card, Memory Stick, Memory Stick Pro Host Controller with flexible
I/O Voltage power.
-. Supports SDIO interface for SDIO peripherals as well as WIFI connectivity.
-. DAI/PCM and I2S interface for Audio application.
zPower Management
-. Power Down Mode for analog and digital circuits.
-. Processor Sleep Mode
-. Pause Mode of 32Khz clocking in Standby state
-. 7 channel Auxiliary 10bit A/D converter for charger and battery monitoring and photo sensing.
zTest and Debug
-. Built-in digital and analog loop back modes for both Audio and baseband front-end.
-. DAI port complying with GSM Rec.11.10
-. JTAG port for debugging embedded MCU.
1.2 Model Feature
zRadio Interface and Baseband Front End
-. GMSK Modulator with analog I and Q channel outputs.
-. 10-bit D/A convert for Uplink baseband I and Q signals.
-. 14bit high resolution A/D converter for downlink baseband I and Q signals.
-. Calibration mechanism of offset and gain mismatch for baseband A/D converter and D/A converter.
-. 10bit D/A converter for Automatic Power Control(APC)
-. 13bit high resolution D/A converter for Automatic frequency Control(AFC)
-. Programmable Radio RX filter.
-. 2 channels Baseband Serial Interface(BSI) with 3-wire control.
-. Bi-Directional BSI interface. RF chip register read access with 3-wire or 4-wire interface
-. 10 pin Baseband Parallel Interface(BPI) with programmable driving strength.
-.Multi-band Support (GSM850, GSM900, DCS1800, PCS1900)
zVoice and Model Codec
-. Dial tone Generation.
-. Voice memo
-. Noise reduction
-. Echo suppression
-. Advanced sidetone Oscillation Reduction.
-. Digital side-tone generator with programmable gain.
SDP100 TECHNICAL MANUAL Page 3.3
MODEL SDP100 VERSION V_1.00
PREPARED BY H/W DATE 25/05/2007
SUBJECT TECHNICAL MANUAL PAGE 4/70
-.Two programmable acoustic compensation filters.
-. GSM/GPRS quad vocoders for adaptive multirate(AMR), enhanced full rate(EFR), full rate(FR) and half rate(HR).
-. GSM channel coding, equalization and A5/1 and A5/2 ciphering.
-.GPRS GEA1 and GEA2 ciphering.
-. Programmable GSM/GPRS model.
-. Packet Switched data with CS1/CS2/CS3/CS4 coding schemes.
-.GSM circuit switch data.
-. GPRS Class 12.
zVoice Interface and Voice Front End.
-. Two microphone inputs sharing one low noise amplifier with programmable gain and automatic gain control(AGC)
mechanisms.
-. Voice power amplifier with programmable gain.
-. 2’nd order Sigma-Delta A/D converter for voice uplink path.
-. D/A Converter for Voice downlink path.
-. Supports Half-duplex hands-free operation.
-. Compliant with GSM 03.50.
1.3 Multimedia Feature
zLCD/NAND Flash Interface
-. Dedicated Parallel Interface supports 3 external devices with 8/16 bits NAND flash interface, 8/9/16/18 bit Parallel
interface and serial interface for LCM.
-. Built-in NAND flash controller with 1 bit ECC for mass storage.
zLCD Controller
-. Supports simultaneous connection to up to 3 parallel LCD and 2 serial LCD modules.
-. Supports LCM format : RGB332, RGB444, RGB565, RGB666, RGB888.
-. Supports LCD Module with maximum resolution up to 800x600 at 24bpp.
-. Per pixel alpha channel.
-. True colour engine
-. Supports hardware display rotation.
-. Capable of combining display memories with up to 6 blending layers.
zImage Signal Processor
-. 8/10 bit Bayer format image input.
-. YUV422 format image input.
-. Capable of processing image of size up to 3M pixels.
-. Colour correction matrix.
-. Gamma correction.
-. Automatic exposure(AE) control.
-. Automatic focus control.
-. Automatic white balance(AWB) control.
-. Programmable AE/AEB windows.
SDP100 TECHNICAL MANUAL Page 3.4
MODEL SDP100 VERSION V_1.00
PREPARED BY H/W DATE 25/05/2007
SUBJECT TECHNICAL MANUAL PAGE 5/70
-. Edge enhancement support.
-. Shading compensation.
-. Defect Pixel compensation.
zGraphic Compression.
-. GIF decoder, PNG Decoder.
zJPEG Decoder
-. ISO/IEC 10918-1 JPEG Baseline and Progressive modes.
-. Supports all possible YUV formats, Including gray-scale format.
-. Supports all DC/AC Huffman table parsing.
-. Supports all quantization table parsing.
-. Supports a restart interval
-. Supports SOS, DHT, DQT and DRI marker parsing.
-. IEEE Std 1180-1990 IDCT standards compliance
-. Supports progressive image processing to minimize storage space requirement.
-. Supports reload-able DMA for VLD stream.
zJPEG Encoder
-. ISO/IEC 10918-1 JPEG baseline mode.
-.ISO/IEC 10918-2 compliance
-. Supports YUV422 and YUV420 and grayscale formats.
-. Supports JFIF.
-. Standard DC and AC Huffman tables.
-. Provides 4 levels of encode quality.
-. Supports continuous shooting.
zImage Data Processing.
-. Supports Digital Zoom.
-. Supports RGB888/565, YUV444 image processing.
-. High throughput hardware scaler. Capable of tailoring an image to an arbitrary size.
-. Horizontal scaling in averaging method.
-. Vertical scaling in bilinear method.
-. Simultaneous scaling for MPEG-4 encode and LCD display.
-. YUV and RGB color space conversion.
-. Pixel format transform.
-. Boundary padding.
-. Pixel processing : hue/saturation/intensity/color adjustment, Gamma correction and grayscale/invert/sepia-tone effects.
-. Programmable spatial filtering : linear filter, non-linear filter and multi-pass artistic effects.
-. Hardware accelerated image editing.
-. Photo frame capability.
-. RGB thumbnail data output.
zMPEG-4/H.263 CODEC
SDP100 TECHNICAL MANUAL Page 3.5
MODEL SDP100 VERSION V_1.00
PREPARED BY H/W DATE 25/05/2007
SUBJECT TECHNICAL MANUAL PAGE 6/70
-. Hardware Video CODEC.
-. ISO/IEC 14496-2 simple profile :
Decode @ level 0/1/2/3
Encode @ level 0.
-. ITU-T H.263 profile 0 @level 10.
-. Max decode speed is VGA @15fps.
-. Max encode speed is CIF@15fps.
-. Support VGA mode encoding.
-. Horizontal and vertical de-blocking filter in video playback.
-. Encoder resync marker and HEC.
-. Support visual tools for decoder : I-VOP, P-VOP, AC/DC Prediction, 4-MV, Unrestricted MV, Error Resilience, Short
Header.
-. Error Resilience for decoder : Slice Resynchronizaton, Data Partitioning, Reversible VLC.
-. Supported visual tools for encoder : I-VOP, P-VOP, Half-Pel, DC Prediction, Unrestricted MV, Reverible VLC, Short
Header.
-. Supports encoding motion vector of range up to -64/+63.5 pixels.
-. HE-AAC decode support.
-. AAC/AMR/WB-AMR audio decode support
-. AMR/WB-AMR audio encode support.
zTV-OUT
-. Supports NTSC/PAL formats(interlaced mode)
-. 10bit video DAC with 2x oversampling.
-. Supports one composite video output.
zAudio CODEC
-. Supports HE-AAC codec decode
-. Supports AAC codec decode
-. Wavetable synthesis with up to 64 tones
-. Advanced wavetable synthesizer capable of generating simulated stereo
-. Wavetable including GM full set of 128 instruments and 47 sets of percussions
-. PCM Playback and Record
-. Digital Audio Playback
zAudio Interface and Audio Front End
-. Supports I2S interface
-. High resolution D/A Converters for Stereo Audio playback
-. Stereo analog input for stereo audio source
-. Analog multiplexer for stereo audio
-. Stereo to mono conversion
SDP100 TECHNICAL MANUAL Page 3.6
MODEL SDP100 VERSION V_1.00
PREPARED BY H/W DATE 25/05/2007
SUBJECT TECHNICAL MANUAL PAGE 7/70
Figure 2 is shown the Block Diagram of MT6228 for detailly.
Figure 2 : Block Diagram of MT6228
2. Product Description
SDP100 TECHNICAL MANUAL Page 3.7
MODEL SDP100 VERSION V_1.00
PREPARED BY H/W DATE 25/05/2007
SUBJECT TECHNICAL MANUAL PAGE 8/70
Pin Outs
One type of Package for this product, TFBGA 13x13mm, 296balls, 0.65mm pitch package, is offered.
Pin outs and the top view are illustrated in Figure 3,4.
-. Pin Out
Figure 3 . MT6228(7) Pin Out.
-. Top and Bottom View
SDP100 TECHNICAL MANUAL Page 3.8
MODEL SDP100 VERSION V_1.00
PREPARED BY H/W DATE 25/05/2007
SUBJECT TECHNICAL MANUAL PAGE 9/70
Top Masking Definition
Figure 5. Top masking definition
SDP100 TECHNICAL MANUAL Page 3.9
MODEL SDP100 VERSION V_1.00
PREPARED BY H/W DATE 25/05/2007
SUBJECT TECHNICAL MANUAL PAGE 10/70
Pin Description
SDP100 TECHNICAL MANUAL Page 3.10
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