Freescale Semiconductor MPC5200 Montage- und Bedienungsanleitung

Freescale Semiconductor

Application Note

AN3223

Rev. 0, 2/2006

Table of Contents

1 Introduction

This application note describes initialization, general

rules, programming model and performance analysis for

the MPC5200 ATA interface, mainly from a software

perspective. The main focus is to help system architects

understand which mode under what circumstances is

optimalforthefinalproduct.Detailedsoftwareexamples

can be found on the publicly available CD with sample

code for the MPC5200. The MPC5200B microcontroller

is based on an e3001core using the PowerPCTM

instruction set.

The ATA interface is used to connect:

• Hard disks

•CD-ROMs

• DVDs

• Flash storage devices

The MPC5200 ATA interface is fully compatible with

ATA/ATAPI-4 specification (AT Attachment with Packet

InterfaceExtension, ANSI NCITS317-1998)supporting

all three groups of modes:

1. e300, 603e, and G2LE are synonymous.

1 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1

2 ATA Interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2

2.1 Electrical Characteristics . . . . . . . . . . . . . . . . 3

2.2 Signals . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4

2.3 IO Cable. . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5

2.4 Byte Ordering. . . . . . . . . . . . . . . . . . . . . . . . . 5

2.5 Register Addressing . . . . . . . . . . . . . . . . . . . 5

2.6 Sector Addressing . . . . . . . . . . . . . . . . . . . . . 6

2.7 ATA Programming Model . . . . . . . . . . . . . . . 6

2.8 Host Initialization . . . . . . . . . . . . . . . . . . . . . . 9

2.9 Protocols . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9

3 Performance Analysis . . . . . . . . . . . . . . . . . . . . . 14

4 Literature. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16

Appendix A MPC5200 ATA Register Summary

MPC5200 ATA Interface

by: Martin Nykodym

Transportation Standard Products Group

MPC5200 ATA Interface, Rev. 0

ATA Interface

Freescale Semiconductor2

• PIO (from PIO-0 to PIO-4) – up to 16.7 MBytes/sec

• Multiword DMA (from MDMA-0 to MDMA-2) – up to 16.7 MBytes/sec

• Ultra DMA (from UDMA-0 to UDMA-2) – up to 33 MBytes/sec

MPC5200 supports 27-bit and 48-bit LBA addressing on every device.

2ATAInterface

The MPC5200 ATA interface includes three groups of registers:

• ATA host registers – host configuration, timing values for all modes (from PIO, MDMA, UDMA)

• ATA FIFO registers – control ATA FIFO for DMA modes (MDMA, UDMA)

• ATA drive registers – access to the registers physically located on the ATA drive

Figure 1 illustrates basic components of the MPC5200 ATA interface internal to the MPC5200. Data

transfer is driven either by MPC5200 core (PIO) or by the BestComm DMA engine (MDMA, UDMA).

BestComm is designed to offload the MPC5200 core and can transfer data to/from different peripherals

simultaneously. The MPC5200 ATA interface is clocked by the IPBI clock of the MPC5200 processor

(66/132 MHz). MPC5200 acts as an ATA host and can control up to two ATA devices as defined in

ATA/ATAPI-4 specification. Pin ATA_ISOLATION of the MPC5200 (not defined as a signal by

ATA/ATAPI-4 spec) connects to the transceiver’s OE pin to control the direction (high = write to drive,

low = read from drive) of the transfer.

Figure 1. ATA Architecture

BestComm

(higher priority)

IPBI

(lower priority)

Arbiter

ATA Rx/Tx FIFO

Interface

(MDMA/UDMA)

IPBI Interface

(PIO)

ATA Host Interface

MPC5200

ATA_ISOLATION

IPBI clock (66/132 MHz)

ATA 40-pin cable

ATA

Line

Drivers

3.3 V – 5 V

ATA device 0

(e.g. DVD drive)

ATA device 1

(e.g. CompactFlash)

ATA Interface

MPC5200 ATA Interface, Rev. 0

Freescale Semiconductor 3

2.1 Electrical Characteristics

ATA is a voltage level interface and the table below defines the voltage levels for logical ones and zeroes

or input and output values.

2.2 Signals

Table 1. ATA DC Characteristics

Description Min Max

IoL Driver sink current1

NOTES:

1IoL for DASP shall be 12 mA minimum to meet legacy timing and signal integrity.

4mA —

IoH Driver source current2

2IoH value at 400 mA is insufficient in the case of DMARQ that is typically pulled low by a 5.6 kW

resistor.

400 µA—

ViH Voltage input high (logical one) 2.0 Vdc —

ViL Voltage input low (logical zero) — 0.8 Vdc

VoH Voltage output high (IoH=-400 µA, logical one) 2.4 Vdc —

VoL Voltage output low (IoL= 12 mA, logical zero) — 0.5 Vdc

Table 2. ATA Signals

ATA Signal ATA Acronym MPC5200 Pin Direction 40-Pin

ATA Cable

Cable select CSEL — > 28

Chip select 0 CS0- ATA_CSB0 > 37

Chip select 1 CS1- ATA_CSB1 > 38

Data bus bit 0 DD0 ATA_DATA_0 <> 17

Data bus bit 1 DD1 ATA_DATA_1 <> 15

Data bus bit 2 DD2 ATA_DATA_2 <> 13

Data bus bit 3 DD3 ATA_DATA_3 <> 11

Data bus bit 4 DD4 ATA_DATA_4 <> 9

Data bus bit 5 DD5 ATA_DATA_5 <> 7

Data bus bit 6 DD6 ATA_DATA_6 <> 4

Data bus bit 7 DD7 ATA_DATA_7 <> 3

Data bus bit 8 DD8 ATA_DATA_8 <> 4

Data bus bit 9 DD9 ATA_DATA_9 <> 6

Data bus bit 10 DD10 ATA_DATA_10 <> 8

Data bus bit 11 DD11 ATA_DATA_11 <> 10

Data bus bit 12 DD12 ATA_DATA_12 <> 12

Data bus bit 13 DD13 ATA_DATA_13 <> 14

MPC5200 ATA Interface, Rev. 0

ATA Interface

Freescale Semiconductor4

2.3 IO Cable

The cable specification impacts system integrity and the maximum length that shall be supported in any

application. Cable total length shall not exceed 0.46 m (18 in.). Cable capacitance shall not exceed 35 pF.

80-pin grounded cable helps to avoid problems with noise and inductance although 40-pin cable is

sufficient for modes up to UDMA-2 as in the ATA/ATAPI-4 spec. Also ATA/ATAPI-4 compliant

termination is a must; otherwise, CRC checksum error may randomly occur.

Data bus bit 14 DD13 ATA_DATA_14 <> 16

Data bus bit 15 DD14 ATA_DATA_15 <> 18

Device active or slave (Device 1)

present

DASP- — > 39

Device address bit 0 DA0 ATA_SA_0 > 35

Device address bit 1 DA1 ATA_SA_1 > 33

Device address bit 2 DA2 ATA_SA_2 > 36

DMA acknowledge DMACK- ATA_DACK_B > 29

DMA request DMARQ ATA_DRQ < 21

Interrupt request INTRQ ATA_INTRQ < 31

I/O read

DMA ready during Ultra DMA data in

bursts

Data strobe during Ultra DMA data

out bursts

DIOR-

HDMARDY-

HSTROBE

ATA _ I O R _ B >

I/O ready

DMA ready during Ultra DMA data

out bursts

Data strobe during Ultra DMA data in

bursts

IORDY-

DDMARDY-

DSTROBE

ATA_IOCHRDY <

I/O write

Stop during Ultra DMA data bursts

DIOW-

STOP

ATA _ I O W _ B >

Passed diagnostics

Cable assembly type identifier

PDIAG-

CBLID-

-<>34

Reset RESET- HRESET_B > 1

Ground GND 2,19,22,24,

26,

30,40

Table 2. ATA Signals (continued)

ATA Signal ATA Acronym MPC5200 Pin Direction 40-Pin

ATA Cable

ATA Interface

MPC5200 ATA Interface, Rev. 0

Freescale Semiconductor 5

2.4 Byte Ordering

Assuming a block of data contains "n" bytes of information, the bytes are labeled Byte(0) through

Byte(n-1), where Byte(0) is the first byte of the block, and Byte(n-1) is the last byte of the block. Table 3

shows the order of the bytes on the ATA interface.

2.5 Register Addressing

This section describes the generation of the actual address (CSn-, DAn) that is present on the physical ATA

interface to address an ATA drive register by means of operations on internal registers of the MPC5200.

Table 4 shows how internal registers are decoded to ATA bus operations.

Table 3. ATA Byte Ordering

First transfer Byte (1) Byte (0)

Second transfer Byte (3) Byte (2)

...

Last transfer Byte (n-1) Byte (n-2)

Table 4. ATA Register Address/Chip Select Decoding

Addresses Functions

MPC5200

address

CS0- CS1- DA2 DA1 DA0

READ (DIOR-) WRITE (DIOW-)

Control Block Registers

— 1 1 x x x Data bus high impedance Not used

— 1 0 0 x x Data bus high impedance Not used

— 1 0 1 0 x Data bus high impedance Not used

0x3A5C 1 0 1 1 0 Drive alternate status Drive device control

— 1 0 1 1 1 Obsolete Not used

0x3A60 0 1 0 0 0 Drive data Drive data

0x3A64 0 1 0 0 1 Drive error Drive features

0x3A68 0 1 0 1 0 Drive sector count Drive sector count

0x3A6c 0 1 0 1 1 Drive sector number Drive sector number

Drive LBA bits 0-7* Drive LBA bits 0-7*

0x3A70 0 1 1 0 0 Drive cylinder low Drive cylinder low

Drive LBA bits 8-15* Drive LBA bits 8-15*

0x3A74 0 1 1 0 1 Drive cylinder high Drive cylinder high

Drive LBA bits 16-23* Drive LBA bits 16-23*

MPC5200 ATA Interface, Rev. 0

ATA Interface

Freescale Semiconductor6

2.6 Sector Addressing

The addressing of data sectors recorded on the device's media is performed by a logical sector address.

Two modes are supported:

• Cylinder/head/sector addressing (CHS)

• Logical block addressing (LBA)

The MPC5200 host system may select either CHS translation addressing or LBA addressing on a

command-by-command basis by using the LBA bit in the ATA drive device/head register. The LBA bit

must be set if the host uses LBA addressing mode. The MPC5200 allows 27-bit LBA addressing per

device.

2.7 ATA Programming Model

Figure 2 describes the typical structure and sequence of steps needed to initialize and issue ATA

commands for MPC5200.

0x3A78 0 1 1 1 0 Drive device/head Drive device/head

Drive LBA bits 24-27* Drive LBA bits 24-27*

0x3A7C 0 1 1 1 1 Drive device status Drive command

— 0 0 x x x Invalid address Invalid address

*Mapping of registers in LBA mode

Table 4. ATA Register Address/Chip Select Decoding (continued)

ATA Interface

MPC5200 ATA Interface, Rev. 0

Freescale Semiconductor 7

Figure 2. MPC5200 ATA Programming Model

A BestComm task loader is needed if there is some peripheral requiring DMA transfer over the FIFOs

to/from a peripheral (ATA MDMA/UDMA, Ethernet, LocalPlus, PCI, etc.). The BestComm image is

downloaded and initialized only once, right after booting, due to the static content of the BestComm image

(image means BestComm binary firmware). The BestComm image acts as a server that serves clients

(peripheral software drivers).

It is recommended to start with the software examples published on the sample code CD. These software

examples include a set of already “pre-cooked” BestComm tasks that handle all required peripherals via

the BestComm C-API (BAPI). The system integrator needs to recompile all drivers in the case of any

change in the image. This guarantees compatible versions for both BestComm firmware and software

drivers.

Figure 3 documents the structure for the MDMA/UDMA data transfer.

BestComm task loader

Download BestComm image

Set task priorities

Initialize BestComm variables

can be restarted at any time

ATA driver

Set cached ATA memory regions

Initialize ATA host (MPC5200)

Initialize ATA device

(e.g. hard disk, CD-ROM, DVD)

Execute ATA command

according specified protocol

MPC5200 ATA Interface, Rev. 0

ATA Interface

Freescale Semiconductor8

Figure 3. MDMA/UDMA BestComm Driven Data Transfer

The BestComm C-API is not resident software. It is a piece of software statically linked to the driver that

includes a set of standardized function calls.

ATA device

(e.g., DVD drive)

ATA cable

MDMA/UDMA data

ATA data

buffers ATA software driver

ATA level shifters

ATA host interface

MPC5200

Embedded computer

Peripheral FIFOs

Set of “pre-cooked”

tasks

Data transfer driven

by BestComm

ATA Rx/Tx FIFO

BestComm

BestComm image in

MPC5200 SRAM

ATA task

BestComm C-API

Set of peripheral

drivers and their

data buffers

Application 1

(e.g., DVD player)

Application 2

(e.g., MP3 player)

SDR/DDR memory

ATA Interface

MPC5200 ATA Interface, Rev. 0

Freescale Semiconductor 9

The following steps should be used to set up the cache for ATA memory buffer regions:

• Set DBAT registers and enable data cache.2(See Programming Environments Manual for 32-Bit

Implementations of the PowerPC Architecture for details.)

• Set XLB priorities in the XLB arbiter master priority register and enable XLB priorities in the

arbiter master priority enable register.3(See the XLB Arbiter chapter in the MPC5200 User’s

Manual for details.)

• Set window address, size and snooping policy in the XLB arbiter snoop window register and

enable snooping in the XLB arbiter configuration register.4(See the XLB Arbiter chapter in the

MPC5200 User’s Manual for details.)

2.8 Host Initialization

The MPC5200 ATA host initialization covers three different groups of steps:

1. ATA common initialization

— Set ATA chip select in GPS port configuration register

— Read IPBI clock speed in CDM configuration register (66 or 132 MHz) needed for timing

registers)5

— Enable ATA clock in CDM clock enable register

— Install ATA interrupt handler and BestComm interrupt handler for MDMA/UDMA modes

— Enable ATA/BestComm interrupt

2. PIO initialization (BestComm not needed for PIO modes)

— Set PIO timing registers

— Enable drive interrupt (to pass to CPU in PIO modes) in ATA host configuration register

(IE bit)

— Enable IORDY in ATA host configuration register (for PIO-3 and above)

3. MDMA/UDMA initialization

— Set either MDMA or UDMA timing registers

2.9 Protocols

ATA commands written into the ATA drive device command register are grouped into different classes

according to the protocols. The protocols define the command execution flow. The command classes with

their associated protocols are defined in Table 5.

The following sections directly document the commands instead of providing a detailed general

description for each protocol. The addressing scheme and the handling of some of the commands are

usually provided in linkable libraries by operating system vendors; therefore, the following description is

2. Usually entire memory cached, initialized by bootloader

3. Initialized by bootloader

4. Set up by driver

5. Bootloader sets up IPBI clock speed, peripheral drivers should read status only

MPC5200 ATA Interface, Rev. 0

ATA Interface

Freescale Semiconductor10

intended to help software engineers understand how to initialize the MPC5200 ATA interface and how to

execute standard commands.

NOTE

Flash storage media require a different set of commands that are not

described in this application note. It is recommended to first read the

identify table for each ATA device found on the ATA bus. It contains

specific information needed to handle the device properly. For protocol and

identification information details, see Attachment with Packet Interface

Extension, ANSI NCITS 317-1998.

2.9.1 Drive Initialization

2.9.1.1 PIO Initialization Protocol Steps

1. Select drive according to device selection protocol in ATA/ATAPI-4 spec:

a) Wait for BSY6=0 and DRQ7= 0 in ATA drive alternate status register

Table 5. ATA Protocols

Protocol Commands

Device reset protocol —

Execute device diagnostic

protocol

—

Device selection protocol —

PIO data-in command protocol CFA TRANSLATE SECTOR, IDENTIFY DEVICE, IDENTIFY PACKET DEVICE, READ BUFFER,

READ MULTIPLE, READ SECTOR(S), SMART READ DATA

PIO data-out command protocol CFA WRITE MULTIPLE WITHOUT ERASE, CFA WRITE SECTORS WITHOUT ERASE,

DOWNLOAD MICROCODE, SECURITY DISABLE PASSWORD, SECURITY ERASE UNIT,

SECURITY SET PASSWORD, SECURITY UNLOCK, WRITE BUFFER, WRITE MULTIPLE,

WRITE SECTOR(S)

Non-data command protocol CFA ERASE SECTORS, CFA REQUEST EXTENDED ERROR CODE, CHECK POWER MODE,

FLUSH CACHE, GET MEDIA STATUS IDLE, IDLE IMMEDIATE, INITIALIZE DEVICE

PARAMETERS, MEDIA EJECT, MEDIA LOCK, MEDIA UNLOCK, NOP, READ NATIVE MAX

ADDRESS, READ VERIFY SECTOR(S, SECURITY ERASE PREPARE, SECURITY FREEZE

LOCK SEEK, SET FEATURES, SET MAX ADDRESS, SET MULTIPLE MODE SLEEP, SMART

DISABLE OPERATION, SMART ENABLE/DISABLE AUTOSAVE, SMART ENABLE

OPERATION, SMART EXECUTE OFFLINE IMMEDIATE, SMART RETURN STATUS,

STANDBY, STANDBY IMMEDIATE

DMA command protocol READ DMA, WRITE DMA

Packet non-data and PIO data

command protocol

PACKET, SERVICE

Packet DMA command protocol PACKET, SERVICE

Read/write DMA queued

command protocol

READ DMA QUEUED, SERVICE, WRITE DMA QUEUED

6. BSY - The Drive Busy bit indicates that the device is busy.

7. DRQ - The Data Request bit indicates that the device is ready to transfer a word of data between the host and the device.

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