Fujitsu MB15F74UV Bedienungsanleitung

DS04-21381-1E

FUJITSU SEMICONDUCTOR

DATA SHEET

ASSP

Dual Serial Input

PLL Frequency Synthesizer

MB15F74UV

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■■

■DESCRIPTION

The Fujitsu MB15F74UV is a serial input Phase Locked Loop (PLL) frequency synthesizer with a 4000 MHz and

a 2000 MHz prescalers. A 64/65 or a 128/129 for the 4000 MHz prescaler, and a 32/33 or a 64/65 for the

2000 MHz prescaler can be selected for the prescaler that enables pulse swallow operation.

The BiCMOS process is used, as a result a supply current is typically 9.0 mA at 3.0 V. The supply voltage range

is from 2.7 V to 3.6 V. A refined charge pump supplies well-balanced output current with 1.5 mA and 6 mA

selectable by serial date. The serial data format is the same as MB15F74UL. Fast locking is achieved for adopting

the new circuit.

MB15F74UV is in the small package (BCC18) which decreases a mount area of MB15F74UV about 50%com-

paring with the former BCC20 (for dual PLL) .

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■FEATURES

• High frequency operation : RF synthesizer : 4000 MHz Max

: IF synthesizer : 2000 MHz Max

• Low power supply voltage : VCC =2.7 V to 3.6 V

• Ultra low power supply current : ICC =9.0 mA Typ

(VCC =3.0 V, Ta =+25 °C, SWIF =SWRF =0 in IF/RF locking state)

(Continued)

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■■

■PACKAGE

18-pin plastic BCC

(LCC-18P-M05)

MB15F74UV

(Continued)

• Direct power saving function : Power supply current in power saving mode

Typ 0.1 µA (VCC =3.0 V, Ta =+25 °C at 1 system)

Max 10 µA (VCC =3.0 V at 1 system)

• Software selectable charge pump current : 1.5 mA/6.0 mA Typ

• Dual modulus prescaler : 4000 MHz prescaler (64/65 or128/129) /2000 MHz prescaler (32/33 or 64/65)

• 23 bit shift register

• Serial input binary 14-bit programmable reference divider : R =3 to 16,383

• Serial input programmable divider consisting of:

- Binary 7-bit swallow counter : 0 to 127

- Binary 11-bit programmable counter : 3 to 2,047

• Built-in high-speed tuning, low-noise phase comparator, current-switching type constant current circuit

• On-chip phase control for phase comparator

• On-chip phase comparator for fast lock and low noise

• Built-in digital locking detector circuit to detect PLL locking and unlocking

• Operating temperature : Ta =−40 °C to +85 °C

• Serial data format compatible with MB15F74UL

• Ultra small package BCC18 (2.4 mm ×2.7 mm ×0.45 mm)

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■PIN ASSIGNMENTS

TOP VIEW

(LCC-18P-M05)

GND

finIF

XfinIF

GNDIF

VCCIF

DOIF

finRF

XfinRF

GNDRF

VCCRF

DORF

78910

18 17

PSIF PSRF

LD/fout

OSCIN Data

Clock

16 14

MB15F74UV

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■PIN DESCRIPTION

Pin no. Pin

name I/O Descriptions

1GNDGround pin for OSC input buffer and the shift register circuit.

2fin

IF IPrescaler input pin for the IF-PLL.

Connection to an external VCO should be AC coupling.

3Xfin

IF IPrescaler complimentary input for the IF-PLL section.

This pin should be grounded via a capacitor.

4GNDIF Ground pin for the IF-PLL section.

CCIF Power supply voltage input pin for the IF-PLL section, the shift register and the oscillator

input buffer.

6Do

IF O Charge pump output for the IF-PLL section.

7PSIF I

Power saving mode control pin for the IF-PLL section. This pin must be set at “L” when

the power supply is started up. (Open is prohibited.)

PSIF =“H” ; Normal mode/PSIF =“L” ; Power saving mode

8 LD/fout O Lock detect signal output (LD) /phase comparator monitoring output (fout) pin. The out-

put signal is selected by LDS bit in a serial data.

LDS bit =“H” ; outputs fout signal/LDS bit =“L” ; outputs LD signal

9PS

RF IPower saving mode control for the RF-PLL section. This pin must be set at “L” when the

power supply is started up. (Open is prohibited. )

PSRF =“H” ; Normal mode/PSRF =“L” ; Power saving mode

10 DoRF O Charge pump output for the RF-PLL section.

11 VCCRF Power supply voltage input pin for the RF-PLL section.

12 GNDRF Ground pin for the RF-PLL section

13 XfinRF IPrescaler complimentary input pin for the RF-PLL section.

This pin should be grounded via a capacitor.

14 finRF IPrescaler input pin for the RF-PLL.

Connection to an external VCO should be via AC coupling.

15 LE I Load enable signal input pin (with the schmitt trigger circuit)

When LE is set “H”, data in the shift register is transferred to the corresponding latch ac-

cording to the control bit in a serial data.

16 Data I Serial data input pin (with the schmitt trigger circuit)

Data is transferred to the corresponding latch (IF-ref. counter, IF-prog. counter,

RF-ref. counter, RF-prog. counter) according to the control bit in a serial data.

17 Clock I Clock input pin for the 23-bit shift register (with the schmitt trigger circuit)

One bit data is shifted into the shift register on a rising edge of the clock.

18 OSCIN IThe programmable reference divider input pin. TCXO should be connected with an AC

coupling capacitor.

MB15F74UV

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■BLOCK DIAGRAM

(10)

Clock

Data

PSRF

XfinRF

finRF

OSCIN

finIF

PSIF

VCCIF GNDIF

fpIF

DoIF

LDIF

T1 T2

FCRF

SWRF

LDS

DoRF

OR LD/

fout

frIF

frRF

fpIF

fpRF

frIF

frRF

fpRF

AND

VCCRF GNDRF

(18)

( )

(9)

(16)

(17)

(11) (12)

(8)

(6)

(4)

(5)

(2)

(7)

(14)

GND

(1)

(15)

XfinIF (3)

Intermittent

mode control

(IF-PLL)

Prescaler

(IF-PLL)

(32/33, 64/65)

7 bit latch 11 bit latch

Binary 7-bit

swallow counter

(IF-PLL)

Binary 11-bit

programmable

counter (IF-PLL)

Phase

comp.

(IF-PLL)

Charge

pump

(IF-PLL)

Current

Switch

2 bit latch 14 bit latch 1 bit latch

Binary 14-bit pro-

grammable ref.

counter(IF-PLL) C/P setting

counter

Lock Det.

(IF-PLL)

2 bit latch 14 bit latch 1 bit latch

Binary 14-bit pro-

grammable ref.

counter (RF-PLL)) C/P setting

counter

Selector

Prescaler

(RF-PLL)

(64/65, 128/129) Lock Det.

(RF-PLL)

Intermittent

mode control

(RF-PLL) 3 bit latch

FCIF

SWIF

LDS

3 bit latch

7 bit latch 11 bit latch

Binary 7-bit

swallow counter

(RF-PLL)

Binary 11-bit

programmable

counter (RF-PLL)

Phase

comp.

(RF-PLL)

Fast lock

Tuning

Charge

pump

(RF-PLL)

Current

Switch

Schmitt

trigger

circuit Latch selector

23-bit shift register

Fast

lock

Tuning

LDRF

fpRF

Fast

lock

Tuning

Schmitt

trigger

circuit

Schmitt

trigger

circuit

MB15F74UV

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■■

■ABSOLUTE MAXIMUM RATINGS

WARNING: Semiconductor devices can be permanently damaged by application of stress (voltage, current,

temperature, etc.) in excess of absolute maximum ratings. Do not exceed these ratings.

■

■■

■RECOMMENDED OPERATING CONDITIONS

Note : •VCCRF and VCCIF must supply equal voltage.

Even if either RF-PLL or IF-PLL is not used, power must be supplied to VCCRF and VCCIF to keep them

equal.

It is recommended that the non-use PLL is controlled by power saving function.

•Although this device contains an anti-static element to prevent electrostatic breakdown and the circuitry

hasbeenimprovedin electrostatic protection,observe thefollowing precautions whenhandling the device.

•When storing and transporting the device, put it in a conductive case.

•Beforehandlingthedevice,confirmthe (jigsand)toolstobeusedhavebeenuncharged(grounded)as

well as yourself. Use a conductive sheet on working bench.

•Before fitting the device into or removing it from the socket, turn the power supply off.

•When handling (such as transporting) the device mounted board, protect the leads with a conductive

sheet.

WARNING: The recommended operating conditions are required in order to ensure the normal operation of the

semiconductor device. All of the device’s electrical characteristics are warranted when the device is

operated within these ranges.

Always use semiconductor devices within their recommended operating condition ranges. Operation

outside these ranges may adversely affect reliability and could result in device failure.

No warranty is made with respect to uses, operating conditions, or combinations not represented on

the data sheet. Users considering application outside the listed conditions are advised to contact their

FUJITSU representatives beforehand.

Parameter Symbol Rating Unit

Min Max

Power supply voltage VCC −0.5 4.0 V

Input voltage VI−0.5 VCC +0.5 V

Output voltage LD/fout VOGND VCC V

DoIF, DoRF VDO GND VCC V

Storage temperature Tstg −55 +125 °C

Parameter Symbol Value Unit Remarks

Min Typ Max

Power supply voltage VCC 2.7 3.0 3.6 V VCCRF =VCCIF

Input voltage VIGND VCC V

Operating temperature Ta −40 +85 °C

MB15F74UV

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■ELECTRICAL CHARACTERISTICS (VCC =2.7 V to 3.6 V, Ta =−40 °C to +85 °C)

(Continued)

Parameter Symbol Condition Value Unit

Min Typ Max

Power supply current ICCIF *1finIF =2000 MHz

VCCIF =3.0 V 2.1 2.5 3.2 mA

ICCRF *1finRF =2500 MHz

VCCRF =3.0 V 5.7 6.5 8.4 mA

Power saving current IPSIF PSIF =PSRF =“L” 0.1*210 µA

IPSRF PSIF =PSRF =“L” 0.1*210 µA

Operating frequency

finIF *3finIF IF PLL 200 2000 MHz

finRF *3finRF RF PLL 2000 4000 MHz

OSCIN fOSC 340 MHz

Input sensitivity finIF PfinIF IF PLL, 50 Ωsystem −15 +2dBm

finRF PfinRF RF PLL, 50 Ωsystem −10 +2dBm

Input available voltage OSCIN VOSC 0.5 1.0 1.5 VP-P

“H” level input voltage Data

Clock

VIH Schmitt trigger input 0.7 VCC

+0.4 V

“L” level input voltage VIL Schmitt trigger input 

0.3 VCC

−0.4 V

“H” level input voltage PSIF

PSRF

VIH 0.7 VCC V

“L” level input voltage VIL 0.3 VCC V

“H” level input current Data

Clock

IIH *4−1.0 +1.0 µA

“L” level input current IIL *4−1.0 +1.0 µA

“H”level output voltage LD/

fout VOH VCC =3.0 V, IOH =−1 mA VCC −0.4 V

“L” level output voltage VOL VCC =3.0 V, IOL =1 mA 0.4 V

“H”level output voltage DoIF

DoRF

VDOH VCC =3.0 V, IDOH =−0.5 mA VCC −0.4 V

“L” level output voltage VDOL VCC =3.0 V, IDOL =0.5 mA 0.4 V

High impedance cutoff

current DoIF

DoRF IOFF VCC =3.0 V

VOFF =0.5 V to VCC −0.5 V 2.5 nA

“H” level output current LD/

fout IOH *4VCC =3.0 V −1.0 mA

“L” level output current IOL VCC =3.0 V 1.0 mA

“H” level output current DoIF *8

DoRF IDOH *4VCC =3.0 V,

VDOH =VCC /2,

Ta =+25 °C

CS bit =“1” −8.2 −6.0 −4.1 mA

CS bit =“0” −2.2 −1.5 −0.8 mA

“L” level output current DoIF *8

DoRF IDOL VCC =3.0 V,

VDOL =VCC /2,

Ta =+25 °C

CS bit =“1” 4.1 6.0 8.2 mA

CS bit =“0” 0.8 1.5 2.2 mA

MB15F74UV

(Continued)

(VCC =2.7 V to 3.6 V, Ta =−40 °C to +85 °C)

*1 : Conditions ; fosc =12.8 MHz, Ta =+25 °C, SW =“0” in locking state.

*2 : VCCIF =VCCRF =3.0 V, fosc =12.8 MHz, Ta =+25 °C, in power saving mode.

PSIF =PSRF =GND

VIH =VCC, VIL =GND (at CLK, Data, LE)

*3 : AC coupling. 1000 pF capacitor is connected under the condition of Min operating frequency.

*4 : The symbol “–” (minus) means the direction of current flow.

*5 : VCC =3.0 V, Ta =+25 °C (||I3| −|I4||) /[ (|I3| +|I4|) /2] ×100 (%)

*6 : VCC =3.0 V, Ta =+25 °C [ (||I2| −|I1||) /2] /[ (|I1| +|I2|) /2] ×100 (%) (Applied to both lDOL and lDOH)

*7 : VCC =3.0V,[||IDO (+85 °C)|−|IDO (–40 °C)||/2]/[|IDO (+85 °C)|+|IDO (–40 °C)|/2]×100(%) (AppliedtobothIDOL andIDOH)

*8 : When Charge pump current is measured, set LDS =“0” , T1 =“0” and T2 =“1”.

Parameter Symbol Condition Value Unit

Min Typ Max

Charge pump

current rate

IDOL/IDOH IDOMT *5VDO =VCC /2 310%

vs VDO IDOVD *60.5 V ≤VDO ≤VCC −0.5 V 10 15 %

vs Ta IDOTA *7−40 °C ≤Ta ≤85 °C,

VDO =VCC /2 510%

IDOL

I1I3I2

0.5 VCC/2 VCC −0.5 VCC

IDOH

Charge pump output voltage (V)

MB15F74UV

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■FUNCTIONAL DESCRIPTION

1. Pulse swallow function

fVCO =[ (P ×N) +A] ×fOSC ÷R

fVCO : Output frequency of external voltage controlled oscillator (VCO)

P : Preset divide ratio of dual modulus prescaler (32 or 64 for IF-PLL, 64or 128 for RF-PLL)

N : Preset divide ratio of binary 11-bit programmable counter (3 to 2,047)

A : Preset divide ratio of binary 7-bit swallow counter (0 ≤A ≤127, A < N)

fOSC : Reference oscillation frequency (OSCIN input frequency)

R : Preset divide ratio of binary 14-bit programmable reference counter (3 to 16,383)

2. Serial Data Input

The serial data is entered using three pins, Data pin, Clock pin, and LE pin. Programmable dividers of IF/RF-

PLL sections, programmable reference dividers of IF/RF-PLL sections are controlled individually.

The serial data of binary data is entered through Data pin.

On rising edge of Clock, one bit of the serial data is transferred into the shift register. On a rising edge of load

enable signal, the data stored in the shift register is transferred to one of latches depending upon the control bit

data setting.

(1) Shift Register Configuration

The programmable

reference counter

for the IF-PLL

The programmable

reference counter

for the RF-PLL

The programmable

counter and the swallow

counter for the IF-PLL

The programmable

counter and the swallow

counter for the RF-PLL

CN1 0 1 0 1

CN2 0 0 1 1

•Programmable Reference Counter

CS : Charge pump current select bit

R1 to R14 : Divide ratio setting bits for the programmable reference counter (3 to 16,383)

T1, T2 : LD/fout output setting bit

CN1, CN2 : Control bit

X : Dummy bits (Set “0” or “1”)

Note : Data input with MSB first.

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23

CN1 CN2 T1 T2 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 CS X X X X

(LSB) (MSB)Data Flow

MB15F74UV

(2) Data setting

•Binary 14-bit Programmable Reference Counter Data Setting

Note : Divide ratio less than 3 is prohibited.

•Binary 11-bit Programmable Counter Data Setting

Note : Divide ratio less than 3 is prohibited

•Binary 7-bit Swallow Counter Data Setting

DivideratioR14R13R12R11R10R9R8R7R6R5R4R3R2R1

3 00000000000011

•

16383

•

DivideratioN11N10N9N8N7N6N5N4N3N2N1

3 00000000011

•

2047

•

DivideratioA7A6A5A4A3A2A1

0 0000000

•

127

•

• Programmable Counter

A1 to A7 : Divide ratio setting bits for the swallow counter (0 to 127)

N1 to N11 : Divide ratio setting bits for the programmable counter (3 to 2,047)

LDS : LD/fout signal select bit

SWIF/SWRF : Divide ratio setting bit for the prescaler (IF : SWIF, RF : SWRF)

FCIF/FCRF : Phase control bit for the phase detector (IF : FCIF, RF : FCRF)

CN1, CN2 : Control bit

Note : Data input with MSB first.

1 2 3 4 5 6 7 8 9 101112131415161718192021 22 23

CN1 CN2 LDS SWIF/

SWRF FCIF/

FCRF A1 A2 A3 A4 A5 A6 A7 N1 N2 N3 N4 N5 N6 N7 N8 N9 N10 N11

(LSB) (MSB)

Data Flow

MB15F74UV

•Prescaler Data Setting

• Charge Pump Current Setting

•LD/fout output Selectable Bit Setting

•Phase Comparator Phase Switching Data Setting

Z: High-impedance

Depending upon the VCO and LPF polarity, FC bit should be set.

Divide ratio SW =

=“1” SW =

=“0”

Prescaler divide ratio IF-PLL 32/33 64/65

Prescaler divide ratio RF-PLL 64/65 128/129

Current value CS

±6.0 mA 1

±1.5 mA 0

LD/fout pin state LDS T1 T2

LD output

000

010

011

fout

output

frIF 100

frRF 110

fpIF 101

fpRF 111

Phase comparator input FCIF, RF =

=“1” FCIF, RF =

=“0”

DoIF, DoRF DoIF, DoRF

fr >fp H L

fr <fp L H

fr =fp Z Z

(1)

(2)

(1) VCO polarity FC =“1”

(2) VCO polarity FC =“0”

Note : Give attention to the polarity for using active type LPF.

VCO Output

Frequency

High

LPF Output voltage Max

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