GE MiCOM P40 Agile Bedienungsanleitung

GE Energy Connections

Grid Solutions

MiCOM P40 Agile

P543i/P545i

Technical Manual

Single Breaker Current Differential (with Distance)

Hardware Version: M

Software Version: 85

Publication Reference: P54x1i-TM-EN-1

Contents

Chapter 1 Introduction 1

1 Chapter Overview 3

2 Foreword 4

2.1 Target Audience 4

2.2 Typographical Conventions 4

2.3 Nomenclature 5

2.4 Compliance 5

3 Product Scope 6

3.1 Product Versions 6

3.1.1 Ordering Options 7

4 Features and Functions 8

4.1 Current Differential Protection Functions 8

4.2 Distance Protection Functions 8

4.3 Protection Functions 8

4.4 Control Functions 9

4.5 Measurement Functions 10

4.6 Communication Functions 10

5 Logic Diagrams 11

6 Functional Overview 13

Chapter 2 Safety Information 15

1 Chapter Overview 17

2 Health and Safety 18

3 Symbols 19

4 Installation, Commissioning and Servicing 20

4.1 Lifting Hazards 20

4.2 Electrical Hazards 20

4.3 UL/CSA/CUL Requirements 21

4.4 Fusing Requirements 21

4.5 Equipment Connections 22

4.6 Protection Class 1 Equipment Requirements 22

4.7 Pre-energisation Checklist 23

4.8 Peripheral Circuitry 23

4.9 Upgrading/Servicing 24

5 Decommissioning and Disposal 25

6 Regulatory Compliance 26

6.1 EMC Compliance: 2014/30/EU 26

6.2 LVD Compliance: 2014/35/EU 26

6.3 R&TTE Compliance: 2014/53/EU 26

6.4 UL/CUL Compliance 26

6.5 ATEX Compliance: 2014/34/EU 26

Chapter 3 Hardware Design 29

1 Chapter Overview 31

2 Hardware Architecture 32

2.1 Coprocessor Hardware Architecture 32

3 Mechanical Implementation 34

3.1 Housing Variants 34

3.2 List of Boards 35

4 Front Panel 37

4.1 Front Panel 37

4.1.1 Front Panel Compartments 37

4.1.2 Keypad 38

4.1.3 Front Serial Port (SK1) 38

4.1.4 Front Parallel Port (SK2) 39

4.1.5 Fixed Function LEDs 39

4.1.6 Function Keys 39

4.1.7 Programable LEDs 40

5 Rear Panel 41

6 Boards and Modules 43

6.1 PCBs 43

6.2 Subassemblies 43

6.3 Main Processor Board 44

6.4 Power Supply Board 45

6.4.1 Watchdog 47

6.4.2 Rear Serial Port 48

6.5 Input Module - 1 Transformer Board 49

6.5.1 Input Module Circuit Description 50

6.5.2 Transformer Board 51

6.5.3 Input Board 52

6.6 Standard Output Relay Board 53

6.7 IRIG-B Board 54

6.8 Fibre Optic Board 55

6.9 Rear Communication Board 56

6.10 Ethernet Board 56

6.11 Redundant Ethernet Board 58

6.12 Coprocessor Board 60

6.12.1 Current Differential Inputs 60

6.12.2 Coprocessor board with 1PPS input 60

Chapter 4 Software Design 63

1 Chapter Overview 65

2 Sofware Design Overview 66

3 System Level Software 67

3.1 Real Time Operating System 67

3.2 System Services Software 67

3.3 Self-Diagnostic Software 67

3.4 Startup Self-Testing 67

3.4.1 System Boot 67

3.4.2 System Level Software Initialisation 68

3.4.3 Platform Software Initialisation and Monitoring 68

3.5 Continuous Self-Testing 68

4 Platform Software 70

4.1 Record Logging 70

4.2 Settings Database 70

4.3 Interfaces 70

5 Protection and Control Functions 71

5.1 Acquisition of Samples 71

5.2 Frequency Tracking 71

5.3 Direct Use of Sample Values 71

5.4 System Level Software Initialisation 71

5.5 Distance Protection 72

5.6 Fourier Signal Processing 72

5.7 Programmable Scheme Logic 73

5.8 Event Recording 74

5.9 Disturbance Recorder 74

5.10 Fault Locator 74

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ii P54x1i-TM-EN-1

5.11 Function Key Interface 74

Chapter 5 Configuration 75

1 Chapter Overview 77

2 Settings Application Software 78

3 Using the HMI Panel 79

3.1 Navigating the HMI Panel 80

3.2 Getting Started 80

3.3 Default Display 81

3.4 Default Display Navigation 82

3.5 Password Entry 83

3.6 Processing Alarms and Records 83

3.7 Menu Structure 84

3.8 Changing the Settings 85

3.9 Direct Access (The Hotkey menu) 86

3.9.1 Setting Group Selection Using Hotkeys 86

3.9.2 Control Inputs 86

3.9.3 Circuit Breaker Control 87

3.10 Function Keys 87

4 Line Parameters 89

4.1 Tripping Mode 89

4.1.1 CB Trip Conversion Logic Diagram 89

4.2 Residual Compensation 90

4.3 Mutual Compensation 90

5 Date and Time Configuration 92

5.1 Using an SNTP Signal 92

5.2 Using an IRIG-B Signal 92

5.3 Using an IEEE 1588 PTP Signal 92

5.4 Without a Timing Source Signal 93

5.5 Time Zone Compensation 93

5.6 Daylight Saving Time Compensation 94

6 Settings Group Selection 95

Chapter 6 Current Differential Protection 97

1 Chapter Overview 99

2 Current Differential Protection Principle 100

2.1 Numerical Current Differential Protection 100

3 Synchronisation of Current Signals 102

3.1 Time Alignment using Ping-Pong Technique 102

3.2 GPS Synchronisation 103

4 Phase Current Differential Protection 105

4.1 Phase Current Differential Tripping Criteria 106

4.2 Phase Current Differential Protection Logic 107

5 Neutral Current Differential Protection 108

6 Three-Terminal Schemes 109

6.1 Three-Terminal Scheme Reconfiguration on Energisation 110

7 Transient Bias 111

8 Capacitive Charging Current Compensation 112

9 CT Compensation 113

10 Feeders with In-Zone Transformers 114

10.1 CT Phase Correction 114

10.2 Zero Sequence Filtering 115

10.3 Magnetising Inrush Restraint 116

10.3.1 Second Harmonic Restraint 117

10.4 Overfluxing Restraint 119

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P54x1i-TM-EN-1 iii

10.4.1 Fifth Harmonic Blocking 119

10.5 Logic for Feeders with In-Zone Transformers 120

10.6 Second Harmonic Blocking Logic 121

10.7 Fifth Harmonic Blocking Logic 122

11 Current Differential Intertripping 123

12 Stub Bus Differential Protection 124

13 Application Notes 125

13.1 Setting Up the Phase Differential Characteristic 125

13.2 Sensitivity Under Heavy Loads 126

13.3 Permissive Intertripping 127

13.4 CT Ratio Correction Setting Guidelines 127

13.5 Feeders with Small Tapped Loads 128

13.6 Setting a Two-Terminal Phase Current Differential Element 128

13.7 Setting a Three-Terminal Phase Current Differential Element 129

Chapter 7 Distance Protection 133

1 Chapter Overview 135

2 Introduction 136

2.1 Distance Protection Principle 136

2.2 Performance Influencing Factors 136

2.3 Impedance Calculation 137

2.4 Implementation with Comparators 137

2.5 Polarization of Distance Characteristics 137

3 Distance Measuring Zones Operating Principles 138

3.1 Mho Characteristics 139

3.1.1 Directional Mho Characteristic for Phase Faults 139

3.1.2 Offset Mho Characteristic for Phase Faults 139

3.1.3 Directional Self-Polarized Mho Characteristic for Earth Faults 140

3.1.4 Offset Mho Characteristic for Earth Faults 142

3.1.5 Memory Polarization of Mho Characteristics 144

3.1.6 Dynamic Mho Expansion and Contraction 144

3.1.7 Cross Polarization of Mho Characteristics 147

3.1.8 Implementation of Mho Polarization 148

3.2 Quadrilateral Characteristic 149

3.2.1 Directional Quadrilaterals 150

3.2.2 Earth Fault Quadrilateral Characteristics 154

3.3 Quadrilateral Characteristic for Phase Faults 162

3.3.1 Phase Fault Impedance Reach Line 163

3.3.2 Phase Fault Reverse Impedance Reach Line 163

3.3.3 Phase Fault Resistive Reach Line 164

3.3.4 Phase Fault Reverse Resistive Reach Line 166

3.3.5 Phase Fault Quadrilateral Characteristic Summary 166

4 Phase and Earth Fault Distance Protection Implementation 168

4.1 Phase Fault Characteristics 168

4.2 Earth Fault Characteristics 168

4.3 Distance Protection Tripping Decision 168

4.4 Distance Protection Phase Selection 169

4.4.1 Faulted Phase Selection 169

4.5 Biased Neutral Current Detector 170

4.6 Distance Element Zone Settings 171

4.6.1 Directionalizing the Distance Elements 171

4.6.2 Advanced Distance Zone Settings 172

4.6.3 Distance Zone Sensitivities 172

4.7 Capacitor VT Applications 173

4.7.1 CVTs with Passive Suppression of Ferroresonance 173

4.7.2 CVTs with Active Suppression of Ferroresonance 173

4.8 Load Blinding 174

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iv P54x1i-TM-EN-1

4.9 Cross Country Fault Protection 175

5 Delta Directional Element 176

5.1 Delta Directional Principle and Setup 176

5.2 Delta Directional Decision 177

6 Distance Isolated and Compensated Systems 179

6.1 Peterson Coil Earthed Systems 179

6.2 Earth Fault Distance Protection for Isolated and Compensated Systems 182

6.2.1 Single-phase to Earth Faults on Isolated or Compensated Systems 183

6.2.2 Cross-Country Faults on Isolated or Compensated Systems 183

6.3 Implementation of Distance Protection for Isolated and Compensated Networks 184

6.3.1 Network Earthing System Setting 184

6.3.2 First Earth FaultDetection 184

6.3.3 Fault Detection Logic 186

6.3.4 Phase Preferential Logic 187

7 Application Notes 193

7.1 Setting Mode Choice 193

7.2 Operating Characteristic Selection 193

7.2.1 Phase Characteristic 193

7.2.2 Earth Fault Characteristic 194

7.3 Zone Reach Setting Guidelines 194

7.3.1 Quadrilateral Resistive Reaches 195

7.4 Earth Fault Resistive Reaches and Tilting 195

7.4.1 Dynamic Tilting 196

7.4.2 Fixed Tilting 197

7.5 Phase Fault Zone Settings 197

7.6 Directional Element for Distance Protection 198

7.7 Filtering Setup 198

7.7.1 Distance Digital Filter 198

7.7.2 Setting up CVTs 198

7.8 Load Blinding Setup 199

7.9 Polarizing Setup 199

7.10 Delta Directional Element Setting Guidelines 200

7.10.1 Delta Thresholds 200

7.11 Distance Protection Worked Example 201

7.11.1 Line Impedance Calculation 202

7.11.2 Residual Compensation for Earth Fault Elements 202

7.11.3 Zone 1 Phase and Ground Reach Settings 202

7.11.4 Zone 2 Phase and Ground Reach Settings 203

7.11.5 Zone 3 Phase and Ground Reach Settings 203

7.11.6 Zone 3 Reverse Reach Settings 203

7.11.7 Zone 4 Reverse Reach Settings 203

7.11.8 Load Avoidance 204

7.11.9 Quadrilateral Resistive Reach Settings 204

7.12 Teed Feeder Applications 206

Chapter 8 Carrier Aided Schemes 207

1 Chapter Overview 209

2 Introduction 210

3 Carrier Aided Schemes Implementation 211

3.1 Carrier Aided Scheme Types 211

3.2 Default Carrier Aided Schemes 212

4 Aided Distance Scheme Logic 213

4.1 Permissive Underreach Scheme 213

4.2 Permissive Over-reach Scheme 214

4.2.1 Permissive Overreach Trip Reinforcement 216

4.2.2 Permissive Overreach Weak Infeed Features 217

4.3 Permissive Scheme Loss Of Guard 217

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P54x1i-TM-EN-1 v

4.4 Current Reversal Guard Logic 218

4.5 Aided Distance Blocking Schemes 219

4.6 Aided Distance Unblocking Schemes 220

4.7 Aided Distance Logic Diagrams 222

4.7.1 Aided Distance Send Logic 222

4.7.2 Carrier Aided Schemes Receive Logic 223

4.7.3 Aided Distance Tripping Logic 223

4.7.4 PUR Aided Tripping logic 224

4.7.5 POR Aided Tripping logic 225

4.7.6 Aided Scheme Blocking 1 Tripping logic 226

4.7.7 Aided Scheme Blocking 2 Tripping logic 226

5 Aided DEF Scheme Logic 227

5.1 Aided DEF Introduction 227

5.2 Implementation 227

5.3 Aided DEF Polarization 227

5.3.1 Zero Sequence Polarizing 228

5.3.2 Negative Sequence Polarizing 229

5.4 Aided DEF Setting Guidelines 230

5.5 Aided DEF POR Scheme 231

5.6 Aided DEF Blocking Scheme 232

5.7 Aided DEF Logic Diagrams 233

5.7.1 DEF Directional Signals 233

5.7.2 Aided DEF Send Logic 234

5.7.3 Carrier Aided Schemes Receive Logic 234

5.7.4 Aided DEF Tripping Logic 235

5.7.5 POR Aided Tripping logic 236

5.7.6 Aided Scheme Blocking 1 Tripping logic 237

5.7.7 Aided Scheme Blocking 2 Tripping logic 237

6 Aided Delta Scheme Logic 238

6.1 Aided Delta POR Scheme 238

6.2 Aided Delta Blocking Scheme 239

6.3 Aided Delta Logic Diagrams 241

6.3.1 Aided Delta Send Logic 241

6.3.2 Carrier Aided Schemes Receive Logic 241

6.3.3 Aided Delta Tripping Logic 242

6.3.4 POR Aided Tripping logic 243

6.3.5 Aided Scheme Blocking 1 Tripping logic 244

6.3.6 Aided Scheme Blocking 2 Tripping logic 244

7 Application Notes 245

7.1 Aided Distance PUR Scheme 245

7.2 Aided Distance POR Scheme 245

7.3 Aided Distance Blocking Scheme 245

7.4 Aided DEF POR Scheme 246

7.5 Aided DEF Blocking Scheme 246

7.6 Aided Delta POR Scheme 246

7.7 Aided Delta Blocking Scheme 246

7.8 Teed Feeder Applications 247

7.8.1 POR Schemes for Teed Feeders 248

7.8.2 PUR Schemes for Teed Feeders 248

7.8.3 Blocking Schemes for Teed Feeders 249

Chapter 9 Non-Aided Schemes 251

1 Chapter Overview 253

2 Non-Aided Schemes 254

3 Basic Schemes 255

3.1 Basic Scheme Modes 255

3.2 Basic Scheme Setting 258

Contents P543i/P545i

vi P54x1i-TM-EN-1

4 Trip On Close Schemes 259

4.1 Switch On To Fault (SOTF) 260

4.1.1 Switch Onto Fault Mode 260

4.1.2 SOTF Tripping 261

4.1.3 SOTF Tripping with CNV 261

4.2 Trip On Reclose (TOR) 261

4.2.1 Trip On Reclose Mode 262

4.2.2 TOR Tripping Logic for Appropriate Zones 262

4.2.3 TOR Tripping Logic with CNV 262

4.3 Polarisation during Circuit Engergisation 262

5 Zone1 Extension Scheme 264

6 Loss of Load Scheme 265

Chapter 10 Power Swing Functions 267

1 Chapter Overview 269

2 Introduction to Power Swing Blocking 270

3 Power Swing Blocking 272

3.1 Power Swing Detection 272

3.1.1 Settings-Free Power Swing Detection 272

3.1.2 Slow Power Swing Detection 275

3.2 Detection of a Fault During a Power Swing 276

3.3 Power Swing Blocking Configuration 276

3.4 Power Swing Load Blinding Boundary 277

3.5 Power Swing Blocking Logic 278

3.6 Power Swing Blocking Setting Guidelines 279

3.6.1 Setting the Resistive Limits 280

3.6.2 Setting the Reactive Limits 280

3.6.3 PSB Timer Setting Guidelines 281

4 Out of Step Protection 283

4.1 Out of Step Detection 283

4.2 Out of Step Protection Operataing Principle 284

4.3 Out of Step Logic Diagram 285

4.4 OST Application Notes 285

4.4.1 Setting the OST Mode 285

Chapter 11 Autoreclose 293

1 Chapter Overview 295

2 Introduction to Autoreclose 296

3 Autoreclose Implementation 297

3.1 Autoreclose Logic Inputs from External Sources 298

3.1.1 Circuit Breaker Healthy Input 298

3.1.2 Inhibit Autoreclose Input 298

3.1.3 Block Autoreclose Input 298

3.1.4 Reset Lockout Input 299

3.1.5 Pole Discrepancy Input 299

3.1.6 External Trip Indication 299

3.2 Autoreclose Logic Inputs 299

3.2.1 Trip Initiation Signals 299

3.2.2 Circuit Breaker Status Inputs 299

3.2.3 System Check Signals 299

3.3 Autoreclose Logic Outputs 299

3.4 Autoreclose Operating Sequence 300

3.4.1 AR Timing Sequence - Transient Fault 300

3.4.2 AR Timing Sequence - Evolving/Permanent Fault 300

3.4.3 AR Timing Sequence - Evolving/Permanent Fault Single-phase 301

4 Autoreclose System Map 302

P543i/P545i Contents

P54x1i-TM-EN-1 vii

4.1 Autoreclose System Map Diagrams 304

4.2 Autoreclose Internal Signals 309

4.3 Autoreclose DDB Signals 311

5 Logic Modules 317

5.1 Circuit Breaker Status Monitor 317

5.1.1 CB State Monitor Logic diagram 318

5.2 Circuit Breaker Open Logic 319

5.2.1 Circuit Breaker Open Logic Diagram 319

5.3 Circuit Breaker in Service Logic 319

5.3.1 Circuit Breaker in Service Logic Diagram 319

5.3.2 Autoreclose OK Logic Diagram 320

5.4 Autoreclose Enable 320

5.4.1 Autoreclose Enable Logic Diagram 320

5.5 Autoreclose Modes 320

5.5.1 Single-Phase and Three-Phase Autoreclose 321

5.5.2 Autoreclose Modes Enable Logic Diagram 322

5.6 AR Force Three-Phase Trip Logic 322

5.6.1 AR Force Three-Phase Trip Logic Diagram 322

5.7 Autoreclose Initiation Logic 322

5.7.1 Autoreclose Initiation Logic Diagram 324

5.7.2 Autoreclose Trip Test Logic Diagram 324

5.7.3 AR External Trip Initiation Logic Diagram 325

5.7.4 Protection Reoperation and Evolving Fault Logic Diagram 326

5.7.5 Fault Memory Logic Diagram 326

5.8 Autoreclose In Progress 326

5.8.1 Autoreclose In Progress Logic Diagram 327

5.9 Sequence Counter 327

5.9.1 Autoreclose Sequence Counter Logic Diagram 328

5.10 Autoreclose Cycle Selection 328

5.10.1 Single-Phase Autoreclose Cycle Selection Logic Diagram 328

5.10.2 3-phase Autoreclose Cycle Selection 329

5.11 Dead Time Control 329

5.11.1 Dead Time Start Enable Logic Diagram 330

5.11.2 1-phase Dead Time Logic Diagram 331

5.11.3 3-phase Dead Time Logic Diagram 332

5.12 Circuit Breaker Autoclose 332

5.12.1 Circuit Breaker Autoclose Logic Diagram 333

5.13 Reclaim Time 333

5.13.1 Prepare Reclaim Initiation Logic Diagram 334

5.13.2 Reclaim Time Logic Diagram 334

5.13.3 Succesful Autoreclose Signals Logic Diagram 335

5.13.4 Autoreclose Reset Successful Indication Logic Diagram 335

5.14 CB Healthy and System Check Timers 335

5.14.1 CB Healthy and System Check Timers Logic Diagram 336

5.15 Autoreclose Shot Counters 336

5.15.1 Autoreclose Shot Counters Logic Diagram 337

5.16 Circuit Breaker Control 338

5.16.1 CB Control Logic Diagram 338

5.17 Circuit Breaker Trip Time Monitoring 339

5.17.1 CB Trip Time Monitoring Logic Diagram 339

5.18 Autoreclose Lockout 339

5.18.1 CB Lockout Logic Diagram 340

5.19 Reset Circuit Breaker Lockout 341

5.19.1 Reset CB Lockout Logic Diagram 341

5.20 Pole Discrepancy 342

5.20.1 Pole Discrepancy Logic Diagram 342

5.21 Circuit Breaker Trip Conversion 342

5.21.1 CB Trip Conversion Logic Diagram 343

Contents P543i/P545i

viii P54x1i-TM-EN-1

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