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Camera Link Area-scan Camera Interface using the FPGA5

v2.2 R.Williams 28-04-05

The HERON-FPGA and HERON-IO families are ranges of HERON modules with FPGAs, often

combined with some interface capability. The HERON-FPGA family in particular provides an FPGA

along with a large number of signals routed to general-purpose connectors. These modules are suitable for

connecting to digital cameras, where the control of the camera and image capture can be performed by the

FPGA fitted to the module.

For the development of the FPGA function, HUNT ENGINEERING provides a Hardware Interface

Layer written in VHDL. This layer allows developers to focus on the application-specific parts of the

system. All of the module hardware should be accessed using parts from the library.

Through the Camera Link Area-scan Camera example HUNT ENGINEERING provides a structured

starting point for the development of an area-scan camera interface. The example includes several

components suitable for processing a stream of camera data. It is intended to be a generic tutorial, so does

not address any camera specific issues.

History

Rev 1.0 Adapted from the examples for HERON-FPGA3 and HERON-FPGA4

Rev 2.1 Updated high frequency de-serializer

Rev 2.2 Removed reference to specific ISE versions

Concepts

FPGA devices are programmable hardware, which can be configured to meet the needs of your system.

As with a microprocessor, the function of the FPGA is controlled entirely by the program – and by the

peripherals the FPGA is connected to.

A HERON module has access to FIFOs for communicating with other modules in the system – there

may be up to 6 input FIFOs and 6 output FIFOs. It may have additional interfaces, such as ADCs, or

level-shifting buffers, allowing it to interface to the real world.

The HERON-FPGA family use Xilinx re-configurable logic devices. These can be programmed at low

level, but can also be programmed using high level blocks, such as FIR filters, FFT transforms and so

on. This process is covered in a separate paper.

The Camera Link Area-scan Example

Every HERON-FPGA module is provided with a Hardware Interface Layer that makes it simple for a

user’s FPGA design to access the hardware. Some of the HERON-FPGA modules also have a Camera

Link area-scan camera interface example entitled “CamLink_Cam”. For the rest of this document we

will discuss the Camera Link area-scan camera example provided for the Virtex-II version of the

HERON-FPGA5.

Camera Link is a communication interface that was specifically developed by camera and frame-grabber

manufacturers for use with vision applications. Camera Link works in one of three different

configurations, Base, Medium and Full. The Camera Link example has been developed specifically for

the Base Configuration only. Using this configuration however, it is possible to support cameras from

8-bit pixel resolutions up to 24-bit RGB.

Please note, in order to correctly interface to Camera Link, the FPGA must be able to connect to

LVDS signals. The Virtex-II FPGA IO standards include LVDS support, while the Spartan-II FPGA

IO standards do not. As a result Spartan-II versions of HERON-FPGA modules cannot be used with

the Camera Link example. You can refer to the later sections on ‘Signal Voltage Levels’ for more

information on the requirements of connecting to LVDS.

The “CamLink_Cam” example is supplied as a project for ISE. It contains the top-level design, and

user constraints that define the pinning of the FPGA and timing of the clocks.

The code for the camera interface is implemented in the User Application source file, user_ap1.vhd,

and the files below that. The part of the design tree that includes the files hsb1.vhd and below contains

a set of registers that are programmed over the HSB message interface in order to control camera

interface operation. The HSB interface also provides a mechanism for transmitting and receiving RS-

232 messages between the Camera Link camera and the FPGA camera interface. The part of the design

tree that includes the file clink.vhd and below contains the Camera Link interface. The file camera.vhd

contains generic camera processing functions. All of these files can be modified to make your own

camera interface.

Although the FPGA can be used to capture and process image data without the need for a DSP, the

standard IP outputs full rate image data. This cannot be sent to a Host PC without providing a buffer

that takes care of the “burst” nature of PCI transactions. So for this example we actually capture images

into the memory of a DSP module, then use the DSP to format that into the Windows ‘.bmp’ format

and write it to the hard drive of the host PC using Server/Loader functions.

So in addition to the FPGA example, there is a software example that can be run on a DSP. This

program is provided as a set of two C source files and three header files. The program performs four

tasks. The first task is to set up the camera interface over the HSB interface. The second task is to send

and receive a series of RS-232 messages between the FPGA and camera. Thirdly an image is captured

by the FPGA module, transmitted through a HERON-FIFO and received on the DSP. Finally a series

of bitmap creation functions are called to create a Bitmap file (image.bmp) from the captured image.

The created file can then be viewed by host system imaging software.

This tutorial assumes that the version of ISE design tool you are using is the same as the version of the

camera-link example. There are application notes on the HUNT ENGINEERING CD that describe

how to re-use CD example projects with different versions of ISE if this is necessary. In addition, if

you are using a different synthesis environment to ISE there is an application note ‘Using VHDL tools

other tan ISE’ that you can refer to.

What the Bit-stream Does

The Camera Link Area-scan Camera example provided on the HUNT ENGINEERING CD includes

bit-streams that can be loaded directly onto the Virtex-II, HERON-FPGA5 module. These bit-streams

implement a generic area-scan camera interface, with automatic frame-size and region of interest

detection and programmable region of interest for capture, and frame capture control.

The bit-streams are provided for connecting to a camera that operates using Camera Link. There are

two versions of the bit-stream. One bitstream for cameras operating at 24MHz and below and another

bitstream for cameras working at 25MHz or above.

The VHDL provided in the ‘CamLink_Cam’ example includes source code for two different frequency

Camera Link de-serializers. Each de-serializer design works with a different range of camera pixel clock

frequency. The appropriate frequency range de-serializer must be used based on the pixel clock

frequency of the camera you are using.

For the cameras with pixel clocks of 24MHz or below, the bitstream ending ‘_lf’ must be used. This

bitstream has been built with the Low Frequency Camera Link de-serializer. For the cameras with pixel

clock of 25MHz and above the bitstream ending ‘_hf’ must be used. This bitstream has been built with

the High Frequency Camera Link de-serializer.

For the examples that follow, one of the standard bit-streams supplied on the CD will be downloaded

to your module, depending on your module type. When using one of these standard bit-streams, it will

be necessary to understand what that bit-stream is doing.

Functional Block Diagram

Camera Link

Area-scan Signal

Interface

Capture

Region of

Interest

Frame

Control

Output Packing

and

Synchronisation

511x32

CoreGen

FIFO

HERON FIFO

Write Interface

HERON

Interface

HSB

Message

Interface

Area-scan

Camera

Conn.A

Conn.B

RS-232

Interface

Automatic Region of

Interest Detection

Camera Inputs

The Camera Link interface transmits camera control and data signals using the LVDS signalling

standard. In order to interface to LVDS signals the correct input and output buffer components must

be used in the FPGA design. This is done inside the file ‘top.vhd’. The module expects as inputs one

LVDS camera clock and four LVDS camera data lines. The module drives as outputs four LVDS

camera control signals. In addition to these signals, the module receives one RS232 input from the

camera and transmits one RS232 output to the camera.

The example bit-streams require the camera signals to be provided on Connector A and Connector B

of the HERON-FPGA5. The connections that are required are shown in the table below.

Connector A/B Camera Link Signal

CONN_A0 X0−

CONN_A1 X0+

CONN_A2 X1−

CONN_A3 X1+

CONN_A4 X2−

CONN_A5 X2+

CONN_A6 Xclk−

CONN_A7 Xclk+

CONN_A8 X3−

CONN_A9 X3+

CONN_B0 SerTC−

CONN_B1 SerTc+

CONN_B2 SerTFG−

CONN_B3 SerTFG+

CONN_B4 CC1−

CONN_B5 CC1+

CONN_B6 CC2−

CONN_B7 CC2+

CONN_B8 CC3−

CONN_B9 CC3+

CONN_B10 CC4−

CONN_B11 CC4+

Signal Voltage Levels

The Camera Link standard uses Low Voltage Differential Signalling (LVDS) for the electrical interface

layer. The LVDS signalling standard is as the name suggests, differential. Therefore, one LVDS

connection will involve a positive signal and a negative signal complement. In order to correctly

connect to LVDS a Xilinx FPGA must be used that supports the LVDS standard.

HERON-FPGA modules are available with either Spartan-II or Virtex-II family devices fitted. The

Spartan-II family does not support LVDS signalling however, while the Virtex-II does. As a

consequence of this, only Virtex-II HERON-FPGA modules may be used with the Camera Link

example.

Please note: a 100R series resistor is required for every LVDS input to the Virtex-II FPGA5. This is

required to ensure correct operation. On the FPGA5 this simply requires the fitting of 100R resistor

packs to the reverse side of the board. Please ensure that if you intend to use your HERON-FPGA5

module for implementing a Camera Link interface that you specify the inclusion of the 100R

termination resistor packs for your board when you place the order.

The 100R termination resistor packs are shown on the underside of the board, in the picture above.

They must be fitted to the sites for Connector A of the HERON-FPGA5 such that each Camera Link

signal pair is terminated with 100R between the positive signal and negative signal of the pair.

If when you ordered your HERON-FPGA5 module you did not inform HUNT ENGINEERING

that you would be interfacing to Camera Link cameras, then your board will not have these resistors

fitted. In this case you can either contact HUNT ENGINEERING to discuss having the resistor packs

fitted at the factory, or alternatively you can fit the resistor packs yourself. Please note, although HUNT

ENGINEERING is happy for you to fit the resistors yourself, any damage done to the board in doing

so is not covered under the warranty.

Camera Speeds

The bit-streams supplied by HUNT ENGINEERING have been specified for operation using a

Camera pixel clock frequency of 50MHz or less. There are two versions of the bitstream, one built

using a Low Frequency de-serializer for pixel clocks up to 24MHz and one built using a High

Frequency de-serializer for pixel clocks above 24MHz.

The Camera Link standard uses ‘Channel Link’ for the physical layer. Channel Link consists of a driver

and receiver pair. The driver accepts 28 bits of data and a clock. The data is serialised 7:1 into four data

streams and transmitted with a dedicated clock over 5 LVDS pairs. The receiver accepts the four LVDS

data streams and clock and then recreates the original 28-bit data stream along with the clock.

For those users who have cameras with pixel clocks above 50MHz the User Constraints File for the

project needs to be modified to reflect the particular operating frequency. When this has been done the

bitstream should be regenerated and the place and route report file checked to see those time-

specifications were met.

Automatic Region of Interest Detection

The module AUTO_ROI performs automatic region of interest detection. The module allows the

frame size and active areas of the image to be automatically detected and read over the HSB message

interface.

This information, if used, enables the controlling software to automatically calculate the window for the

capture region of interest process by using values that directly relate to the observed operation of the

camera.

Capture Region of Interest

The module ROI performs a region of interest operation by using a pixel counter and a line counter,

along with a pixel start position, pixel stop position, line start position and line stop position.

The pixel start, pixel stop, line start and line stop values are all programmed over the HSB message

interface. Each of these values can be pre-calculated using the Automatic Region of Interest logic, or

they can be set directly from values supplied by the user.

Frame Control

After the capture region of interest has processed each frame, whether that frame will be output or not

depends on the frame-control component. The continuous mode and N-frames mode are programmed

over the HSB message interface.

Output Packing and Synchronisation

One word, equal to 0 is added at the end of each camera line, apart from the last line of a frame, where

one word with all bits set high (the value FFFFFFFFh) is added to indicate end of frame. In order to

avoid the synchronisation values being present in the data, the bottom byte of camera data is modified

to prevent the values 00h and FFh (a value of 00h will become 01h and a value of FFh will become

FEh).

CoreGen FIFO and HERON FIFO Interface

After the data has been processed by the output packing and synchronisation component, the data is

fed into a Core-generator generated FIFO. The FIFO is a 32-bit word, 511 word deep asynchronous

FIFO built using Block RAM.

When there is any data in the CoreGen FIFO, it is read out and placed in the HERON FIFO Write

Interface. The FIFO number used for output is programmed over the HSB message interface. If the

HERON FIFO becomes full, eventually the CoreGen FIFO will become full and camera data will be

lost. If the CoreGen FIFO becomes full, LED0 will become illuminated.

RS-232 Interface

Camera Link provides two LVDS pairs for serial communication between the ‘frame grabber’ and

camera. The first LVDS pair ‘SerTC+/SerTC−’ is provided for communication To the Camera (TC)

and the second pair ‘SerTFG+/SerTFG−’ is provided for communication To the Frame-Grabber

(TFG).

The RS-232 Interface is connected to HSB. This enables HSB messages to be used to send RS-232

commands to the camera and receive camera status information back. The RS-232 Interface uses a 16-

byte transmit buffer and a 16-byte receive buffer. These buffers allow RS-232 transmission to be

decoupled from HSB.

The Baud rate of the RS-232 connection can be programmed over HSB.

HSB Control Registers

The following table defines the control registers that can be set by sending messages to the FPGA

using HSB.

HSB Address

Byte (decimal) Register Function Description

0 Pixel Start 0 Register LSB of pixel start register for Capture