Intel 8XC251SA Leitfaden

ReleaseDate:December2003

Order Number: 273138-002

The 8xC251Tx may contain design defects or errors known as errata which may cause

the product to deviate from published specifications. Such errata are not covered by

Intel's warranty. Current characterized errata are available on request.

Addendum to the 8xC251SA, 8xC251SB,

8xC251SP, 8xC251SQ, User’s Manual

8xC251TB, 8xC251TQ,

Hardware Description

Information in this document is provided in connection with Intel products. No license, express or implied, by

estoppel or otherwise, to any intellectual property rights is granted by this document. Except as provided in Intel's

Terms and Conditions of Sale for such products, Intel assumes no liability whatsoever, and Intel disclaims any

express or implied warranty, relating to sale and/or use of Intel products including liability or warranties relating to

fitness for a particular purpose, merchantability, or infringement of any patent, copyright or other intellectual

property right. Intel products are not intended for use in medical, life saving, or life sustaining applications. Intel

may make changes to specifications and product descriptions at any time, without notice. Contact your local Intel

sales office or your distributor to obtain the latest specifications and before placing your product order.

Designers must not rely on the absence or characteristics of any features or instructions marked "reserved" or

"undefined." Intel reserves these for future definition and shall have no responsibility whatsoever for conflicts or

incompatibilities arising from future changes to them.

The 8xC251Tx may contain design defects or errors known as errata which may cause the product to deviate

from published specifications. Current characterized errata are available on request.

Copies of documents which have an ordering number and are referenced in this document, or other Intel

literature, may be obtained from:

Intel Corporation

P.O. Box 5937

Denver CO 80217-9808

or call 1-800-548-4725.

Many documents are available for download from Intel’s website at http://www.intel.com.

*Third party brands and names are the property of their respective owners.

273138-002 December2003iii

8xC251Tx Hardware Description

REVISION HISTORY:

Date Revision Description

November 1997 001 Initial release of this document

December 2003 002 Removed references to 8XC251TA, 8XC251TP

ivDecember2003 273138-002

8xC251Tx Hardware Description

273138-002December2003v

8xC251Tx Hardware Description

8xC251TB, 8xC251TQ Hardware Description

Addendum to the 8xC251SA, 8xC251SB, 8xC251SP, 8xC251SQ, User’s Manual

1.0 INTRODUCTION TO THE 8xC251Tx

1.1 Comparing the 8xC251Tx and 8xC251Sx..................................................................... 1

2.0 SIGNAL SUMMARY

3.0 THE SECOND SERIAL I/O PORT

3.1 Overview........................................................................................................................ 7

3.2 Special Function Register Definitions............................................................................ 9

3.2.1 SCON1 .................................................................................................................... 9

3.2.2 SBUF1 ................................................................................................................... 10

3.2.3 SADDR1 ................................................................................................................ 10

3.2.4 SADEN1 ................................................................................................................ 10

3.2.5 BGCON .................................................................................................................. 10

3.2.6 IE1 ......................................................................................................................... 11

3.2.7 IPH1 ....................................................................................................................... 11

3.2.8 IPL1 ....................................................................................................................... 11

4.0 EXTENDED DATA FLOAT TIMING

4.1 Summary of the Extended Data Float Timing Changes .............................................. 12

FIGURES

Figure 1 8xC251Tx Block Diagram .....................................................................................1

TABLES

Table 1. 8xC251Tx Signal Summary ................................................................................. 2

Table 2. 8xC251Tx Signal Descriptions............................................................................. 3

Table 3. Special Function Register (SFR) Map.................................................................. 6

Table 4. Second Serial I/O Port Signals ............................................................................ 7

Table 5. Second Serial I/O Port Special Function Registers.............................................. 8

Table 6. SCON1 Special Function Register Definitions..................................................... 9

Table 7. BGCON Special Function Register Definitions.................................................. 10

Table 8. IE1 Special Function Register Definitions.......................................................... 11

Table 9. IPH1 Special Function Register Definitions ....................................................... 11

Table 10. IPL1 Special Function Register Definitions........................................................ 11

Table 11. Interrupt Priority of Second Serial I/O Port......................................................... 11

Table 12. UCONFIG1 bit definitions for the 8xC251Tx...................................................... 12

Table 13. Summary of the EDF# and WSB#[1:0] Configuration Options........................... 13

8xC251Tx Hardware Description

vi December2003273138-002

8xC251Tx Hardware Description

1.0 INTRODUCTION TO THE 8xC251Tx

This Hardware Description describes the 8xC251TB, 8xC251TQ (referred to collectively as the 8xC251Tx)

embedded microcontroller, which is the newest member of the MCS®251 microcontroller family. The

8xC251Tx is pin and code compatible with the 8xC251Sx but is enhanced with the addition of new features.

This document addresses the differences between the two members of the MCS 251 microcontroller family.

For a detailed description of the MCS 251 microcontroller core and standard peripherals shared by both the

8xC251Sx and 8xC251Tx, please refer to the 8xC251SA, 8xC251SB, 8xC251SP, 8xC251SQ Embedded

Microcontroller User’s Manual (272795).

1.1 Comparing the 8xC251Tx and 8xC251Sx

The differences between the 8xC251Tx and the 8xC251Sx are briefly described here.

•The maximum operating frequency of the 8xC251Tx is 24 Mhz compared to 16 MHz for the 8xC251Sx.

•The 8xC251Tx has two serial I/O ports while the 8xC251Sx has one. The pins for the second serial I/O

port are multiplexed with other functional pins.

•The 8xC251Tx has a new configuration option (Extended Data Float timing) to allow interfacing with

slower memories. This feature is supported by a bit in the configuration byte, UCONFIG1. The corre-

sponding bit in the 8xC251Sx has a different function.

•The 8xC251Tx is offered in with factory programmed ROM while the 8xC251Sx is also offered with

OTPROM/EPROM.

Figure 1. 8xC251Tx Block Diagram

PORT

0-3 EPROM/

ROM RAM

BUS INTERFACE UNIT

Instruction

Sequencer

ALU Register

File Program

Counter

Clock and

Reset Unit

Interrupt

Handler Unit

Peripherals

3 Timers

WDT

PCA

Serial I/O

824

INSTR 24

Memory Data

Memory Address

Data Bus

Data Address

IB Bus

Peripheral Interface Unit

Data Memory Interface

CPU

SRC1, SRC2

DST

RESETP0 (A7-

0/D7-0)

P2 (A15-8)

PSEN

ALE VCC VSS

XTAL1

XTAL2

2nd Serial

I/O

8xC251Tx Hardware Description

2.0 SIGNAL SUMMARY

Table 1. 8xC251Tx Signal Summary

Address & Data Input/Output

Name PLCC DIP Name PLCC DIP

AD0/P0.0 43 39 P1.0/T2 2 1

AD1/P0.1 42 38 P1.1/T2EX 3 2

AD2/P0.2 41 37 P1.2/EC/RXD1 4 3

AD3/P0.3 40 36 P1.3/CEX0/TXD1 5 4

AD4/P0.4 39 35 P1.4/CEX1 6 5

AD5/P0.5 38 34 P1.5/CEX2 7 6

AD6/P0.6 37 33 P1.6/CEX3/WAIT# 8 7

AD7/P0.7 36 32 P1.7/CEX4/A17/WCLK 9 8

A8/P2.0 24 21 P3.0/RXD 11 10

A9/P2.1 25 22 P3.1/TXD 13 11

A10/P2.2 26 23 P3.4/T0 16 14

A11/P2.3 27 24 P3.51/T1 17 15

A12/P2.4 28 25

A13/P2.5 29 26 Power & Ground

A14/P2.6 30 27 Name PLCC DIP

A15P2.7 31 28 VCC 44 40

P3.7/RD#/A16 19 17 VCC2 12

P1.7/CEX4/A17/WCLK 9 8 VSS 22 20

VSS1 1

Processor Control VSS2 23,24

Name PLCC DIP

P3.2/INT0# 14 12 Bus Control & Status

P3.3/INT1# 15 13 Name PLCC DIP

EA# 35 31 P3.6/WR# 18 16

RST 10 9P3.7/RD#/A16 19 17

XTAL1 21 18 ALE 33 30

XTAL2 20 19 PSEN# 32 29

NOTE: Pins in this font indicate functions associated with the second serial I/O port.

8xC251Tx Hardware Description

Table 2. 8xC251Tx Signal Descriptions (Sheet 1 of 3)

Signal

Name Type Description Alternate

Function

A17 OAddress Line 17. Output to memory as the 18th external address bit

(A17) in extended bus applications, depending on the values of bits

RD0 and RD1 in configuration byte UCONFIG0 (see Chapter 4,

"Device Configuration," of the 8xC251SA, 8xC251SB, 8xC251SP,

8xC251SQ Embedded Microcontroller User’s Manual (272795). See

also RD# and PSEN#.

P1.7/CEX4/

WCLK

A16 OAddress Line 16. See RD#. P3.7/RD#

A15:8* OAddress Lines. Upper address lines for the external bus. P2.7:0

A7:0 I/O Address/Data Lines. Multiplexed lower address lines and data lines

for external bus. P0/7:0

ALE OAddress Latch Enable. ALE signals the start of an external bus

cycle and indicates that valid address information is available on lines

A15:8 and A7:0. An external latch can use ALE to demultiplex the

address from the address/data bus.

CEX0

CEX1

CEX2

CEX3

CEX4

I/O Programmable Counter Array (PCA) input/output pins. These are

input signals for the PCA capture mode and output signals for the

PCA compare mode and PCA PWM mode.

P1.3/TXD1

P1.4

P1.5

P1.6/WAIT#

P1.7/A17/

WCLK

EA# IExternal Access. Direct program accesses to on-chip or off-chip

code memory. For EA# = 0, all program memory accesses are off

chip. For EA# = 1, all program memory accesses are on-chip if the

address is within the range of the on-chip program memory; other-

wise the access is off-chip. The value of EA# is latched at reset. For

devices without on-chip program memory, EA# must be strapped to

ground.

ECI IPCA External Clock Input. External clock input to the 16 bit PCA

timer. P1.2/RXD1

INT1:0# IExternal Interrupts 0 and 1. These inputs set IE1:0 in the TCON

by the falling edge on the INT1#/INT0#. If bits IT1:0 are clear, bits

IE1:0 are set by a low level on INTO1:0#.

P3.3:2

P0.7:0 I/O Port 0. This is an 8 bit, open drain, bidirectional I/O port. AD7:0

P1.0

P1.1

P1.2

P1.3

P1.4

P1.5

P1.6

P1.7

I/O Port 1. This is an 8 bit, bidirectional I/O port with internal pullups. T2

T2EX

ECI/RXD1

CEX0/TXD1

CEX1

CEX2

CEX3/WAIT#

CEX4/A17/

WCLK

P2.7:0 I/O Port 2. This is an 8 bit, bidirectional I/O port with internal pullups. A15:8

* The descriptions of A15:8/P2.7:0 and AD7:0/P0.7:0 are for non page mode configuration. If configured in

page mode, Port 0 carries the lower address bits (A7:0) and Port 2 carries the upper address bits (A15:8)

and the data (D7:0)

8xC251Tx Hardware Description

P3.0

P3.1

P3.2

P3.3

P3.4

P3.5

P3.6

P3.7

I/O Port 3. This is an 8 bit, bidirectional I/O port with internal pullups RXD

TXD

INT0#

INT1#

WR#

RD#/A16

PSEN# OProgram Store Enable. Read signal output to external memory.

Asserted for the address range specified by the configuration byte

UCONFIG0, bits RD1:0.

RD# ORead. Read signal output to external memory. Asserted for the

address range specified by the configuration byte UCONFIG0, bits

RD1:0.

P3.7/A16

RST IReset. Reset input to the chip. Holding this pin high for 64 oscillator

periods while the oscillator is running resets the device. The port pins

are driven to their reset conditions when a voltage greater than VIH1

is applied, whether or not the oscillator is running. This signal has a

Schmitt trigger input. Connecting the RST pin to VCC through a

capacitor provides power-on reset. Asserting RST when the chip is in

idle mode or powerdown mode returns the chip to normal operation.

RXD I/O Receive Serial Data. RXD send and receives data in serial I/O mode

0 and receives data in serial I/O modes 1, 2 and 3. P3.0

RXD1 I/O Receive Serial Data 1. RXD send and receives data in serial I/O

mode 0 and receives data in serial I/O modes 1, 2 and 3 for the sec-

ond serial I/O port.

P1.2/ECI

T1:0 ITimer 1:0 External Clock Inputs. When Timer 1:0 operates as a

counter, a falling edge on the T1:0 pin increments the count. P3.5:4

T2 I/O Timer 2 Clock Input/Output. For Timer 2 capture mode, this signal

is the external clock input. For the clock-out mode, it is the timer 2

clock input.

P1.0

T2EX ITimer 2 External Input. In Timer 2 capture mode, a falling edge ini-

tiates a capture of Timer 2 registers. In auto-reload mode, a falling

edge causes the Timer 2 registers to be reloaded. In the up-down

counter mode, this signal determines the count direction:

•1=up

•0 = down.

P1.1

TXD OTransmit Serial Data. TXD outputs the shift clock in serial I/O mode

0 and transmits serial data in serial I/O modes 1, 2 and 3. P3.1

TXD1 OTransmit Serial Data 1. TXD outputs the shift clock in serial I/O

mode 0 and transmitsserial data in serial I/Omodes 1,2 and 3 for the

second serial I/O port.

P1.3/CEX0

VCC PWR Supply Voltage. Connect this pin to the +5 supply voltage.

Table 2. 8xC251Tx Signal Descriptions (Sheet 2 of 3)

Signal

Name Type Description Alternate

Function

* The descriptions of A15:8/P2.7:0 and AD7:0/P0.7:0 are for non page mode configuration. If configured in

page mode, Port 0 carries the lower address bits (A7:0) and Port 2 carries the upper address bits (A15:8)

and the data (D7:0)

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