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Intel® Agilex™ Power Management

User Guide

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Contents

1. Intel® Agilex™ Power Management Overview..................................................................3

1.1. Power System Design Phases.................................................................................. 3

1.1.1. Choosing a Power Tree............................................................................... 3

1.1.2. Power Estimation.......................................................................................3

1.1.3. Power Optimization....................................................................................4

1.1.4. Power Generation...................................................................................... 4

1.1.5. Power Distribution..................................................................................... 4

1.1.6. Power Dissipation and Thermal Considerations...............................................4

1.2. Power Supplies......................................................................................................4

2. Intel Agilex Power Basics............................................................................................... 5

2.1. Power Consumption............................................................................................... 5

2.2. Power Estimation Basics......................................................................................... 5

2.3. Early Power Estimator (EPE)....................................................................................6

2.4. Power Analyzer..................................................................................................... 7

3. Intel Agilex Power and I/O State Sequencing.................................................................8

3.1. Overview..............................................................................................................8

3.2. Power-Up Sequence Requirements........................................................................... 8

3.3. Power-On Reset...................................................................................................10

3.3.1. Power Supplies Monitored by the POR Circuitry............................................ 11

4. Intel Agilex Sensor Monitoring System......................................................................... 12

4.1. Voltage Monitoring System....................................................................................12

4.1.1. Voltage Sensor Transfer Function............................................................... 12

4.2. Temperature Monitoring System.............................................................................13

4.2.1. Local Temperature Sensor......................................................................... 13

4.2.2. Remote Temperature Sensing Diode........................................................... 14

4.2.3. Temperature Sensor Channels and Locations............................................... 15

4.3. Intel Agilex Sensors Design Considerations..............................................................15

4.3.1. Intel Agilex Voltage Monitor Design Guidelines............................................. 15

4.3.2. Intel Agilex Temperature Monitor Design Guidelines......................................16

5. Intel Agilex Power Optimization Techniques and Features........................................... 17

5.1. SmartVID Standard Power Devices.........................................................................17

5.1.1. SmartVID Feature Implementation in Intel Agilex Devices............................. 18

5.1.2. SDM Power Manager.................................................................................19

5.1.3. Temperature Compensation.......................................................................23

5.1.4. Intel Agilex Power Management and VID Implementation Guide..................... 24

5.2. DSP and M20K Power Gating................................................................................. 26

5.3. Clock Gating....................................................................................................... 26

5.4. Power Sense Line.................................................................................................27

5.5. Power Optimization Techniques in the Intel Quartus Prime Software............................27

6. Document Revision History for the Intel Agilex Power Management User Guide...........28

Contents

Intel® Agilex™ Power Management User Guide Send Feedback

1. Intel® Agilex™ Power Management Overview

The Intel® Agilex™ device family offers SmartVID standard power devices in all speed

grades. Fixed-voltage devices are also available, but only in –4 speed grade. All

SmartVID standard power devices must be driven by the Power Management BUS

(PMBus™)-compliant voltage regulator, operating either in the PMBus master or PMBus

slave mode.

Intel Agilex devices also offer power-gating feature to the digital signal processing

(DSP) blocks, M20K memory blocks, and clock signals that are not in use for static

power savings. You can enable this feature through the Intel Quartus® Prime software.

This user guide describes the power-optimizing features of the Intel Agilex device

family, and the power-up and power-down sequencing requirements for the Intel

Agilex devices.

1.1. Power System Design Phases

Power system design is done in the following logical phases.

1.1.1. Choosing a Power Tree

A power tree topology is chosen based on the requirements of your device.

The requirements of the power supply may not yet be known, but you can access the

supply voltage and connection requirements from the Intel Agilex Device Family Pin

Connection Guidelines and the power tree selector guides in the Intel Enpirion® Power

Resource Center. Any required power supply sequencing and SmartVID usage will

impact the power tree topology.

Related Information

•Intel Agilex Device Family Pin Connection Guidelines

Provides more information about the supply voltage and connection guidelines

of each pin.

•Intel Enpirion Power Solutions

1.1.2. Power Estimation

The amount of electrical power required by the various device power supplies is

estimated using the Early Power Estimator (EPE) tool and the Power Analyzer tool.

As the design evolves to the final configuration, the quality and type of information

available improve and the estimation becomes more accurate.

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1.1.3. Power Optimization

The device configuration can be optimized to reduce power.

This step involves the Intel Quartus Prime software power optimization wizard, the

SmartVID feature (available in all Intel Agilex devices except for –4F speed grade),

system cooling decisions, and/or dynamic workload management strategies. This

phase may occur several times during the evolution of the system and device design.

1.1.4. Power Generation

Voltage regulator modules (VRMs) are selected based on the power tree and electrical

power estimates. VRM selection is critical to producing high-quality power systems

with the minimum number and cost of bypass elements. Intel Enpirion VRMs are

featured due to their high quality and fast load transient response.

1.1.5. Power Distribution

The power distribution network (PDN) is designed, producing a list of the required

number, value, and quality of bypass capacitors using the PDN tool, power tree, VRMs

electrical power estimations, and board physical geometries.

1.1.6. Power Dissipation and Thermal Considerations

Thermal cooling estimates are used to design the cooling solution. The EPE can be

used to model the effect of different solutions on junction temperature. The effects of

junction temperature on device power consumption and device reliability should be

considered in this phase.

1.2. Power Supplies

For more information about the supported power supplies and the nominal voltages,

refer to the Intel Agilex Device Data Sheet.

Related Information

Intel Agilex Device Data Sheet

Provides more information about the supported power supplies and the nominal

voltages.

1. Intel® Agilex™ Power Management Overview

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Intel® Agilex™ Power Management User Guide Send Feedback

2. Intel Agilex Power Basics

2.1. Power Consumption

The total power consumption of an Intel Agilex device consists of the following

components:

• Static power—the power that the configured device consumes when powered up

but no user clocks are operating, excluding DC bias power of analog blocks, such

as I/O and transceiver analog circuitry.

• Dynamic power—the additional power consumption of the device due to signal

activity or toggling. Dynamic power is dependent on the operating frequency of

your design, applied voltage, and load capacitance, which depends on design

connectivity.

• Standby power—the component of active power that is independent of signal

activity or toggling. Standby power includes, but is not limited to, I/O and

transceiver DC bias power.

Intel Agilex devices minimize static and dynamic power using advanced process

optimizations. These optimizations allow Intel Agilex designs to meet specific

performance requirements with the lowest possible power.

2.2. Power Estimation Basics

The Intel power analysis features, including Early Power Estimator (EPE) and the Intel

Quartus Prime software Power Analyzer, give you the ability to estimate power

consumption from early design concept through design implementation, as shown in

the following figure.

As you provide more details about your design characteristics, estimation accuracy is

improved. Intel recommends that you switch from the EPE to the Power Analyzer in

the Intel Quartus Prime software once your design is available. The Power Analyzer

produces more accurate results because it has more detailed information about your

design, including routing and configuration information about all the resources in your

design.

The accuracy of the power model is determined on a per-power-rail basis for both the

Power Analyzer and the EPE. For most designs, the Power Analyzer and the EPE have

the following accuracies, with final power models:

• Power Analyzer—within 10% of silicon for the majority of power rails and the

highest power rails, assuming accurate inputs and toggle rates.

• EPE—within 15% of silicon for the majority of power rails and the highest power

rails, assuming accurate inputs and toggle rates. Recommended margins are

shown in the Report tab.