Intel Arria 10 series Bedienungsanleitung

Intel® FPGA HDMI Design Example

User Guide for Intel® Arria 10

Devices

Updated for Intel® Quartus® Prime Design Suite: 17.1

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UG-20077 | 2017.11.06

Related Links

Intel FPGA HDMI IP Core User Guide

1.1 Directory Structure

The directories contain the generated files for the Intel FPGA HDMI design example.

UG-20077 | 2017.11.06

and Stratix words and logos are trademarks of Intel Corporation or its subsidiaries in the U.S. and/or other

countries. Intel warrants performance of its FPGA and semiconductor products to current specifications in

accordance with Intel's standard warranty, but reserves the right to make changes to any products and services

at any time without notice. Intel assumes no responsibility or liability arising out of the application or use of any

information, product, or service described herein except as expressly agreed to in writing by Intel. Intel

customers are advised to obtain the latest version of device specifications before relying on any published

information and before placing orders for products or services.

*Other names and brands may be claimed as the property of others.

ISO

9001:2008

Registered

Figure 2. Directory Structure for the Design Example

* Standard = Intel Quartus Prime Standard Edition

Pro = Intel Quartus Prime Pro Edition

quartus

incremental_db (Standard)

db (Standard)/qdb (Pro)

output_files

tmp-clearbox (Pro)

a10_hdmi_demo.qpf

a10_hdmi_demo.qsf

rtl

nios.qsys

gxb

hdmi_rx

hdmi_tx

i2c_master

i2c_slave

reconfig_mgmt

sdc

hdr

common (Pro)

pll

rxtx_link.v

a10_hdmi2_demo.v

a10_reconfig_arbiter.sv

clock_control.qsys/clock_control.ip

clock_crosser.v

script

build_ip.tcl

build_sw.sh

runall.tcl

tx_control_bsp

tx_control

tx_control_src

software

simulation

aldec

cadence

mentor

synopsys

hdmi_rx

hdmi_tx

autotest_crc.v

bitec_hdmi_audio_gen.v

bitec_hdmi_tb.sv

tpg.v

Table 1. Generated RTL Files

Folders Files

gxb • /gxb_rx.qsys (Intel Quartus Prime Standard Edition)

•/gxb_rx.ip (Intel Quartus Prime Pro Edition)

•/gxb_rx_reset.qsys (Intel Quartus Prime Standard Edition)

•/gxb_rx_reset.ip (Intel Quartus Prime Pro Edition)

•/gxb_tx.qsys (Intel Quartus Prime Standard Edition)

•/gxb_tx.ip (Intel Quartus Prime Pro Edition)

•/gxb_tx_fpll.qsys (Intel Quartus Prime Standard Edition)

•/gxb_tx_fpll.ip (Intel Quartus Prime Pro Edition)

•/gxb_tx_reset.qsys (Intel Quartus Prime Standard Edition)

•/gxb_tx_reset.ip (Intel Quartus Prime Pro Edition)

hdmi_rx • /hdmi_rx.qsys (Intel Quartus Prime Standard Edition)

•/hdmi_rx.ip (Intel Quartus Prime Pro Edition)

/hdmi_rx_top.v

/mr_clock_sync.v

/mr_hdmi_rx_core_top.v

/mr_rx_oversample.v

/symbol_aligner.v

hdmi_tx • /hdmi_tx.qsys (Intel Quartus Prime Standard Edition)

•/hdmi_tx.ip (Intel Quartus Prime Pro Edition)

/hdmi_tx_top.v

continued...

1 Intel® FPGA HDMI Design Example Quick Start Guide for Intel® Arria® 10 Devices

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Intel® FPGA HDMI Design Example User Guide for Intel® Arria 10 Devices

Folders Files

/mr_ce.v

/mr_hdmi_tx_core_top.v

/mr_tx_oversample.v

i2c_master /i2c_master_bit_ctrl.v

/i2c_master_byte_ctrl.v

/i2c_master_defines.v

/i2c_master_top.v

/oc_i2c_master.v

/oc_i2c_master_hw.tcl

/timescale.v

i2c_slave • /edid_ram.qsys (Intel Quartus Prime Standard Edition)

•/edid_ram.ip (Intel Quartus Prime Pro Edition)

/I2Cslave.v

•/output_buf_i2c.qsys (Intel Quartus Prime Standard Edition)

•/output_buf_i2c.ip (Intel Quartus Prime Pro Edition)

/Panasonic.hex

/i2c_avl_mst_intf_gen.v

/i2c_clk_cnt.v

/i2c_condt_det.v

/i2c_databuffer.v

/i2c_rxshifter.v

/i2c_slvfsm.v

/i2c_spksupp.v

/i2c_txout.v

/i2c_txshifter.v

/i2cslave_to_avlmm_bridge.v

pll • /pll_hdmi.qsys (Intel Quartus Prime Standard Edition)

•/pll_hdmi.ip (Intel Quartus Prime Pro Edition)

•/pll_hdmi_reconfig.qsys (Intel Quartus Prime Standard Edition)

•/pll_hdmi_reconfig.ip (Intel Quartus Prime Pro Edition)

common /reset_controller (Intel Quartus Prime Pro Edition)

hdr /altera_hdmi_aux_hdr.v

/altera_hdmi_aux_snk.v

/altera_hdmi_aux_src.v

/altera_hdmi_hdr_infoframe.v

/avalon_st_mutiplexer.v

continued...

1 Intel® FPGA HDMI Design Example Quick Start Guide for Intel® Arria® 10 Devices

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Intel® FPGA HDMI Design Example User Guide for Intel® Arria 10 Devices

Folders Files

reconfig_mgmt /mr_compare_pll.v

/mr_compare_rx.v

/mr_rate_detect.v

/mr_reconfig_master_pll.v

/mr_reconfig_master_rx.v

/mr_reconfig_mgmt.v

/mr_rom_pll_dprioaddr.v

/mr_rom_pll_valuemask_8bpc.v

/mr_rom_pll_valuemask_10bpc.v

/mr_rom_pll_valuemask_12bpc.v

/mr_rom_pll_valuemask_16bpc.v

/mr_rom_rx_dprioaddr_bitmask.v

/mr_rom_rx_valuemask.v

/mr_state_machine.v

sdc /a10_hdmi2.sdc

/mr.sdc

/jtag.sdc

Table 2. Generated Simulation Files

Folders Files

aldec /aldec.do

/rivierapro_setup.tcl

cadence /cds.lib

/hdl.var

/ncsim.sh

/ncsim_setup.sh

<cds_libs folder>

mentor /mentor.do

/msim_setup.tcl

synopsys /vcs/filelist.f

/vcs/vcs_setup.sh

/vcs/vcs_sim.sh

/vcsmx/vcsmx_setup.sh

/vcsmx/vcsmx_sim.sh

/vcsmx/synopsys_sim_setup

continued...

1 Intel® FPGA HDMI Design Example Quick Start Guide for Intel® Arria® 10 Devices

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Intel® FPGA HDMI Design Example User Guide for Intel® Arria 10 Devices

Folders Files

hdmi_rx • /hdmi_rx.qsys (Intel Quartus Prime Standard Edition)

•/hdmi_rx.ip (Intel Quartus Prime Pro Edition)

/hdmi_rx.sopcinfo (Intel Quartus Prime Standard Edition)

hdmi_tx • /hdmi_tx.qsys (Intel Quartus Prime Standard Edition)

•/hdmi_tx.ip (Intel Quartus Prime Pro Edition)

/hdmi_tx.sopcinfo (Intel Quartus Prime Standard Edition)

Table 3. Generated Software Files

Folders Files

tx_control_src

Note: The tx_control folder will also

contain duplicates of these files.

/i2c.c

/i2c.h

/main.c

/xcvr_gpll_rcfg.c

/xcvr_gpll_rcfg.h

1.2 Hardware and Software Requirements

Intel uses the following hardware and software to test the design example.

Hardware

• Intel Arria 10 GX FPGA Development Kit

• HDMI Source (Graphics Processor Unit (GPU))

• HDMI Sink (Monitor)

• Bitec HDMI 2.0 FMC daughter card (Revision 4.0)

• HDMI cables

Software

• Intel Quartus Prime version 17.1 (for hardware testing)

• ModelSim* - Intel FPGA Edition, ModelSim - Intel FPGA Edition Starter Edition,

NCSim (Verilog HDL only), Riviera-Pro, or VCS/VCS-MX simulator

1.3 Generating the Design

Use the Intel FPGA HDMI parameter editor in the Intel Quartus Prime software to

generate the design examples.

Figure 3. Generating the Design Flow

Start Parameter

Editor

Specify IP Variation

and Select Device

Select

Design Parameters

Initiate

Design Generation

Specify

Example Design

1 Intel® FPGA HDMI Design Example Quick Start Guide for Intel® Arria® 10 Devices

UG-20077 | 2017.11.06

Intel® FPGA HDMI Design Example User Guide for Intel® Arria 10 Devices

1. Create a project targeting Intel Arria 10 device family and select the desired

device.

2. In the IP Catalog, locate and double-click Intel FPGA HDMI IP Core. The New

IP Variant or New IP Variation window appears.

3. Specify a top-level name for your custom IP variation. The parameter editor saves

the IP variation settings in a file named <your_ip>.ip or <your_ip>.qsys.

4. Click OK. The parameter editor appears.

5. On the IP tab, configure the desired parameters for both TX and RX.

6. On the Design Example tab, select Arria 10 HDMI RX-TX Retransmit.

7. Select Simulation to generate the testbench, and select Synthesis to generate

the hardware design example.

You must select at least one of these options to generate the design example files.

If you select both, the generation time is longer.

8. For Generate File Format, select Verilog or VHDL.

9. For Target Development Kit, select Intel Arria 10 GX FPGA Development

Kit. If you select a development kit, then the target device (selected in step 4)

changes to match the device on target board. For Intel Arria 10 GX FPGA

Development Kit, the default device is 10AX115S2F4I1SG.

10. Click Generate Example Design.

1.4 Simulating the Design

The HDMI testbench simulates a serial loopback design from a TX instance to an RX

instance. Internal video pattern generator and audio pattern generator modules drive

the HDMI TX instance and the serial output from the TX instance connects to the RX

instance in the testbench.

Figure 4. Design Simulation Flow

Change to

Related Links

Intel Arria 10 FPGA Development Kit User Guide

1 Intel® FPGA HDMI Design Example Quick Start Guide for Intel® Arria® 10 Devices

UG-20077 | 2017.11.06

Intel® FPGA HDMI Design Example User Guide for Intel® Arria 10 Devices

1.6 Design Limitation

You may encounter timing violation on the maximum skew constraints required for the

designs that use TX PMA and PCS bonding.

Choose the transceiver channels farther away from the Hard IP (HIP) block to meet

the maximum skew tolerance constraints requirement.

1.7 Intel FPGA HDMI Design Example Parameters

Table 5. Intel FPGA HDMI Design Example Parameters for Intel Arria 10 Devices

These options are available for Intel Arria 10 devices only.

Parameter Value Description

Available Design Example

Select Design Arria 10 HDMI RX-TX

Retransmit

Select the design example to be generated. The generated design

example has preconfigured parameter settings. It does not follow user

settings.

Design Example Files

Simulation On, Off Turn on this option to generate the necessary files for the simulation

testbench.

Synthesis On, Off Turn on this option to generate the necessary files for Intel Quartus

Prime compilation and hardware demonstration.

Generated HDL Format

Generate File Format Verilog, VHDL Select your preferred HDL format for the generated design example

fileset.

Note: This option only determines the format for the generated top

level IP files. All other files (e.g. example testbenches and top

level files for hardware demonstration) are in Verilog HDL format.

Target Development Kit

Select Board No Development Kit,

Arria 10 GX FPGA

Development Kit,

Custom Development

Kit

Select the board for the targeted design example.

• No Development Kit: This option excludes all hardware aspects for

the design example. The IP core sets all pin assignments to virtual

pins.

• Arria 10 GX FPGA Development Kit: This option automatically selects

the project's target device to match the device on this development

kit. You may change the target device using the Change Target

Device parameter if your board revision has a different device

variant. The IP core sets all pin assignments according to the

development kit.

• Custom Development Kit: This option allows the design example to

be tested on a third party development kit with an Intel FPGA. You

may need to set the pin assignments on your own.

Target Device

Change Target Device On, Off Turn on this option and select the preferred device variant for the

development kit.

1 Intel® FPGA HDMI Design Example Quick Start Guide for Intel® Arria® 10 Devices

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Intel® FPGA HDMI Design Example User Guide for Intel® Arria 10 Devices

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