Intel CH-486-33A Bedienungsanleitung

CH-486-33A

User’s Manual

1st Edition, June 1991

The information contained in this manual is

subject to change without notice

_.___

____________

IBM

PC/XT/AT/PS-2

are registered trademarks of

International Business Machines Corporation.

AMI

is a trademark of American Megatrends, inc.

486 is a trademark of Intel Corporation.

Other brand and product name or trademarks

and/or registered trademarks of respective companies.

Table Of Contents

1. Introduction

Hardware Description

System Description

Connector and Jumper Settings

DRAM Bank Configuration

SRAM Configuration

BIOS Setup

3-6

’

BIOS Overview

Standard CMOS Setup

Advanced CMOS Setup

Advanced

Chipset

Setup

Auto Configuration with BIOS

Defaults.

Auto Configuration with Power-On

Defaults

Write To CMOS and Exit

Not Write To CMOS and Exit

htroduction

The

CH-486.33A

is a three-chip solution offering optional

performance for high-end

486.based

AT systems. The

CH-486.33A

is designed for INTEL

80486DX

running 33 MHz

or INTEL

80486SX

running for

20/25MHz

combines three

major functions:

The

82C493

System Controller

(sysc)

The

82C392

Data Buffer Contrdler (DBC)

The

82C206

Integrated Peripheral Controller (IPC)

l-l. CH-486-33A Mainboard Specification

33 MHz INTEL 80486 DX CPU OR

20125

MHz INTEL

80486

CPU

ISA architecture

Copy-Back Direct-Mapped Cache with size of 64KB

or 256 KB selectable

Up to 32 MB of local high-speed page-mode DRAM

memory space

DRAM TYPE support 256K/i

M/4MB

Control of two non-cacheable regions

Shadow

RAM support

Optional Cacheable of shadow video BIOS

Turbo/slow speed selectable for hardware and

software controller

Introduction

1-1

WEITEK 4167 coprocessor socket on board

On board rechargeable battery back-up for CMOS

configuration and real-time dock

Optimized for

OS/2,

window/386, window 3.0, XENIX,

UNIX software operation

Baby AT size, with XT/AT mounting

hole

l-2

lntroductlon

2. Hardware Description

2-l

System Description

80486

Microprocessor

The 80486 is a high performance

32.bit

microprocessor with

on-chip memory management, floating point and cache

memory units. It is binary compatible with members of the 86

architectural family. The 486 CPU contains all the features of

the 386 CPU with enhancements to increase performance.

On-chip Floating Point Control Unit

The operation of the 486 microprocessor’s on-chip floating

point control unit is exactly the same as the 387 math

coprocessor. Software written for the 387 math coprocessor will

run on the on-chip floating point unit without any

modification. It occupies

I/O

address range of

8OOOOOFOH-SOOOOOFFH

and operates in parallel with the

arithmetic and logic unit and provides arithmetic instructions

for a variety of numeric data types.

On-chip Cache Memory

The

8KB

on-chip cache is a 4-way set associative write-through

code and data cache memory. Individual pages can be

designated as cacheable or non-cacheable by software or

hardware. The cache can also be enabled and disabled by

software or hardware.

Hardware Description

4167 Floating-point Coprocessor

The WEITEK 4167 is a high-performance single-chip

floating-point coprocessor for 80486 microprocessor. It is

upwardly binary compatible with the WEITEK 3167

coprocessor.

The 4167 coprocessor is

memory-mapped peripheral

that

communicates with the

80486

over the

same

address

bus

tklt

connects the main memory to CPU. The

coprocessor

will

respond to memory addresses

COOOOOOO1:

through

CIFFFFFFH. Writing to this ;ddrcss space will

cause

the

107

to execute this

fractions

coprocessor to drive the and reading from it will cause the

data

bus.

2-2 Connector and Jumper Settings

This chapter describes the

CH-486.33A

main

bo;rrd’s

jumpers

and connectors

The system layout are shown on the next

purge.

Hardware Description

JPll

WEITEK

82c4w

4167

DRAMBank

J23

324

SW2

JP12

Hardware Description

2-3

SW1

Hardware Reset switch Connector

sw2:

Hardware Turbo Switch Connector

Keyboard Connector

JlO: External Battery Connector

Jll

J12: Power Connector

J23:

Keylock and Power LED Connector

J24:

Speaker Connector

JP12:

Turbo LED Connector

2-4 Hardware Description

Jumper

Description

Setting

JPl

Monitor Type Selectable

Monochrome

JP2

JP4

CMOS power

1-2

Clear CMOS RAM

2-3

Backup CMOS RAM

JPS

CPU selectable

[Always

2-3 Short

1-2

487SX

(2-3

4860X

13Upen:4BSX

JP6

JP7

CPU selectable

[Short

486

OX,

487SX

Open

486 SX

JP8

Cache

$i28 Sdetctabl8

_-.--_-.-.-

Short

256K

@pen

64K

Jp9

JPlO

JPll

Cache size selectable

Short

256K

IOpen

64K

[Always Open

Short

256K

IOpen

64K

NOTE

TItose

enclosed in box

ate

Mainboard

Default

2. This

Mainbmud

mly supput Intel C

Iater

stepping

cfpracesscx.

Hardware Description 2-5

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