Intel MAX 10 FPGA Bedienungsanleitung

MAX 10 FPGA Device Overview

M10-OVERVIEW

2017.02.21

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Contents

1 MAX® 10 FPGA Device Overview...................................................................................... 3

1.1 Key Advantages of MAX 10 Devices...........................................................................3

1.2 Summary of MAX 10 Device Features ...................................................................... 4

1.3 MAX 10 Device Ordering Information.........................................................................5

1.3.1 MAX 10 Device Feature Options.................................................................... 6

1.4 MAX 10 Device Maximum Resources ........................................................................6

1.5 MAX 10 Devices I/O Resources Per Package ............................................................. 7

1.6 MAX 10 Vertical Migration Support............................................................................ 7

1.6.1 MAX 10 I/O Vertical Migration Support...........................................................8

1.6.2 MAX 10 ADC Vertical Migration Support......................................................... 8

1.7 Logic Elements and Logic Array Blocks.......................................................................9

1.8 Analog-to-Digital Converter......................................................................................9

1.9 User Flash Memory............................................................................................... 10

1.10 Embedded Multipliers and Digital Signal Processing Support......................................10

1.11 Embedded Memory Blocks....................................................................................11

1.12 Clocking and PLL.................................................................................................11

1.13 FPGA General Purpose I/O....................................................................................12

1.14 External Memory Interface................................................................................... 12

1.15 Configuration......................................................................................................13

1.16 Power Management............................................................................................. 13

1.17 Document Revision History for MAX 10 FPGA Device Overview.................................. 13

Contents

MAX 10 FPGA Device Overview

1 MAX® 10 FPGA Device Overview

MAX® 10 devices are single-chip, non-volatile low-cost programmable logic devices

(PLDs) to integrate the optimal set of system components.

The highlights of the MAX 10 devices include:

• Internally stored dual configuration flash

• User flash memory

• Instant on support

• Integrated analog-to-digital converters (ADCs)

• Single-chip Nios II soft core processor support

MAX 10 devices are the ideal solution for system management, I/O expansion,

communication control planes, industrial, automotive, and consumer applications.

Related Links

MAX 10 FPGA Device Datasheet

1.1 Key Advantages of MAX 10 Devices

Table 1. Key Advantages of MAX 10 Devices

Advantage Supporting Feature

Simple and fast configuration Secure on-die flash memory enables device configuration in less than 10 ms

Flexibility and integration • Single device integrating PLD logic, RAM, flash memory, digital signal

processing (DSP), ADC, phase-locked loop (PLL), and I/Os

• Small packages available from 3 mm × 3 mm

Low power • Sleep mode—significant standby power reduction and resumption in less than

1 ms

• Longer battery life—resumption from full power-off in less than 10 ms

20-year-estimated life cycle Built on TSMC's 55 nm embedded flash process technology

High productivity design tools • Quartus® Prime Lite edition (no cost license)

• Qsys system integration tool

• DSP Builder for Intel® FPGAs

• Nios® II Embedded Design Suite (EDS)

1 MAX® 10 FPGA Device Overview

and Stratix words and logos are trademarks of Intel Corporation or its subsidiaries in the U.S. and/or other

countries. Intel warrants performance of its FPGA and semiconductor products to current specifications in

accordance with Intel's standard warranty, but reserves the right to make changes to any products and services

at any time without notice. Intel assumes no responsibility or liability arising out of the application or use of any

information, product, or service described herein except as expressly agreed to in writing by Intel. Intel

customers are advised to obtain the latest version of device specifications before relying on any published

information and before placing orders for products or services.

*Other names and brands may be claimed as the property of others.

ISO

9001:2008

Registered

1.2 Summary of MAX 10 Device Features

Table 2. Summary of Features for MAX 10 Devices

Feature Description

Technology 55 nm TSMC Embedded Flash (Flash + SRAM) process technology

Packaging • Low cost, small form factor packages—support multiple packaging

technologies and pin pitches

• Multiple device densities with compatible package footprints for seamless

migration between different device densities

• RoHS6-compliant

Core architecture • 4-input look-up table (LUT) and single register logic element (LE)

• LEs arranged in logic array block (LAB)

• Embedded RAM and user flash memory

• Clocks and PLLs

• Embedded multiplier blocks

• General purpose I/Os

Internal memory blocks • M9K—9 kilobits (Kb) memory blocks

• Cascadable blocks to create RAM, dual port, and FIFO functions

User flash memory (UFM) • User accessible non-volatile storage

• High speed operating frequency

• Large memory size

• High data retention

• Multiple interface option

Embedded multiplier blocks • One 18 × 18 or two 9 × 9 multiplier modes

• Cascadable blocks enabling creation of filters, arithmetic functions, and image

processing pipelines

ADC • 12-bit successive approximation register (SAR) type

• Up to 17 analog inputs

• Cumulative speed up to 1 million samples per second ( MSPS)

• Integrated temperature sensing capability

Clock networks • Global clocks support

• High speed frequency in clock network

Internal oscillator Built-in internal ring oscillator

PLLs • Analog-based

• Low jitter

• High precision clock synthesis

• Clock delay compensation

• Zero delay buffering

• Multiple output taps

General-purpose I/Os (GPIOs) • Multiple I/O standards support

• On-chip termination (OCT)

• Up to 830 megabits per second (Mbps) LVDS receiver, 800 Mbps LVDS

transmitter

External memory interface (EMIF) 1Supports up to 600 Mbps external memory interfaces:

continued...

1 EMIF is only supported in selected MAX 10 device density and package combinations. Refer to

the External Memory Interface User Guide for more information.

1 MAX® 10 FPGA Device Overview

MAX 10 FPGA Device Overview

Feature Description

• DDR3, DDR3L, DDR2, LPDDR2 (on 10M16, 10M25, 10M40, and 10M50.)

• SRAM (Hardware support only)

Note: For 600 Mbps performance, –6 device speed grade is required.

Performance varies according to device grade (commercial, industrial, or

automotive) and device speed grade (–6 or –7). Refer to the MAX 10

Device Data Sheet or External Memory Interface Spec Estimator for more

details.

Configuration • Internal configuration

• JTAG

• Advanced Encryption Standard (AES) 128-bit encryption and compression

options

• Flash memory data retention of 20 years at 85 °C

Flexible power supply schemes • Single- and dual-supply device options

• Dynamically controlled input buffer power down

• Sleep mode for dynamic power reduction

1.3 MAX 10 Device Ordering Information

Figure 1. Sample Ordering Code and Available Options for MAX 10 Devices

V : Wafer-Level Chip Scale (WLCSP)

E : Plastic Enhanced Quad Flat Pack (EQFP)

M : Micro FineLine BGA (MBGA)

U : Ultra FineLine BGA (UBGA)

F : FineLine BGA (FBGA)

Family Signature

Package Type

WLCSP Package Type

36 : 36 pins, 3 mm x 3 mm

81 : 81 pins, 4 mm x 4 mm

EQFP Package Type

144 : 144 pins, 22 mm x 22 mm

UBGA Package Type

169 : 169 pins, 11 mm x 11 mm

324 : 324 pins, 15 mm x 15 mm

FBGA Package Type

256 : 256 pins, 17 mm x 17 mm

484 : 484 pins, 23 mm x 23 mm

672 : 672 pins, 27 mm x 27 mm

MBGA Package Type

153 : 153 pins, 8 mm x 8 mm

Package Code

Operating Temperature

FPGA Fabric

Speed Grade Optional Suffix

Indicates specific device

options or shipment method

6 (fastest)

10M 16 DA U 484 I 7 G

SC : Single supply - compact features

SA : Single supply - analog and flash features

with RSU option

DC Dual supply - compact features

DF Dual supply - flash features with RSU option

DA Dual supply - analog and flash features

with RSU option

Feature Options

02 : 2K logic elements

04 : 4K logic elements

08 : 8K logic elements

16 : 16K logic elements

25 : 25K logic elements

40 : 40K logic elements

50 : 50K logic elements

Member Code

10M : MAX 10

G : RoHS6

ES : Engineering sample

P : Leaded package

C : Commercial (T = 0° C to 85° C)

I : Industrial (T = - 40° C to 100° C)

A : Automotive (T = - 40° C to 125° C)

Note: The –I6 and –A6 speed grades of the MAX 10 FPGA devices are not available by

default in the Quartus Prime software. Contact your local Intel sales representatives

for support.

Related Links

•MAX 10 General Purpose I/O User Guide

•MAX 10 High-Speed LVDS I/O User Guide

1.6 MAX 10 Vertical Migration Support

Vertical migration supports the migration of your design to other MAX 10 devices of

different densities in the same package with similar I/O and ADC resources.

1 MAX® 10 FPGA Device Overview

MAX 10 FPGA Device Overview

1.6.1 MAX 10 I/O Vertical Migration Support

Figure 2. Migration Capability Across MAX 10 Devices

• The arrows indicate the migration paths. The devices included in each vertical

migration path are shaded. Some packages have several migration paths. Devices

with lesser I/O resources in the same path have lighter shades.

• To achieve the full I/O migration across product lines in the same migration path,

restrict I/Os usage to match the product line with the lowest I/O count.

Device

Package

V36 V81 M153 U169 U324 F256 E144 F484 F672

10M02

10M04

10M08

10M16

10M25

10M40

10M50

Note: To verify the pin migration compatibility, use the Pin Migration View window in the

Quartus Prime software Pin Planner.

1.6.2 MAX 10 ADC Vertical Migration Support

Figure 3. ADC Vertical Migration Across MAX 10 Devices

The arrows indicate the ADC migration paths. The devices included in each vertical

migration path are shaded.

Device

Package

M153 U169 U324 F256 E144 F484 F672

10M04

10M08

10M16

10M25

10M40

10M50

Dual ADC Device: Each ADC (ADC1 and ADC2) supports 1 dedicated analog input pin and 8 dual function pins.

Single ADC Device: Single ADC that supports 1 dedicated analog input pin and 16 dual function pins.

Single ADC Device: Single ADC that supports 1 dedicated analog input pin and 8 dual function pins.

1 MAX® 10 FPGA Device Overview

MAX 10 FPGA Device Overview

Table 7. Pin Migration Conditions for ADC Migration

Source Target Migratable Pins

Single ADC device Single ADC device You can migrate all ADC input pins

Dual ADC device Dual ADC device

Single ADC device Dual ADC device • One dedicated analog input pin.

• Eight dual function pins from the ADC1 block of the

source device to the ADC1 block of the target device.

Dual ADC device Single ADC device

1.7 Logic Elements and Logic Array Blocks

The LAB consists of 16 logic elements (LE) and a LAB-wide control block. An LE is the

smallest unit of logic in the MAX 10 device architecture. Each LE has four inputs, a

four-input look-up table (LUT), a register, and output logic. The four-input LUT is a

function generator that can implement any function with four variables.

Figure 4. MAX 10 Device Family LEs

Row, Column,

And Direct Link

Routing

data 1

data 2

data 3

data 4

labclr1

labclr2

Chip-Wide

Reset

(DEV_CLRn)

labclk1

labclk2

labclkena1

labclkena2

LE Carry-In

LAB-Wide

Synchronous

Load

LAB-Wide

Synchronous

Clear

Row, Column,

And Direct Link

Routing

Local

Routing

Output

Programmable

Routing from

previous LE

LE Carry-Out

Synchronous

Load and

Clear Logic

Carry

Chain

Look-Up Table

(LUT)

Asynchronous

Clear Logic

Clock &

Clock Enable

Select

ENA

CLRN

1.8 Analog-to-Digital Converter

MAX 10 devices feature up to two ADCs. You can use the ADCs to monitor many

different signals, including on-chip temperature.

1 MAX® 10 FPGA Device Overview

MAX 10 FPGA Device Overview

Table 8. ADC Features

Feature Description

12-bit resolution • Translates analog signal to digital data for information processing, computing,

data transmission, and control systems

• Provides a 12-bit digital representation of the observed analog signal

Up to 1 MSPS sampling rate Monitors single-ended external inputs with a cumulative sampling rate of 25

kilosamples per second to 1 MSPS in normal mode

Up to 17 single-ended external inputs

for single ADC devices

One dedicated analog and 16 dual function input pins

Up to 18 single-ended external inputs

for dual ADC devices

• One dedicated analog and eight dual-function input pins in each ADC block

• Simultaneous measurement capability for dual ADC devices

On-chip temperature sensor Monitors external temperature data input with a sampling rate of up to 50

kilosamples per second

1.9 User Flash Memory

The user flash memory (UFM) block in MAX 10 devices stores non-volatile information.

UFM provides an ideal storage solution that you can access using Avalon Memory-

Mapped (Avalon-MM) slave interface protocol.

Table 9. UFM Features

Features Capacity

Endurance Counts to at least 10,000 program/erase cycles

Data retention • 20 years at 85 ºC

• 10 years at 100 ºC

Operating frequency Maximum 116 MHz for parallel interface and 7.25 MHz for

serial interface

Data length Stores data up to 32 bits length in parallel

1.10 Embedded Multipliers and Digital Signal Processing Support

MAX 10 devices support up to 144 embedded multiplier blocks. Each block supports

one individual 18 × 18-bit multiplier or two individual 9 × 9-bit multipliers.

With the combination of on-chip resources and external interfaces in MAX 10 devices,

you can build DSP systems with high performance, low system cost, and low power

consumption.

You can use the MAX 10 device on its own or as a DSP device co-processor to improve

price-to-performance ratios of DSP systems.

You can control the operation of the embedded multiplier blocks using the following

options:

• Parameterize the relevant IP cores with the Quartus Prime parameter editor

• Infer the multipliers directly with VHDL or Verilog HDL

System design features provided for MAX 10 devices:

1 MAX® 10 FPGA Device Overview

MAX 10 FPGA Device Overview

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