ARCHITECTURE OVERVIEW
The following sections describe the functional blocks of the KAI-4011/KAI-4021 Imager board (refer to Figure 1).
POWER FILTERING AND REGULATION
Power is supplied to the Imager Board via the J1
interface connector. The power supplies are de-coupled
and filtered with ferrite beads and capacitors to suppress
noise. Voltage regulators are used to create the +15 and
–15V supplies from the VPLUS and VMINUS supplies.
LVDS RECEIVERS / TTL BUFFERS
LVDS timing signals are input to the Imager Board via
the J1 interface connector. These signals are shifted to
TTL levels before being sent to the CCD clock drivers.
CCD PIXEL-RATE CLOCK DRIVERS (H1, H2 &
RESET CLOCKS)
The pixel rate CCD clock drivers utilize two fast switching
transistors that are designed to translate TTL-level input
clock signals to the voltage levels required by the CCD.
The high level and low level of the CCD clocks are set by
potentiometers.
RESET CLOCK ONE-SHOT (U15; NOT
POPULATED)
The pulse width of the RESET_CCD clock used to be set
by a programmable One-Shot. The One-Shot was
configured to provide a RESET_CCD clock signal with a
pulse width from 5ns to 15ns. Now, the pulse width
control functionality is provided by the KSC-1000 Timing
Generator Board, and the one-shot has been bypassed by
removing U15 and inserting a shorting resistor on pads 1
and 2 of U15.
CCD VCLK DRIVERS
The vertical clock (VCLK) drivers consist of MOSFET
driver IC’s. These drivers are designed to translate the
TTL-level clock signals to the voltage levels required by
the CCD. The high, middle, and low voltage levels of the
vertical clocks are set by potentiometers buffered by
operational amplifiers configured as voltage followers.
The current sources for these voltage levels are high
current (up to 600 mA) transistors. The V2_CCD high
level clock voltage is switched from V_MID to V_HIGH
once per frame to transfer the charge from the
photodiodes to the vertical CCDs.
CCD FDG DRIVER
The Fast Dump Gate (FDG) driver is a transistor that will
switch the voltage on the FDG pin of the CCD from
FDG_LOW to FDG_HIGH during Fast Dump Gate
operation. When not in operation, or when the Fast
Dump Gate feature is not being utilized, the FDG pin of
the CCD is held at FDG_LOW. The FDG_HIGH and
FDG_LOW voltage levels of the FDG driver are set by
resistor divider circuits, and are buffered by operational
amplifiers configured as voltage followers.
VES CIRCUIT
The quiescent CCD substrate voltage (VSUB) is set by a
potentiometer. For electronic shutter operation, the VES
signal drives a transistor amplifier circuit that AC-
couples the voltage difference between the VPLUS and
VMINUS supplies onto the Substrate voltage. This
creates the necessary potential to clear all charge from
the photodiodes, thereby acting as an electronic shutter
to control exposure.
CCD BIAS VOLTAGES
The CCD bias voltages are set by potentiometers,
buffered by operational amplifiers configured as voltage
followers. The bias voltages are de-coupled at the CCD
pin.
CCD IMAGE SENSOR
This evaluation board supports the Kodak KAI-4011 and
KAI-4021 Interline CCD image sensors.
EMITTER-FOLLOWER
The VOUT_CCD signals are buffered using bipolar
junction transistors in the emitter-follower configuration.
These circuits also provide the necessary 5mA current
sink for the CCD output circuits.
LINE DRIVERS
The buffered VOUT_CCD signals are AC-coupled and
driven from the Imager Board by operational amplifiers
©Eastman Kodak Company, 2005 www.kodak.com/go/imagers Revision 4.0 (MTD/PS-0521) p4
