MC80F0424/0432/0448 Preliminary
MAR. 2005 Ver 0.2
16. SERIAL INPUT/OUTPUT (SIO) ................................................................................................................. 78
16.1 Transmission/Receiving Timing .......................................................................................................... 79
16.2 The method of Serial I/O ..................................................................................................................... 81
16.3 The Method to Test Correct Transmission .......................................................................................... 81
17. UNIVERSAL ASYNCHRONOUS RECEIVER/TRANSMITTER (UART) ................................................... 82
17.1 UART Serial Interface Functions ........................................................................................................ 82
17.2 Serial Interface Configuration ............................................................................................................. 83
17.3 Communication operation ................................................................................................................... 85
17.4 Relationship between main clock and baud rate ................................................................................ 86
17.5 Communication operation ................................................................................................................... 87
18. BUZZER FUNCTION ................................................................................................................................. 88
19. INTERRUPTS ............................................................................................................................................ 90
19.1 Interrupt Sequence ............................................................................................................................. 92
19.2 BRK Interrupt ...................................................................................................................................... 94
19.3 Shared Interrupt Vector ....................................................................................................................... 94
19.4 Multi Interrupt ...................................................................................................................................... 95
19.5 External Interrupt ................................................................................................................................ 96
20. OPERATION MODE .................................................................................................................................. 98
20.1 Operation Mode Switching .................................................................................................................. 99
21. POWER SAVING OPERATION .............................................................................................................. 101
21.1 Sleep Mode ....................................................................................................................................... 101
21.2 Stop Mode ......................................................................................................................................... 102
21.3 Stop Mode at Internal RC-Oscillated Watchdog Timer Mode ........................................................... 105
21.4 Minimizing Current Consumption ...................................................................................................... 107
22. OSCILLATOR CIRCUIT .......................................................................................................................... 109
23. RESET ..................................................................................................................................................... 110
24. POWER FAIL PROCESSOR ................................................................................................................... 111
25. FLASH PROGRAMMING ........................................................................................................................ 113
25.1 Lock bit .............................................................................................................................................. 113
25.2 Power Fail Detection level ................................................................................................................ 113
26. Emulator EVA. Board Setting .............................................................................................................. 114
27. IN-SYSTEM PROGRAMMING (ISP) ....................................................................................................... 117
27.1 Getting Started / Installation .............................................................................................................. 117
27.2 Basic ISP S/W Information ................................................................................................................ 117
27.3 Hardware Conditions to Enter the ISP Mode .................................................................................... 119
27.4 Reference ISP Circuit Diagram and MagnaChip Supplied ISP Board .............................................. 120
INSTRUCTION MAP........................................................................................................................................... i
INSTRUCTION SET........................................................................................................................................... ii
MASK ORDER SHEET................................................................................................................................... viii
