Microchip Technology SAM L11 Xplained Pro Bedienungsanleitung

AN5365

SAM L11 Security Reference Guide

Introduction

This document is intended to help the developer to use SAM L11 security features for building secure

embedded applications.

The following application development aspects are covered in this document:

• Single and dual developer approach

• Secure solution development using SAM L11 ecosystem

• Secure software protection using ARM® TrustZone® for cortex®-M and Debug Access Levels

• System root of trust using Secure boot

The use of key security features is illustrated using bare-metal software examples on the following:

• Using SAM L11 Secure, Non-Secure, and Mix Secured peripherals.

• Using an embedded Cryptographic Accelerator (CRYA) for AES-128, SHA-256, and GCM algorithm.

• Using Data Flash and Trust RAM for storing and protecting application secrets using tamper

detection, scrambling, and silent accesses.

Table of Contents

Introduction......................................................................................................................1

1. Introduction to SAM L11 Security Features............................................................... 3

1.1. TrustZone for ARMv8-M ..............................................................................................................3

1.2. Secure and Non-Secure Peripherals............................................................................................9

1.3. Mix-Secure Integrated Peripherals.............................................................................................10

1.4. Debug Access Level (DAL) and Chip Erase.............................................................................. 13

1.5. Secure Boot................................................................................................................................17

2. SAM L11 Application Development (Customer A and Customer B)........................ 21

2.1. Single-Developer Approach....................................................................................................... 21

2.2. Dual-Developer Approach.......................................................................................................... 21

2.3. Develop a Secure Solution (Customer A).................................................................................. 22

2.4. Develop a Non-Secure Project (Customer B)............................................................................ 40

2.5. Developing Solution with Secure Boot Program (Customer A).................................................. 56

3. Software Use Case Examples.................................................................................66

3.1. Non-Secure Peripheral (TC0).....................................................................................................66

3.2. Secure Peripheral (TC0)............................................................................................................ 68

3.3. Mix-Secure Peripheral (EIC)...................................................................................................... 70

3.4. TrustRAM................................................................................................................................... 74

3.5. Cryptographic Accelerator (CRYA).............................................................................................76

3.6. Data Flash.................................................................................................................................. 78

4. Revision History.......................................................................................................80

The Microchip Web Site................................................................................................ 81

Customer Change Notification Service..........................................................................81

Customer Support......................................................................................................... 81

Microchip Devices Code Protection Feature................................................................. 81

Legal Notice...................................................................................................................82

Trademarks................................................................................................................... 82

Quality Management System Certified by DNV.............................................................83

Worldwide Sales and Service........................................................................................84

AN5365

1. Introduction to SAM L11 Security Features

1.1 TrustZone for ARMv8-M

The central security element for the Microchip SAM L11 microcontroller (MCU) is the implementation of

the TrustZone for an ARMv8-M device. The TrustZone technology is a System-on-Chip (SoC) and MCU

system-wide approach to security that enables Secure and Non-Secure application code to run on a

single MCU.

TrustZone for an ARMv8-M device is based on a specific hardware that is implemented in the Cortex-M23

core, which is combined with a dedicated secure instructions set. It enables creating multiple software

security domains that restricts access to selected memory, peripherals, and I/O to trusted software

without compromising the system performances.

The main goal of the TrustZone for a ARMv8-M device is to simplify security assessment of a deeply

embedded device. The principle behind the TrustZone for a ARMv8-M embedded software application is

illustrated in the figure below.

Figure 1-1. Standard Interactions Between Secure and Non-Secure States

In the SAM L11 Cortex-M23 Core implementation, the security management is done using the

Implementation Defined Attribution Unit (IDAU). The IDAU interface controls the access to the execution

of specific instructions which are based on the current core security state and the address of the

instruction. The figure below illustrates the Core/Debugger access verification, performed by the system

prior to allowing access to specific memory region.

AN5365

Introduction to SAM L11 Security Features

Figure 1-2. IDAU Interface and Memory Accesses

Core/Debugger

access

Combine

IDAU

Responder

IDAU

Interface

Non-

Secure

MPU

Secure

MPU

Access to

memory

Cortex-M23

Address

S / NS / NCS

SAM L11

Thanks to this implementation, a simple function call or an interrupt processing results in a branch to a

specific security state as illustrated in the figure below. This allows for efficient calling by avoiding any

code and execution overhead.

Figure 1-3. ARMv8-M with TrustZone States Transition

AN5365

Introduction to SAM L11 Security Features

1.1.1 Memory Security Attribution

To differentiate and isolate the Secure code from the Non-Secure code, the SAM L11 memory is divided

into ten memory regions as shown in the figure below. Each region size can be configured using

dedicated NVM fuses, such as BS, BNSC, BOOTPROT, AS, ANSC, DS, and RS.

Figure 1-4. SAM L11 Memory Regions

SecureFlash

(BOOTRegion)

Non‐SecureCallableFlash

(BOOTRegion)

Non‐SecureFlash

(BOOTRegion)

SecureFlash

(APPLICATIONRegion)

Non‐SecureCallableFlash

(APPLICATIONRegion)

Non‐SecureFlash

(APPLICATIONRegion)

0x00000000

BS x0x100– BNSC x0x20

BOOTPROT x0x100

BS x0x100

(BOOTPROT +AS)x0x100–

ANSC x0x20

(BOOTPROT +AS)x0x100

0x00010000

Flash(Upto64KB)

SecureSRAM

Non‐SecureSRAM

SRAM(Upto16KB)

SecureDataFlash

Non‐SecureDataFlash

DataFlash(2KB)

0x400000

0x400000+(DS*0x20)

0x400800

0x20000000

0x20000000+(RS*0x80)

0x20004000

Each memory region is preconfigured in the hardware with one of the following attributes:

• Non-Secure (NS): Non-Secure addresses are used for memory and peripherals, which are

accessible by all software running on the device.

• Secure (S): Secure addresses are used for memory and peripherals, which are accessible only by

Secure software.

• Non-Secure Callable (NSC): NSC is a special type of Secure memory location. It enables software

transition from a Non-Secure to a Secure state.

The security attribute of each region will define the security state of the code stored in this region.

1.1.2 Secure and Non-Secure Function Call Mechanism

To prevent Secure code and data from being accessed from a Non-Secure state, the Secure code must

meet several requirements. The responsibility for meeting these requirements is shared between the

MCU architecture, software architecture, and the toolchain configuration.

At the core level, a set of Secure instructions dedicated to ARMv8-M devices are used to preserve and

protect the secure register values during the CPU security state transition.

• Secure Gateway (SG): Used for switching from a Non-Secure to a Secure state at the first instruction

of a Secure entry point.

• Branch with exchange to Non-Secure state (BXNS): Used by the Secure software to branch, or

return to the Non-Secure program.

• Branch with link and exchange to Non-Secure state (BLXNS): Used by the Secure software to call

the Non-Secure functions.

At the toolchain level, a ‘C’ language Extension (CMSE) provided by ARM must be used to ensure the

use of AMRv8-M Secure instruction.

AN5365

Introduction to SAM L11 Security Features

At the software architecture level, specific Secure and Non-Secure function call mechanisms must be

used to ensure security, which are described in the following sections:

1.1.2.1 Non-Secure Callable APIs

When working with TrustZone for ARMv8-M, the application developer can define a set of Non-Secure

callable APIs which can be used to access the Secure code from the Non-Secure world. These APIs,

known as Secure Gateways (SG) or veneers are in charge of the CPU Security state switch and allow the

decoupling of Secure entry points from the rest of the Secure code. Therefore, limiting the amount of

code that can potentially be accessed by the Non-Secure state.

SG are expected to be placed in NSC memory regions, which are executable only when the CPU is in

Non-Secure state. The rest of the Secure code is expected to be placed in the Secure memory regions

which are not accessible when the CPU is in Non-Secure state, see figure below.

Figure 1-5. Non-Secure Callable APIs Mechanism

Using Non-Secure callable APIs require the use of specific Cortex-M23 instructions that ensure security

during the core security state switching. A direct API function call from the Non-Secure to the Secure

software entry points is allowed only if the first instruction of the entry point is a SG and is in a Non-

Secure callable memory location. The use of the special instructions (BXNS and BLXNS) are also

required to branch to Non-Secure code.

The following code illustrates Secure function and its SG APIs declaration and definition using ARM GCC

toolchain with a ‘’C language Extension (CMSE).

Veneer.h:

/* Non-secure callable functions */

extern int nsc_func1(int x);

Veneer.c (linked in the NSC memory region of the device):

/* Non-secure callable (entry) function */

int __attribute__((cmse_nonsecure_entry)) nsc_func1(int x)

{

return secure_func1(x);

}

AN5365

Introduction to SAM L11 Security Features

Secure_function.c (linked in the secure memory region of the device):

int secure_func1(int x)

{

return x + 3;

}

1.1.2.2 Non-Secure Software Callbacks

The Secure code can define and use software callbacks to execute functions from the Non-Secure world.

This is a consequence of separating Secure and Non-Secure code into separate executable files. The

following figure shows the software callback approach.

Figure 1-6. Non-Secure Software Callbacks Flow Chart

The management of callback functions can be performed using the BLXNS instruction. The following

figure illustrates the Non-Secure callback mechanism

AN5365

Introduction to SAM L11 Security Features

Figure 1-7. Non-Secure Software Callback Mechanism

Note: The definition of Non-Secure software callback is done through pointer to Non-Secure code

location . If not correctly checked in the Secure application, a wrong use of pointers can lead to security

weakness that enables execution of any Secure functions by the Non-Secure code. To overcome this

disadvantages, a set of CMSE functions based on the new Cortex-M23 TT instructions is provided.

1.1.2.3 Security State and Call Mismatch

Any attempts to access Secure regions from the Non-Secure code, or a mismatch between the code that

is executed and the security state of the system results in a HardFault exception as shown in the

following figure.

Figure 1-8. Security State and Call Mismatch

Non-Secure

…

MOVr0,#10

MOV r1,#abc

ADD r2,r0,r1

…

BLXsecure_addr

CMP r1,#result

…

Secure NSC

…

MOVS r1,#0

MOVS r3,#1

…

Secure

DCD0xE97FE97F

MOVSr1,#0

MOVSr3,#1

…

BXNSlr

…

AN5365

Introduction to SAM L11 Security Features

1.1.3 Secure and Non-Secure Interrupts Handling

The Cortex-M23 (ARMv8-M architecture) uses the same exception stacking mechanism as the ARMv7-M

architecture, where a subset of core registers is stored automatically into the stack (hardware context

saving). This permits immediate execution of the interrupt handler without the need to perform a context

save in the software. ARMV8-M extends this mechanism to provide enhanced security based on two

different stack pointers (a Secure stack pointer and a Non-Secure stack pointer).

According to the priority settings configured in the Nested Vector Interrupt Controller (NVIC), Secure code

execution can interrupt Non-Secure code execution, and Non-Secure code can interrupt Secure code

execution. The NVIC registers at the core level are duplicated. This allows two vector table definitions,

one for Secure and another for Non-Secure.

At product start-up, all interrupts are mapped by default to the Secure world (Secure vector table).

Specific CMSIS functions accessible in the Secure world, allocate each interrupt vector to a Non-Secure

handler (declared in Non-Secure vector table).

As illustrated in the figure below, if the Secure code is running when a higher priority Non-Secure interrupt

arrives, the core pushes all its register content into a dedicated Secure stack. Registers are then zeroed

automatically to prevent any information being read, and the core executes the Non-Secure exception

handler. When the Non-Secure handler execution is finished, the hardware recovers all the registers from

the Secure stack automatically. This mechanism is managed in hardware and does not require any

software intervention. This allows a Secure handover from running Secure code to a Non-Secure

interrupt handler and returning to running Secure code.

Figure 1-9. Cortex-M 23 Interrupt Mechanism

1.2 Secure and Non-Secure Peripherals

The SAM L11 extends the concept of TrustZone to its integrated peripherals and offers the possibility to

allocate specific peripheral to Secure and Non-Secure world. the management of each peripheral security

attribution is done through the Peripheral Access Controller (PAC).

As shown in the figure below, The PAC controller embeds a set of registers that define the security

attribution of each integrated peripheral of the system. These registers are configured at device startup by

the ROM code which set the PAC.NONSECx registers according to the user configuration stored in the

User Row (UROW) fuses.

AN5365

Introduction to SAM L11 Security Features

Figure 1-10. PAC.NONSECx Registers Description

Important: The peripherals security attribution cannot be changed by accessing the

PAC.NONSECx registers during application run-time. Any changes must be done using the

User Row fuses and require a reset of the SAM L11 device. The application can read the

PAC.NONSECx register to get the current attribution of integrated peripherals.

Peripherals can be categorized into two groups depending on their PAC security attribution and their

internal secure partitioning capabilities (standard/mix-secure):

• Non-Secure peripheral: A standard peripheral configured as Non-Secure in the PAC. The security

attribution of the whole peripheral is defined by the associated NONSECx fuse set to one. Secure

and Non-Secure accesses to the peripheral are granted.

• Secure peripheral: A standard peripheral configured as Secure in the PAC. The security attribution of

the whole peripheral is defined by the associated NONSECx fuse set to zero. Secure accesses to the

peripheral are granted where Non-Secure accesses are discarded (Write is ignored, Read 0x0), and

a PAC error is triggered.

When a peripheral is allocated to the Secure world, only Secure accesses to its registers are granted,

and interrupt handling should be managed in the Secure world only.

1.3 Mix-Secure Integrated Peripherals

The SAM L11 embeds five Mix-Secure peripherals, which allow part of their internal resources to be

shared between Secure and Non-Secure worlds. A complete list of SAM L11 Mix-Secure peripherals and

their shared resources are as follows:

• Peripheral Access Controller (PAC): Manages the peripherals security attribution (Secure or Non-

Secure).

• Non-Volatile Memory Controller (NVMCTRL): Handles the Secure and Non-Secure Flash region

programming.

• I/O Pin Controller (PORT): Supports individual allocation of each I/O to the Secure or Non-Secure

applications.

• External Interrupt Controller (EIC): Supports individual assignment of each external interrupt to the

Secure or Non-Secure applications.

AN5365

Introduction to SAM L11 Security Features

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