Microsemi SmartFusion2 MSS Bedienungsanleitung

DG0388

Demo Guide

SmartFusion2 SoC FPGA Error Detection and

Correction of eSRAM Memory - Libero SoC v11.8 SP1

50200388. 10.0 10/17

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globally. Learn more at www.microsemi.com.

DG0388 Demo Guide Revision 10.0 iii

Contents

1 Revision History . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1

1.1 Revision 10.0 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1

1.2 Revision 9.0 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1

1.3 Revision 8.0 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1

1.4 Revision 7.0 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1

1.5 Revision 6.0 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1

1.6 Revision 5.0 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1

1.7 Revision 4.0 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1

1.8 Revision 3.0 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1

1.9 Revision 2.0 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1

1.10 Revision 1.0 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1

2 SmartFusion2 SoC FPGA - Error Detection and Correction of eSRAM Memory . . . 2

2.1 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2

2.2 Demo Requirements . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3

2.2.1 Design Files . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3

2.3 Demo Design Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4

2.3.1 Loop Test . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4

2.3.2 Manual Test . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4

2.4 Running the Demo . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6

2.4.1 Demo Setup . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6

2.4.2 Graphical User Interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7

2.4.3 Running the Design . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8

2.5 Conclusion . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11

DG0388 Demo Guide Revision 10.0 iv

Figures

Figure 1 Top-Level Block Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2

Figure 2 Demo Design Top-Level Structure . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3

Figure 3 Design Flow . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5

Figure 4 USB to UART Bridge Drivers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6

Figure 5 SmartFusion2 Security Evaluation Kit Board Setup . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7

Figure 6 eSRAM – EDAC Demo GUI . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8

Figure 7 FlashPro Programming Window . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9

Figure 8 1-Bit Error Correction Tab . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10

Figure 9 2-Bit Error Detection Tab . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11

DG0388 Demo Guide Revision 10.0 v

Tables

Table 1 Demo Requirements . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3

Table 2 SmartFusion2 Security Evaluation Kit Jumper Settings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6

Table 3 eSRAM Memory Addresses Used in Loop Test . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10

Revision History

DG0388 Demo Guide Revision 10.0 1

1 Revision History

The revision history describes the changes that were implemented in the document. The changes are

listed by revision, starting with the current publication.

1.1 Revision 10.0

Updated the document for Libero SoC v11.8 SP1 software release.

1.2 Revision 9.0

Updated the document for Libero SoC v11.8 software release.

1.3 Revision 8.0

Updated the document for Libero SoC v11.7 software release (SAR 77402).

1.4 Revision 7.0

Updated the document for Libero SoC v11.6 software release (SAR 72777).

1.5 Revision 6.0

Updated the document for Libero SoC v11.5 software release (SAR 64979).

1.6 Revision 5.0

Updated the document for Libero SoC v11.4 software release (SAR 60476).

1.7 Revision 4.0

Updated the document for Libero SoC v11.3 software release (SAR 56852).

1.8 Revision 3.0

Updated the document for Libero SoC v11.2 software release (SAR 52960).

1.9 Revision 2.0

Updated the document for Libero SoC v11.0 software release (SAR 47858).

1.10 Revision 1.0

Revision 1.0 was the first publication of this document.

SmartFusion2 SoC FPGA - Error Detection and Correction of eSRAM Memory

DG0388 Demo Guide Revision 10.0 2

2 SmartFusion2 SoC FPGA - Error Detection

and Correction of eSRAM Memory

2.1 Introduction

This document describes the error detection and correction (EDAC) capabilities of the SmartFusion®2

devices on the embedded static random access memory (eSRAM).

The EDAC controllers implemented in the SmartFusion2 devices support single-error correction and

double-error detection (SECDED). All memories within the microcontroller subsystem (MSS) of the

SmartFusion2 are protected by SECDED. The eSRAM memory can be eSRAM_0 or eSRAM_1. The

address range of eSRAM_0 is 0x20000000 to 0x20007FFF and the address range of eSRAM_1 is

0x20008000 to 0x2000FFFF.

When SECDED is enabled:

• A write operation computes and adds 8 bits of SECDED code to every 32 bits of data

• A read operation reads and checks the data against the stored SECDED code to support 1-bit error

correction and 2-bit error detection

In this demo, the EDAC can be identified by the blinking light-emitting diode (LED) on the board and by

graphical user interface (GUI).

Figure 1 • Top-Level Block Diagram

The EDAC of eSRAM supports the following features:

1. SECDED mechanism

2. Provides interrupts to the ARM Cortex- M3 processor and FPGA fabric upon the detection of a

1-bit error or 2-bit error.

3. Stores the number of 1-bit and 2-bit errors to the error counter registers.

4. Stores the address of the last 1-bit or 2-bit error affected memory location.

5. Stores 1-bit or 2-bit error data into the SECDED registers.

6. Provides error bus signals to the FPGA fabric.

Refer to the EDAC chapter of the UG0443: SmartFusion2 and IGLOO2 FPGA Security and Reliability

User Guide and the eSRAM chapter of the UG0331: SmartFusion2 Microcontroller Subsystem User

Guide.

SmartFusion2

Graphical User

Interface

Running on Host PC

EDAC

Controller Logic

eSRAM

GPIO

LED

SmartFusion2 SoC FPGA - Error Detection and Correction of eSRAM Memory

DG0388 Demo Guide Revision 10.0 3

2.2 Demo Requirements

The following table lists the required hardware and software for running the demo.

2.2.1 Design Files

The demo design files are available for download from the following path in the Microsemi website:

http://soc.microsemi.com/download/rsc/?f=m2s_dg0388_liberov11p8_sp1_df

Design files include:

•Libero

• Programming files

• GUI Executable

• Readme file

The following figure shows the top-level structure of the design files. For further details, see the

readme.txt file.

Figure 2 • Demo Design Top-Level Structure

Table 1 • Demo Requirements

Hardware Requirements Description

SmartFusion2 Security Evaluation Kit:

• FlashPro4 programmer

• USB A to Mini - B USB cable

12 V Adapter

Rev D or later

Operating System Any 64-bit or 32-bit Windows XP SP2

Any 64-bit or 32-bit Windows 7

Software Requirements

Libero®system-on-chip (SoC) software v11.8 SP1

SoftConsole v4.0

FlashPro programming software v11.8 SP1

Host PC Drivers USB to UART drivers

For launching demo GUI Microsoft.NET Framework 4 client

GUI Executable

Libero

M2S90_eSRAM_EDAC_DF

<download_folder>

Programming File

readme.txt

SmartFusion2 SoC FPGA - Error Detection and Correction of eSRAM Memory

DG0388 Demo Guide Revision 10.0 4

2.3 Demo Design Description

Each eSRAM within the MSS is protected by a dedicated EDAC controller. EDAC detects a 1-bit error or

2-bit error when data is read from the memory. If EDAC detects the 1-bit error, the EDAC controller

corrects the same error bit. If EDAC is enabled for all the 1-bit and 2-bit errors, corresponding error

counters in the system registers are incremented and corresponding interrupts and error bus signals to

the FPGA fabric are generated.

In a single event upset (SEU) susceptible environment, random access memory (RAM) is prone to

transient errors caused by heavy ions. This happens in real-time. To demonstrate this, an error is

introduced manually and detection and correction is observed.

This demo design involves implementation of following tasks:

• Enable EDAC

• Write data to eSRAM

• Read data from eSRAM

• Disable EDAC

• Corrupt one or two bits

• Write data to eSRAM

• Enable EDAC

• Read the data

• In the case of a 1-bit error, the EDAC controller corrects the error, updates the corresponding status

registers, and gives the data written in step 2 at the read operation done at step 8.

• In the case of a 2-bit error, a corresponding interrupt is generated and the application must correct

the data or take the appropriate action in the interrupt handler. These two methods are

demonstrated in this demo.

Two tests are implemented in this demo: loop test and manual test and they are applicable to both 1-bit

and 2-bit errors.

2.3.1 Loop Test

Loop Test is executed when the SmartFusion2 receives a loop test command from the GUI. Initially, all

the error counters and EDAC related registers are placed in the RESET state.

The following steps are executed for each iteration:

1. Enable the EDAC controller.

2. Write the data to the specific eSRAM memory location.

3. Disable the EDAC controller.

4. Write the 1-bit or 2-bit error induced data to the same eSRAM memory location.

5. Enable the EDAC controller.

6. Read the data from the same eSRAM memory location.

7. Send the 1-bit or 2-bit error detection and 1-bit error correction data in case of 1-bit error to the GUI.

2.3.2 Manual Test

This method allows manual testing for enabling or disabling EDAC and write or read operation. Using this

method, 1-bit or 2-bit errors can be introduced to any location within the eSRAM. Enable the EDAC and

write data to the specified address using the GUI fields. Disable the EDAC and write 1-bit or 2-bit

corrupted data to the same address location. Enable the EDAC and read the data from the same address

location then the LED on the board toggles to notify the detection and correction of errors. The

corresponding error counter is displayed on the GUI. The GUI Serial Console logs all the actions

performed in SmartFusion2.

SmartFusion2 SoC FPGA - Error Detection and Correction of eSRAM Memory

DG0388 Demo Guide Revision 10.0 5

The following figure shows the eSRAM EDAC demo operations.

Figure 3 • Design Flow

Initialize the application

UART Rx Interrupt

Receive UART

messages and

decode as

commands

Command for

operation?

EDAC loop test Enable/Disable EDAC

Enable/Disable EDAC

Write data to the

specified DDR

address

1.Read data from address

specified in GUI

2.Send Error counters and

address of last error to

GUI

3.Clear status register

Read/Write? Write

Read

Loop

Send error detection and

correction summary to GUI

1.Write data to address X of DDR

With EDAC enabled

2.Read back data from address X

of DDR and induce 1-bit/2bit error

3.Write data to address X of DDR

with EDAC disabled

4.Read back data from address X

of DDR with EDAC enabled

Reset

Messages from

GUI

Andere Handbücher für SmartFusion2 MSS

Inhaltsverzeichnis

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