Motorola DSP56602 Bedienungsanleitung

MOTOROLA DSP56602User’sManual 9-1

SECTION 9

TRIPLE TIMER MODULE

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9-2 DSP56602User’sManual MOTOROLA

Triple Timer Module

9.1 INTRODUCTION. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .9-3

9.2 TRIPLE TIMER MODULE ARCHITECTURE . . . . . . . . . . . . . . .9-3

9.3 TIMER ARCHITECTURE . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .9-4

9.4 TRIPLE TIMER MODULE PROGRAMMING MODEL. . . . . . . . .9-6

9.5 TIMER MODES OF OPERATION. . . . . . . . . . . . . . . . . . . . . . .9-13

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Triple Timer Module

Introduction

MOTOROLA DSP56602User’sManual 9-3

9.1 INTRODUCTION

This section describes the triple timer module, composed of a common 14-bit prescaler

and three independent and identical general purpose 16-bit timer/event counters, each

with its own memory-mapped register set.

Each timer can use internal or external clocking and can interrupt the DSP after a

specified number of events (clocks) or can signal an external device after counting

internal events. Each timer connects to the external world through one bidirectional pin,

TIO. When the TIO pin is configured as an input, the timer functions as an external event

counter or measures external pulse width/signal period. When the TIO pin is used as an

output, the timer functions as either a timer, a watchdog, or a Pulse Width Modulator

(PWM) . When the TIO pin is not used by the timer, it can be configured as a General

Purpose I/O (GPIO) pin.

9.2 TRIPLE TIMER MODULE ARCHITECTURE

The triple timer module includes a 16-bit Timer Prescaler Load Register (TPLR), a 16-bit

Timer Prescaler Count Register (TPCR), a 14-bit Prescaler Counter, and three timers.

Each one of the three timers can use the Prescaler Clock as its clock source.

The Timer Prescaler Load Register (TPLR) is a 16-bit read/write register that controls the

Prescaler Divide Factor and the source for the prescaler input clock. The Timer Prescaler

Count Register (TPCR) is a 16-bit read-only register that reflects the current value in the

prescaler counter. The register bits are described in the following paragraphs. The 14-bit

Prescaler Counter is decremented on each rising edge of the prescaler input clock pulse.

The counter is enabled when at least one of the three timers is both enabled and is using

the prescaler output as its source. Figure 9-1 shows a block diagram of the triple timer

module.

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9-4 DSP56602User’sManual MOTOROLA

Triple Timer Module

Timer Architecture

9.3 TIMER ARCHITECTURE

Figure 9-2 shows a block diagram of a timer. It includes a 16-bit counter, a 16-bit

read/write Timer Control and Status Register (TCSR), a 16-bit read only Timer Count

Compare Register (TCPR), and logic for clock selection and interrupt generation. The

DSP views each timer as a memory-mapped peripheral occupying four 16-bit words in

the X data memory space. The user can use standard polled or interrupt programming

techniques. The programming model is shown in Figure 9-3 on page 9-6.

Figure 9-1 Triple Timer Module Block Diagram

Timer Prescaler

Count Register

GDB 16

TPLR 16

Timer 0

Timer 2

Timer 1

14-bit Prescaler

CLK/2 TIO0 TIO1 TIO2

TPCR

Timer Prescaler

Load Register

AA0743

Counter

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Triple Timer Module

Timer Architecture

MOTOROLA DSP56602User’sManual 9-5

Figure 9-2 16-bit Timer Module Block Diagram

GDB

Control/Status

TCSR

Counter

Timer interrupt

Timer Control

CLK/2TIO

Compare

TCPR

Logic

Load

TLR

Prescaled CLK

TCR

AA0744

16169

16161616

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9-6 DSP56602User’sManual MOTOROLA

Triple Timer Module

Triple Timer Module Programming Model

9.4 TRIPLE TIMER MODULE PROGRAMMING MODEL

The registers comprising the Triple Timer Module are shown in Figure 9-3.

Figure 9-3 Triple Timers Programming Model

TCSR0—X:$FF8F

TCSR1—X:$FF8B

TCSR2—X:$FF87

Timer Control/Status

Reset = $0000

Read/Write

DI DIR TRM INV TC3 TC2 TC0 TCIETOIE TEPCE DO

1110987654321015 14 13 12

TCR0—X:$FF8C

TCR1—X:$FF88

TCR2—X:$FF84

Timer Count Register

Reset = $0000

Read Only

Count Register

111098765432115 14 13 12

* Indicates reserved bits, read and written as 0 to ensure future compatibility

TPCR—X:$FF82

Timer Prescaler

Count Register

Reset = Uninitialized

Read Only

PC7 PC6 PC4 PC3 PC2 PC1 PC0

1110987654321015 14 13 12

TCF TOF TC1 *

TCPR0—X:$FF8D

TCPR1—X:$FF89

TCPR2—X:$FF85

Timer Compare Register

Reset = Uninitialized

Read/Write

Compare Register

1110987654321015 14 13 12

TPLR—X:$FF83

Timer Prescaler

Load Register

Reset = $0000

Read/Write

PL7 PL6 PL4 PL3 PL2 PL1 PL0

1110987654321015 14 13 12

PL5PL PL PL PL9 PL8

PS1 PS0

PC PC PC PC PC9 PC5

PC8

13 12 11 10

AA0745

TLR0—X:$FF8E

TLR1—X:$FF8A

TLR2—X:$FF86

Timer Load Register

Reset = Uninitialized

Write Only

Load Register

1110987654321015 14 13 12

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Triple Timer Module

Triple Timer Module Programming Model

MOTOROLA DSP56602User’sManual 9-7

9.4.1 Timer Prescaler Load Register (TPLR)

The Timer Prescaler Load Register (TPLR) is a 16-bit read/write register that controls the

prescaler Divide Factor and the source for the prescaler input clock. The control bits are

described in the following paragraphs.

9.4.1.1 Prescaler Preload Value (PL[13:0])—Bits 0–13

The Prescaler Preload Value bits (PL[13:0]) contain the prescaler preload value. This

preload value is loaded into the prescaler counter whenever either the counter reaches

the value of 0 or the counter switches state from disabled to enabled. For PL[13:0] = N,

the prescaler counts N + 1 source clock cycles before generating a prescaled clock pulse.

Therefore, the prescaler Divide Factor is the preload value + 1.

The PL[13:0] bits are cleared by hardware and software reset .

9.4.1.2 Prescaler Source (PS[1:0])—Bits 14–15

The Prescaler Source (PS[1:0]) bits control the source of the prescaler clock. Table 9-1

summarizes the functionality of the PS bits. The DSP internal clock CLK divided by two

is selected when the PS[1:0] bits are cleared. The other combinations select one of the TIO

pins as the source clock for the prescaler, regardless of the operating mode of the

selected timer.

Notes: 1. If the prescaler source clock is external, the prescaler counter is

incremented by the transitions on the TIO pin. The external clock is

internally synchronized to the internal clock and its frequency should be

lower than the DSP internal clock (CLK) divided by 4.

2. To ensure proper functionality, the PS[1:0] bits should be changed only

when the prescaler counter is disabled.

The PS[1:0] bits are cleared by hardware and software reset.

Table 9-1 PS[1:0] Bit Functionality

PS1 PS0 Prescaler Clock Source

0 0 DSP internal clock (CLK) divided by two

0 1 TIO0

1 0 TIO1

1 1 TIO2

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9-8 DSP56602User’sManual MOTOROLA

Triple Timer Module

Triple Timer Module Programming Model

9.4.2 Timer Prescaler Count Register (TPCR)

The Timer Prescaler Count Register (TPCR) is a 16-bit read-only register that reflects the

current value in the prescaler counter. The register bits are described in the following

paragraphs.

9.4.2.1 Prescaler Counter Value (PC[13:0])—Bits 0–13

The Prescaler Counter Value (PC[13:0]) bits contain the current value in the prescaler

counter.

9.4.2.2 Reserved Bits—Bits 14–15

These reserved bits are read as 0.

9.4.3 Timer Count Register (TCR)

The Timer Count Register (TCR) is a 16-bit read-only register. In Timer and Watchdog

modes, the counter contents can be read at any time by reading the TCR. In

Measurement modes, the TCR is loaded with the current value of the counter on the

appropriate edge of the input signal and its value can be read to determine the width,

period, or delay of the leading edge of the input signal (incoming on the TIO pin).

9.4.4 Timer Load Register (TLR)

The Timer Load Register (TLR) is a 16-bit write-only register. In all modes, the counter is

preloaded with the TLR value after the Timer Enable (TE) bit in the TCSR is set and a

first event occurs.

In Timer modes, if the Timer Reload Mode (TRM) bit is set, the counter is reloaded each

time after it has reached the value contained by the Timer Compare Register (TCR) and

the new event occurs. In Measurement modes, if the TRM bit is set, the counter is

reloaded with the TLR value on each appropriate edge of the input signal, after the

Timer Enable (TE) bit is set. In Pulse Width Modulation (PWM) modes, if the TRM bit is

set, the counter is reloaded each time after it has overflowed and the new event occurs.

In Watchdog modes, if the TRM bit is set, the counter is reloaded each time after it has

reached the value contained by the Timer Compare Register and the new event occurs.

In this mode, the counter is also reloaded whenever the TLR is written with a new value

while the TE bit is set. In all modes, if the TRM bit is cleared, the counter operates as free

running counter.

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Triple Timer Module

Triple Timer Module Programming Model

MOTOROLA DSP56602User’sManual 9-9

9.4.5 Timer Compare Register (TCPR)

The Timer Compare Register (TCPR) is a 16-bit read/write register that contains the

value to be compared to the counter value. The counter value is compared against the

value in the TCPR on every timer clock after the Timer Enable (TE) bit is set. When the

compare matches, the TCF bit is set. If interrupts are enabled (the TCIE bit is set), an

interrupt is also generated. In Measurement modes, the TCPR is ignored.

9.4.6 Timer Control/Status Register (TCSR)

The Timer Control/Status Register (TCSR) is a 16-bit read/write register that controls

the timer and reflects its status. The control and status bits are described in the following

paragraphs (see Figure 9-3 on page 9-6).

9.4.6.1 Timer Enable (TE)—Bit 0

The Timer Enable (TE) bit is used to enable or disable the timer. Setting the TE bit (TE =

1) enables the timer and clears the Timer Count Register (TCR). The counter starts

counting according to the mode defined by TC[3:0]. Clearing the TE bit disables the

timer. The TE bit is cleared by hardware and software reset.

Note: When all the three timers are disabled and not in GPIO mode, all three TIO

pins are tristated. In order to prevent undesired spikes on the TIO pins (when

switching from tri-state into active state), external pull-up or pull down

resistors should be tied to the TIO pins.

9.4.6.2 Timer Overflow Interrupt Enable (TOIE)—Bit 1

The Timer Overflow Interrupt Enable (TOIE) bit is used to enable the timer overflow

interrupts. The overflow interrupt is generated after the counter wraparound occurs;

that is, the counter value changes from $FFFF to $0000 when a new event occurs. Setting

the TOIE bit enables the overflow interrupts. When the TOIE bit is cleared, the overflow

interrupts are disabled. The TOIE bit is cleared by hardware and software reset.

9.4.6.3 Timer Compare Interrupt Enable (TCIE)–Bit 2

The Timer Compare Interrupt Enable (TCIE) bit is used to enable the timer compare

interrupts. The compare interrupt is generated after the counter matches the compare

interrupt occurs after (N – M + 1) events, where M is TLR value. Setting the TCIE bit

enables the compare interrupts. When the TCIE bit is cleared, the compare interrupts are

disabled. The TCIE bit is cleared by hardware and software reset.

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9-10 DSP56602User’sManual MOTOROLA

Triple Timer Module

Triple Timer Module Programming Model

9.4.6.4 Timer Control (TC[3:0])—Bits 4–7

The four Timer Control (TC[3:0]) bits control the source of the timer clock, the behavior

of the TIO pin and the Timer mode of operation. Table 9-2 summarizes the functionality

of the TC bits. A detailed description of the timer operating modes is given in Timer

Modes of Operation on page 9-13. The TC[3:0] bits are cleared by hardware and

software reset. To ensure proper functionality, the TC[3:0] bits should be changed only

when the timer is disabled.

Note: If the clock is external, the counter is incremented by transitions on the TIO

pin. The external clock is internally synchronized to the internal clock and its

frequency should be lower than the internal operating frequency divided by 4

(CLK/4).

Table 9-2 TC[3:0] Bit Functionality

TC3 TC2 TC1 TC0 TIO Clock Mode

0000GPIO Internal Timer GPIO

0001Output Internal Timer Pulse

0010Output Internal Timer Toggle

0011Input External Event Counter

0100Input Internal Input Width

0101Input Internal Input Period

0110Input Internal Capture

0111Output Internal Pulse Width Modulation(PWM)

1000 — —(Reserved)

1001Output Internal Watchdog Pulse

1010Output Internal Watchdog Toggle

1011 — —(Reserved)

1100 — —(Reserved)

1101 — —(Reserved)

1110 — —(Reserved)

1111Output Internal Timer Pulse

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