NEC 78K0/KD1 Series Bedienungsanleitung

Document No. U16315EJ1V0UD00 (1st edition)

Date Published July 2002 N CP(K)

Printed in Japan

µµ

PD780121

µµ

PD780121(A)

µµ

PD780121(A1)

µµ

PD780122

µµ

PD780122(A)

µµ

PD780122(A1)

µµ

PD780123

µµ

PD780123(A)

µµ

PD780123(A1)

µµ

PD780124

µµ

PD780124(A)

µµ

PD780124(A1)

µµ

PD78F0124

µµ

PD78F0124(A)

78K0/KD1

8-Bit Single-Chip Microcontrollers

Preliminary User’s Manual

Preliminary User’s Manual U16315EJ1V0UD

[MEMO]

Preliminary User’s Manual U16315EJ1V0UD 3

NOTES FOR CMOS DEVICES

1 PRECAUTION AGAINST ESD FOR SEMICONDUCTORS

Note:

Strong electric field, when exposed to a MOS device, can cause destruction of the gate oxide and

ultimately degrade the device operation. Steps must be taken to stop generation of static electricity

as much as possible, and quickly dissipate it once, when it has occurred. Environmental control

must be adequate. When it is dry, humidifier should be used. It is recommended to avoid using

insulators that easily build static electricity. Semiconductor devices must be stored and transported

in an anti-static container, static shielding bag or conductive material. All test and measurement

tools including work bench and floor should be grounded. The operator should be grounded using

wrist strap. Semiconductor devices must not be touched with bare hands. Similar precautions need

to be taken for PW boards with semiconductor devices on it.

2 HANDLING OF UNUSED INPUT PINS FOR CMOS

Note:

No connection for CMOS device inputs can be cause of malfunction. If no connection is provided

to the input pins, it is possible that an internal input level may be generated due to noise, etc., hence

causing malfunction. CMOS devices behave differently than Bipolar or NMOS devices. Input levels

of CMOS devices must be fixed high or low by using a pull-up or pull-down circuitry. Each unused

pin should be connected to V

or GND with a resistor, if it is considered to have a possibility of

being an output pin. All handling related to the unused pins must be judged device by device and

related specifications governing the devices.

3 STATUS BEFORE INITIALIZATION OF MOS DEVICES

Note:

Power-on does not necessarily define initial status of MOS device. Production process of MOS

does not define the initial operation status of the device. Immediately after the power source is

turned ON, the devices with reset function have not yet been initialized. Hence, power-on does

not guarantee out-pin levels, I/O settings or contents of registers. Device is not initialized until the

reset signal is received. Reset operation must be executed immediately after power-on for devices

having reset function.

EEPROM is a trademark of NEC Corporation.

Windows and Windows NT are either registered trademarks or trademarks of Microsoft Corporation in the

United States and/or other countries.

PC/AT is a trademark of International Business Machines Corporation.

HP9000 series 700 and HP-UX are trademarks of Hewlett-Packard Company.

SPARCstation is a trademark of SPARC International, Inc.

Solaris and SunOS are trademarks of Sun Microsystems, Inc.

Ethernet is a trademark of Xerox Corp.

OSF/Motif is a trademark of Open Software Foundation, Inc.

TRON stands for The Realtime Operating system Nucleus.

ITRON is an abbreviation of Industrial TRON.

Preliminary User’s Manual U16315EJ1V0UD

The export of these products from Japan is regulated by the Japanese government. The export of some or all of these

products may be prohibited without governmental license. To export or re-export some or all of these products from a

country other than Japan may also be prohibited without a license from that country. Please call an NEC sales

representative.

License not needed:

PD78F0124, 78F0124(A)

The customer must judge the need for a license:

PD780121, 780122, 780123, 780124, 780121(A), 780122(A),

780123(A), 780124(A), 780121(A1), 780122(A1), 780123(A1),

780124(A1)

• The information contained in this document is being issued in advance of the production cycle for the

device. The parameters for the device may change before final production or NEC Corporation, at its own

discretion, may withdraw the device prior to its production.

• Not all devices/types available in every country. Please check with local NEC representative for availability

and additional information.

• No part of this document may be copied or reproduced in any form or by any means without the prior written

consent of NEC Corporation. NEC Corporation assumes no responsibility for any errors which may appear in

this document.

• NEC Corporation does not assume any liability for infringement of patents, copyrights or other intellectual property

rights of third parties by or arising from use of a device described herein or any other liability arising from use

of such device. No license, either express, implied or otherwise, is granted under any patents, copyrights or other

intellectual property rights of NEC Corporation or others.

• Descriptions of circuits, software, and other related information in this document are provided for illustrative

purposes in semiconductor product operation and application examples. The incorporation of these circuits,

software, and information in the design of the customer's equipment shall be done under the full responsibility

of the customer. NEC Corporation assumes no responsibility for any losses incurred by the customer or third

parties arising from the use of these circuits, software, and information.

• While NEC Corporation has been making continuous effort to enhance the reliability of its semiconductor devices,

the possibility of defects cannot be eliminated entirely. To minimize risks of damage or injury to persons or

property arising from a defect in an NEC semiconductor device, customers must incorporate sufficient safety

measures in its design, such as redundancy, fire-containment, and anti-failure features.

• NEC devices are classified into the following three quality grades:

"Standard", "Special", and "Specific". The Specific quality grade applies only to devices developed based on a

customer designated "quality assurance program" for a specific application. The recommended applications of

a device depend on its quality grade, as indicated below. Customers must check the quality grade of each device

before using it in a particular application.

Standard: Computers, office equipment, communications equipment, test and measurement equipment,

audio and visual equipment, home electronic appliances, machine tools, personal electronic

equipment and industrial robots

Special: Transportation equipment (automobiles, trains, ships, etc.), traffic control systems, anti-disaster

systems, anti-crime systems, safety equipment and medical equipment (not specifically designed

for life support)

Specific: Aircraft, aerospace equipment, submersible repeaters, nuclear reactor control systems, life

support systems or medical equipment for life support, etc.

The quality grade of NEC devices is "Standard" unless otherwise specified in NEC's Data Sheets or Data Books.

If customers intend to use NEC devices for applications other than those specified for Standard quality grade,

they should contact an NEC sales representative in advance.

M5D 98. 12

Preliminary User’s Manual U16315EJ1V0UD 5

Regional Information

Some information contained in this document may vary from country to country. Before using any NEC

product in your application, pIease contact the NEC office in your country to obtain a list of authorized

representatives and distributors. They will verify:

• Device availability

• Ordering information

• Product release schedule

• Availability of related technical literature

• Development environment specifications (for example, specifications for third-party tools and

components, host computers, power plugs, AC supply voltages, and so forth)

• Network requirements

In addition, trademarks, registered trademarks, export restrictions, and other legal issues may also vary

from country to country.

NEC Electronics Inc. (U.S.)

Santa Clara, California

Tel: 408-588-6000

800-366-9782

Fax: 408-588-6130

800-729-9288

NEC Electronics Hong Kong Ltd.

Hong Kong

Tel: 2886-9318

Fax: 2886-9022/9044

NEC Electronics Hong Kong Ltd.

Seoul Branch

Seoul, Korea

Tel: 02-528-0303

Fax: 02-528-4411

NEC Electronics Shanghai, Ltd.

Shanghai, P.R. China

Tel: 021-6841-1138

Fax: 021-6841-1137

NEC Electronics Taiwan Ltd.

Taipei, Taiwan

Tel: 02-2719-2377

Fax: 02-2719-5951

NEC Electronics Singapore Pte. Ltd.

Novena Square, Singapore

Tel: 253-8311

Fax: 250-3583

NEC do Brasil S.A.

Electron Devices Division

Guarulhos-SP, Brasil

Tel: 11-6462-6810

Fax: 11-6462-6829

J02.4

NEC Electronics (Europe) GmbH

Duesseldorf, Germany

Tel: 0211-65 03 01

Fax: 0211-65 03 327

•Sucursal en España

Madrid, Spain

Tel: 091-504 27 87

Fax: 091-504 28 60

Vélizy-Villacoublay, France

Tel: 01-30-67 58 00

Fax: 01-30-67 58 99

•Succursale Française

•Filiale Italiana

Milano, Italy

Tel: 02-66 75 41

Fax: 02-66 75 42 99

•Branch The Netherlands

Eindhoven, The Netherlands

Tel: 040-244 58 45

Fax: 040-244 45 80

•Branch Sweden

Taeby, Sweden

Tel: 08-63 80 820

Fax: 08-63 80 388

•United Kingdom Branch

Milton Keynes, UK

Tel: 01908-691-133

Fax: 01908-670-290

Preliminary User’s Manual U16315EJ1V0UD

INTRODUCTION

Readers This manual is intended for user engineers who wish to understand the functions of the

78K0/KD1 Series and design and develop application systems and programs for these

devices.

The target products are as follows.

78K0/KD1 Series:

PD780121, 780122, 780123, 780124, 78F0124, 780121(A),

780122(A), 780123(A), 780124(A), 78F0124(A), 780121(A1),

780122(A1), 780123(A1), 780124(A1)

Purpose This manual is intended to give users an understanding of the functions described in the

Organization below.

Organization The 78K0/KD1 Series manual is separated into two parts: this manual and the

instructions edition (common to the 78K/0 Series).

78K0/KD1

User’s Manual

(This Manual)

78K/0 Series

User’s Manual

Instructions

•Pin functions

•Internal block functions

•Interrupts

•Other on-chip peripheral functions

•Electrical specifications (target values)

•CPU functions

•Instruction set

•Explanation of each instruction

Preliminary User’s Manual U16315EJ1V0UD 7

How to Read This Manual It is assumed that the readers of this manual have general knowledge of electrical

engineering, logic circuits, and microcontrollers.

•When using this manual as the manual for (A) products and (A1) products:

→Only the quality grade differs between standard products and (A) and (A1)

products. Read the part number as follows.

•

PD780121 →

PD780121(A), 780121(A1)

•

PD780122 →

PD780122(A), 780122(A1)

•

PD780123 →

PD780123(A), 780123(A1)

•

PD780124 →

PD780124(A), 780124(A1)

•

PD78F0124 →

PD78F0124(A)

•To gain a general understanding of functions:

→Read this manual in the order of the CONTENTS.

•How to interpret the register format:

→For a bit number enclosed in square, the bit name is defined as a reserved word

in the assembler, and is already defined in the header file named sfrbit.h in the C

compiler.

•To check the details of a register when you know the register name:

→Refer to APPENDIX C REGISTER INDEX.

•To know details of the 78K/0 Series instructions:

→Refer to the separate document 78K/0 Series Instructions User’s Manual

(U12326E).

Caution Examples in this manual employ the “standard” quality grade for

general electronics. When using examples in this manual for the

“special” quality grade, review the quality grade of each part and/or

circuit actually used.

Conventions Data significance: Higher digits on the left and lower digits on the right

Active low representations: ××× (overscore over pin and signal name)

Note: Footnote for item marked with Note in the text

Caution: Information requiring particular attention

Remark: Supplementary information

Numerical representations: Binary ... ×××× or ××××B

Decimal ... ××××

Hexadecimal ... ××××H

Preliminary User’s Manual U16315EJ1V0UD

Related Documents The related documents indicated in this publication may include preliminary versions.

However, preliminary versions are not marked as such.

Documents Related to Devices

Document Name Document No.

78K0/KD1 User’s Manual This manual

78K/0 Series Instructions User’s Manual U12326E

Documents Related to Development Tools (Software) (User’s Manuals)

Document Name Document No.

Operation U14445E

Language U14446E

RA78K0 Assembler Package

Structured Assembly Language U11789E

Operation U14297ECC78K0 C Compiler

Language U14298E

Operation (WindowsTM Based) U15373ESM78K Series System Simulator Ver. 2.30 or Later

External Part User Open Interface

Specifications

U15802E

ID78K Series Integrated Debugger Ver. 2.30 or Later Operation (Windows Based) U15185E

Fundamentals U11537ERX78K0 Real-Time OS

Installation U11536E

Project Manager Ver. 3.12 or Later (Windows Based) U14610E

Documents Related to Development Tools (Hardware) (User’s Manuals)

Document Name Document No.

IE-78K0-NS In-Circuit Emulator U13731E

IE-78K0-NS-A In-Circuit Emulator U14889E

IE-780148-NS-EM1 Emulation Board To be prepared

Documents Related to Flash Memory Programming

Document Name Document No.

PG-FP3 Flash Memory Programmer User’s Manual U13502E

PG-FP4 Flash Memory Programmer User’s Manual U15260E

Other Documents

Document Name Document No.

SEMICONDUCTOR SELECTION GUIDE −Product & Packages −X13769E

Semiconductor Device Mounting Technology Manual C10535E

Quality Grades on NEC Semiconductor Devices C11531E

NEC Semiconductor Device Reliability/Quality Control System C10983E

Guide to Prevent Damage for Semiconductor Devices by Electrostatic Discharge (ESD) C11892E

Caution The related documents listed above are subject to change without notice. Be sure to use the latest

version of each document when designing.

Preliminary User’s Manual U16315EJ1V0UD 9

CONTENTS

CHAPTER 1 OUTLINE .............................................................................................................................25

1.1 Features .......................................................................................................................................25

1.2 Applications.................................................................................................................................26

1.3 Ordering Information ..................................................................................................................27

1.4 Pin Configuration (Top View).....................................................................................................29

1.5 78K0/Kxx Series Lineup .............................................................................................................31

1.6 Block Diagram .............................................................................................................................33

1.7 Outline of Functions ...................................................................................................................34

CHAPTER 2 PIN FUNCTIONS ................................................................................................................36

2.1 Pin Function List .........................................................................................................................36

2.2 Description of Pin Functions .....................................................................................................39

2.2.1 P00 to P03 (port 0) .........................................................................................................................39

2.2.2 P10 to P17 (port 1) .........................................................................................................................39

2.2.3 P20 to P27 (port 2) .........................................................................................................................40

2.2.4 P30 to P33 (port 3) .........................................................................................................................40

2.2.5 P60 to P63 (port 6) .........................................................................................................................40

2.2.6 P70 to P77 (port 7) .........................................................................................................................40

2.2.7 P120 (port 12).................................................................................................................................41

2.2.8 P130 (port 13).................................................................................................................................41

2.2.9 P140 (port 14).................................................................................................................................41

2.2.10 AVREF .............................................................................................................................................41

2.2.11 AVSS ..............................................................................................................................................41

2.2.12 RESET ...........................................................................................................................................42

2.2.13 REGC .............................................................................................................................................42

2.2.14 X1 and X2.......................................................................................................................................42

2.2.15 XT1 and XT2 ..................................................................................................................................42

2.2.16 VDD and EVDD ................................................................................................................................42

2.2.17 VSS and EVSS .................................................................................................................................42

2.2.18 VPP (flash memory versions only) ...................................................................................................42

2.2.19 IC (mask ROM versions only).........................................................................................................42

2.3 Pin I/O Circuits and Recommended Connection of Unused Pins..........................................43

CHAPTER 3 CPU ARCHITECTURE .......................................................................................................46

3.1 Memory Space.............................................................................................................................46

3.1.1 Internal program memory space.....................................................................................................52

3.1.2 Internal data memory space ...........................................................................................................53

3.1.3 Special function register (SFR) area...............................................................................................53

3.1.4 Data memory addressing ...............................................................................................................54

3.2 Processor Registers ...................................................................................................................59

3.2.1 Control registers .............................................................................................................................59

3.2.2 General-purpose registers..............................................................................................................62

3.2.3 Special Function Registers (SFRs).................................................................................................63

3.3 Instruction Address Addressing ...............................................................................................67

3.3.1 Relative addressing ........................................................................................................................67

Preliminary User’s Manual U16315EJ1V0UD

3.3.2 Immediate addressing ................................................................................................................... 68

3.3.3 Table indirect addressing............................................................................................................... 69

3.3.4 Register addressing....................................................................................................................... 69

3.4 Operand Address Addressing .................................................................................................. 70

3.4.1 Implied addressing......................................................................................................................... 70

3.4.2 Register addressing....................................................................................................................... 71

3.4.3 Direct addressing........................................................................................................................... 72

3.4.4 Short direct addressing.................................................................................................................. 73

3.4.5 Special function register (SFR) addressing ................................................................................... 74

3.4.6 Register indirect addressing .......................................................................................................... 75

3.4.7 Based addressing .......................................................................................................................... 76

3.4.8 Based indexed addressing ............................................................................................................ 77

3.4.9 Stack addressing ........................................................................................................................... 77

CHAPTER 4 PORT FUNCTIONS ........................................................................................................... 78

4.1 Port Functions ............................................................................................................................ 78

4.2 Port Configuration...................................................................................................................... 80

4.2.1 Port 0 ............................................................................................................................................. 81

4.2.2 Port 1 ............................................................................................................................................. 84

4.2.3 Port 2 ............................................................................................................................................. 90

4.2.4 Port 3 ............................................................................................................................................. 91

4.2.5 Port 6 ............................................................................................................................................. 93

4.2.6 Port 7 ............................................................................................................................................. 94

4.2.7 Port 12 ........................................................................................................................................... 95

4.2.8 Port 13 ........................................................................................................................................... 96

4.2.9 Port 14 ........................................................................................................................................... 97

4.3 Registers Controlling Port Function ........................................................................................ 98

4.4 Port Function Operations........................................................................................................ 102

4.4.1 Writing to I/O port......................................................................................................................... 102

4.4.2 Reading from I/O port .................................................................................................................. 102

4.4.3 Operations on I/O port ................................................................................................................. 102

CHAPTER 5 CLOCK GENERATOR .................................................................................................... 103

5.1 Functions of Clock Generator................................................................................................. 103

5.2 Configuration of Clock Generator .......................................................................................... 104

5.3 Registers Controlling Clock Generator.................................................................................. 105

5.4 System Clock Oscillator .......................................................................................................... 112

5.4.1 X1 oscillator ................................................................................................................................. 112

5.4.2 Subsystem clock oscillator........................................................................................................... 112

5.4.3 When subsystem clock is not used.............................................................................................. 115

5.4.4 Ring-OSC oscillator ..................................................................................................................... 115

5.4.5 Prescaler ..................................................................................................................................... 115

5.5 Clock Generator Operation ..................................................................................................... 115

5.6 Time Required to Switch Between Ring-OSC Clock and X1 Input Clock........................... 122

5.7 Changing System Clock and CPU Clock Settings................................................................ 123

5.7.1 Time required for switching between system clock and CPU clock ............................................. 123

5.8 Clock Switching Flowchart and Register Setting ................................................................. 124

5.8.1 Switching from Ring-OSC clock to X1 input clock........................................................................ 124

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