NXP Semiconductors FRDM665SPIEVB Bedienungsanleitung
UM11734
Hardware user manual for FRDM665SPIEVB
Rev. 1 — 18 May 2022 User manual
Document information
Information Content
Keywords MC33665A, SPI, dual SPI, BMS gateway IC
Abstract User manual for starting work with MC33665A SPI EVB.
NXP Semiconductors UM11734
Hardware user manual for FRDM665SPIEVB
Rev Date Description
1 20220518 initial version
Revision history
UM11734 All information provided in this document is subject to legal disclaimers. © NXP B.V. 2022. All rights reserved.
User manual Rev. 1 — 18 May 2022
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NXP Semiconductors UM11734
Hardware user manual for FRDM665SPIEVB
IMPORTANT NOTICE
For engineering development or evaluation purposes only
NXP provides the product under the following conditions:
This evaluation kit is for use of ENGINEERING DEVELOPMENT OR
EVALUATION PURPOSES ONLY. It is provided as a sample IC pre-soldered
to a printed-circuit board to make it easier to access inputs, outputs and
supply terminals. This evaluation board may be used with any development
system or other source of I/O signals by connecting it to the host MCU
computer board via off-the-shelf cables. This evaluation board is not
a Reference Design and is not intended to represent a final design
recommendation for any particular application. Final device in an application
heavily depends on proper printed-circuit board layout and heat sinking
design as well as attention to supply filtering, transient suppression, and I/O
signal quality.
The product provided may not be complete in terms of required design,
marketing, and or manufacturing related protective considerations, including
product safety measures typically found in the end device incorporating the
product. Due to the open construction of the product, it is the responsibility of
the user to take all appropriate precautions for electric discharge. In order to
minimize risks associated with the customers’ applications, adequate design
and operating safeguards must be provided by the customer to minimize
inherent or procedural hazards. For any safety concerns, contact NXP sales
and technical support services.
UM11734 All information provided in this document is subject to legal disclaimers. © NXP B.V. 2022. All rights reserved.
User manual Rev. 1 — 18 May 2022
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NXP Semiconductors UM11734
Hardware user manual for FRDM665SPIEVB
1 Introduction
The NXP analog product development boards provide an easy-to-use platform for
evaluating NXP products. The boards support a range of analog, mixed-signal, and
power solutions. They incorporate monolithic integrated circuits and system-in-package
devices that use proven, high-volume technology. NXP products offer longer battery life,
a smaller form factor, reduced component counts, lower cost, and improved performance
in powering state-of-the-art systems.
This page guides the user through the process of setting up and using the MC33665A
serial peripheral interface (SPI) evaluation board (EVB).
1.1 Kit contents
The FRDM665SPIEVB kit includes:
•MC33665A SPI EVB, SPI to four transformer physical layer (TPL) interface EVB
•Two TPL daisy chain cables; two-wire twisted-pair daisy chain interface cable
•Quick Start Guide
1.2 Additional hardware
In addition to the kit contents, the following hardware is necessary or beneficial:
•External dual power supply 10 V to 18 V/2 A (optional)
•EVBs of battery cell controller (BCC) devices from NXP
•S32K344EVB-Q172 evaluation and development board for S32K344 from NXP
•14-cell battery pack or a battery emulator, such as BATT-14CEMULATOR
2 Getting to know the hardware
2.1 Board overview
The FRDM665SPIEVB serves as a hardware evaluation tool in support of the MC33665A
device of NXP. The MC33665A is a gateway router that can route TPL messages from
a microcontroller to four different TPL ports. It is designed for use in both automotive
and industrial applications. The device can route both TPL2 and TPL3 messages.
FRDM665SPIEVB is an ideal board for rapid prototyping of MC33665A for SPI interface
to MCU.
FRDM665SPIEVB supports an SPI for both requests (REQ) and responses (RSP).
Differential communication to daisy chain devices can be established with four different
ports.
2.2 Board features
The main features of FRDM665SPIEVB are:
•Request SPI
•Response SPI
•Onboard analog termination for daisy chain communication to BCC devices
•Configurable VIO voltage
•Configurable VDD5V from internal and external supply
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NXP Semiconductors UM11734
Hardware user manual for FRDM665SPIEVB
•DIP switch for configuring the SPI of MC33665A to operate with or without crystals
•Reset switch for the device and board
•LED display for the status of power
•Connectors to interface directly with S32K344EVB launchpad
•Connectors for external interface to general-purpose input/output (GPIO) and I2C-bus
2.3 Block diagram
aaa-044811
REQUEST
SPI
VDDIO
CFG0, CFG1
ID0 to ID3
DIP switch
3V3LDO
J13 J8
SW1
J1
D8
RESPONSE
SPI
TPL
PORT 0
LDO
MC33665A
POWER MANAGEMENT
GPIO, CONFIG AND
STATUS PINS
P
ORT
0
RE
Q
S
P
I
RES SPI
TPL
PORT 1
PORT 1
TPL
PORT 2
PORT 2
TPL
PORT 3
reset
switch
PORT 3
VBAT
KL30/
12 V/T30
VDD5V
VREG
VDDC/VDDD
VDD5V
VREG
VREG
EXT5V
5V_S32K
VIO_S32K
external interface
for GPIO and
status signals
Figure 1. FRDM665SPIEVB block diagram
2.4 Board description
The FRDM665SPIEVB allows the user to prototype and test all functions of the
MC33665A gateway router.
It can be stacked directly on the S32K344EVB. Different modes of SPI communication
can be established with MC33665A from K1 to K6 connectors. The FRDM665SPIEVB
can be supplied with 12 V at J6 connector or it can be powered directly from
S32K344EVB or EXT5V at J11. VDDC and VDDD can be selected by bridging one of the
positons in jumper J8 (Table 7) to select the 5 V. Bridging options jumper at J13 (Table 8)
makes it possible to select the VIO voltage of 3.3 V or 5 V or VIO of S32K344EVB.
S32K344EVB can be supplied with USB connection when connected to a PC.
SPI interface to external controller boards can be done with J7 for REQ SPI and J16
for RSP SPI. Do note to check the VIO of external controller board to be same as VIO
selected with jumper J13. Single SPI or dual SPI modes can be selected by using
jumpers at J14. Populating all jumpers at J14 enables single SPI mode and depopulates
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NXP Semiconductors UM11734
Hardware user manual for FRDM665SPIEVB
jumpers at J14 for dual SPI mode. SW2 DIP switch can be used to select the CFG and
ID configuration for MC33665A. BCC devices can be connected to daisy chain ports 0 to
3 via connectors J5, J12, J17, and J18.
Connector J1 gives the option to access the GPIO and I2C-bus pins of MC33665A.
Contact the NXP engineering team for using TPL autowake function in
FRDM665SPIEVB.
Figure 2. SPI EVB description
Power configuration of the board can be reflected by LEDs populated on board. LEDs
glow on board reflects the right power interface connected to FRDM665SPIEVB.
LED VBAT 12 V External 5 V S32K344EVB
D13 - red X - -
D14 - green X X X
D15 - green X X X
D16 - red X - -
Table 1. Power status LEDs
2.5 Connectors
FRDM665SPIEVB has multiple connectors for interfacing to MCU, internal GPIO, and
external BCC devices.
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Hardware user manual for FRDM665SPIEVB
Figure 3. FRDM665SPIEVB connectors
Pin configuration of connectors is shown in Table 2 to Table 15.
Pin number Connection Description
1 VBAT connection to 12 V
2 - not connected
3 - not connected
4 GND ground connection for MC33665A and interface boards
Table 2. Power connector - J6
Pin number Connection Description
1 GPIO0 interface to GPIO0 or INT0 for MC33665A
2 GPIO1 interface to GPIO1 or INT1 for MC33665A
3 GPIO2 interface to GPIO2 or INT2 for MC33665A
4 GPIO3 interface to GPIO3 or INT3 for MC33665A
5 GPIO4 interface to GPIO4 or I2C-bus in MC33665A
6 GPIO5 interface to GPIO5 or I2C-bus in MC33665A
7 GPIO6 interface to GPIO6 or SYNC in MC33665A
8 GPIO7 interface to GPIO7 or HOLD in MC33665A
9 VSS/GND ground
10 VDD5V 5 V supply line
11 VSS/GND ground
12 VIO VIO interface for MC33665A
13 - not connected
14 - not connected
Table 3. GPIO and interface - J1
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NXP Semiconductors UM11734
Hardware user manual for FRDM665SPIEVB
Pin number Connection Description
15 NC-SDAT_RSP_TXD connect R6 to interface SDAT_RSP_TXD of MC33665A
16 NC-SDAT_REQ_RXD connect R7 to interface SDAT_REQ_RXD of MC33665A
17 STB_N_OUT inverted standby signal from MC33665A
18 STB_OUT standby signal from MC33665A
19 RESET reset signal for MC33665A
20 VDD5V 5 V supply line
Table 3. GPIO and interface - J1...continued
Pin number Connection Description
1 SPI_RESP_CS chip select for response SPI
2 GND ground
3 SPI_RESP_CLK clock interface for response SPI
4 GND ground
5 SPI_RESP_SIN response TXD of MC33665A
6 GND ground
7 - not connected
8 GND ground
Table 4. Response SPI - J16
Pin number Connection Description
1 SPI_REQ_CS chip select for request SPI
2 GND ground
3 SPI_REQ_SCK clock interface for request SPI
4 GND ground
5 SPI_REQ_SIN response TXD of MC33665A; interfaced to MC33665A by shorting jumper pin 1
and pin 2 in J14
6 GND ground
7 SPI_REQ_SOUT request RXD of MC33665A
8 GND ground
Table 5. Request SPI - J7
Pin number Connection Description
1 EXT5V external 5 V supply
2 VSS/GND ground
Table 6. External 5 V - J11
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NXP Semiconductors UM11734
Hardware user manual for FRDM665SPIEVB
Pin number Connection Description
1-2 5V-S32K344EVB connection of 5 V from S32K344EVB to MC33665A SPI EVB; functional only
when FRDM665SPIEVB is used with S32K344 stackable EVB
3-4 VREG 5 V generated by VREG is connected to VDD5V. Note: It needs an external
12 V connection to VBAT with J6.
5-6 EXT5V external 5 V supply connected to J11 is selected for EXT5V
Table 7. VDD5V jumper - J8
Pin number Connection Description
1-2 VREG connects constant 5 V generated by VREG to VDDIO/VIO of MC33665A
3-4 VIO-S32K connects VIO preselected in S32K344EVB to MC33665A
5-6 3V3LDO connects constant 3.3 V generated by low dropout (LDO) to VDDIO/VIO of
MC33665A
Table 8. VIO jumper - J13
Pin number Connection Description
1-2 SDAT_RSP_TXD bridge SDAT_RSP_TXD for single SPI mode
3-4 SCLK_RSP bridge SCLK_RSP with SCLK_REQ for single SPI mode
5-6 CSN_RSP bridge CSN_RSP with CSN_REQ for single SPI mode
Table 9. Single SPI jumper - J14
Pin number Connection Description
1 HOLD interface to MC33665A GPIO7
3 SYNC interface to MC33665A GPIO6
5 GPIO5 interface to MC33665A GPIO5
7 GPIO4 interface to MC33665A GPIO4
9 GPIO3 interface to MC33665A GPIO3
11 GPIO2 interface to MC33665A GPIO2
13 GPIO1 interface to MC33665A GPIO1
15 GPIO0 interface to MC33665A GPIO0
Other - not connected
Table 10. S32K344EVB connector - K1
Pin number Connection Description
1 STB_OUT interface to MC33665A standby signal STB_OUT
5 CSN_RSP interface to MC33665A CSN_RSP
7 SDAT_REQ_RXD interface to MC33665A request RXD
Table 11. S32K344EVB connector - K2
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Hardware user manual for FRDM665SPIEVB
Pin number Connection Description
9 SDAT_RSP_TXD interface to MC33665A response TXD
11 SCLK_RSP interface to MC33665A response clock
17 RESET interface to MC33665A RESET signal
19 WAKE_IN interface to MC33665A WAKE_IN signal
Other - not connected
Table 11. S32K344EVB connector - K2...continued
Pin number Connection Description
3 VIO-S32K preselected VIO from S32K344EVB
9 5V-S32K 5 V power rail from S32K344EVB
11 VSS ground
13 VSS ground
Other - not connected
Table 12. S32K344EVB connector - K3
Pin number Connection Description
7 SCLK_REQ request clock signal to MC33665A
13 SDAT_REQ_RXD request RXD signal to MC33665A
15 CSN_REQ request CSN to MC33665A
Other - not connected
Table 13. S32K344EVB connector - K4
Pin number Connection Description
12 VSS ground
Other - not connected
Table 14. S32K344EVB connector - K5
Pin number Connection Description
5 SDAT_RSP_TXD response signal from MC33665A
•Must disable pin of S32K344 in SPI mode
•Only functional for universal asynchronous receiver transmitter (UART) EVB
7 SDAT_REQ_RXD request signal to MC33665A
•Must disable pin of S32K344
•Only functional for UART EVB
12 VSS ground
Other - not connected
Table 15. S32K344EVB connector - K6
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