onsemi NCD57253GEVB Bedienungsanleitung
EVAL BOARD USER’S MANUAL
www.onsemi.com
©Semiconductor Components Industries, LLC, 2020
December, 2021 −Rev. 0
1Publication Order Number:
EVBUM2797/D
NCD57253 Evaluation Board
User Manual
NCD57253GEVB
INTRODUCTION
The NCD57253 Evaluation driver board is designed for evaluation
of the NCD57253.
The NCD57253 is a high current two channel gate driver. It can
directly drive two independent MOFETs in any configuration.
The driver provides 5 kVrms internal galvanic isolation from input
to each output and functional isolation between the two output
channels. The device accepts 3.3 V to 20 V bias voltage and signal
levels on the input side and up to 32 V bias voltage on the output side.
The device accepts complementary inputs and offers separate pins for
Disable and Dead Time control for system design convenience.
NCD57253 is available in wide body SOIC−16 package.
DESCRIPTION
The board was created for the ability to verify and test the datasheet
parameters. The board can be externally connected to a power device
to verify real parameters in the system. It contains all the necessary
peripheral components for direct connection to the power devices. The
input bias is configured so the VDDA and VDDB can be powered by
using many types of integrated dc−dc power supplies or can be
powered directly from external power source. The PCB design is
optimized to reduce loop areas and provide clear and simple
measurement of all signals. All the parts (except optional dc−dc
sources) are TOP mounted which allows easy replacement and can
serve as an ideal reference design for future use.
Features
•High Peak Output Current (+8 A/−8A)
•Configurable as a Dual Low−Side or Dual High−Side or Half−Bridge
Driver
•Programmable Overlap or Dead Time control
•Disable Pin to Turn Off Outputs for Power Sequencing
•ANB Function to Offer Flexibility to Set up the Driver as
Half−bridge Driver Operating with a Single Input Signal
•MOSFET Gate Clamping during Short Circuit
•Short Propagation Delays with Accurate Matching
•Tight UVLO Thresholds on all Power Supplies
•3.3 V, 5 V, and 15 V Logic Input
•5 kVrms Galvanic Isolation from Input to each Output and 1.5 kV
Peak Differential Voltage between Output Channels
•1200 V Working Voltage (per VDE0884−11 Requirements)
•High Common Mode Transient Immunity
•High Electromagnetic Immunity
•This Device is Pb−Free, Halogen Free/BFR Free and is RoHS
Compliant
•Non−inverting Output Signals
Figure 1. Evaluation Board TOP View
•PCB layout optimized for power supply
bypassing capacitor, gate−driver loop
•Allows quick verification of most of the
data sheet parameters
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PIN Description
Table 1. EVALUATION BOARD PIN DESCRIPTION
Pin Name Pin Number Description
INA 17, 24 Channel A input signal
INB 15, 26 Channel B input signal
DIS 19, 22 Disable signal input (active High)
+5V 21, 20 Driver primary side power supply
VCC 23, 18 DC/DC sources alternative power supply (optional)
GND 25, 16 Primary side power/signal ground
VCCA 39, 40 A channel positive power supply
GNDA 37, 38 A channel Ground
VEEA 35, 36 A channel negative power supply
E−A33, 34 Source connection of A channel – connected to GNDA
G−A31, 32 Gate connector of A channel
VCCB 1, 2 B channel positive power supply
GNDB 3, 4 B channel Ground
VEEB 5, 6 B channel negative power supply
E−B7, 8 Source connection of B channel – connected to GNDB
G−B9, 10 Gate connection of B channel
ON−BOARD Jumpers Functional Table
Table 2. NCD57253 JUMPERS FUNCTIONAL TABLE
Jumper Name Setup Description
VIN SET OPEN When using external power supplies for VCCA / VCCB
Power supplies need to be connected to the VCCA, VCCB pins on P1
+5V When using dc−dc converter powered by the same voltage as the primary side of the driver
VCC pin on P1 can be unconnected
VCC When using dc−dc converter powered by different voltage as the primary side of the driver
Power supply for dc−dc converter need to be connected to the VCC pin on P1
ANB SET ON When complementary output signals need to be generated from a single input signal
OFF Output signals are in phase with input signals
DT SET DT Dead time and interlocking logic between INA and INB is defined by the value of the external
resistor (R7)
OFF Interlocking logic disabled, no dead time applied
FLOAT Dead time and interlocking logic between INA and INB are set internally to the minimum value
(see the datasheet)
B−IN SET INA When ANB SET is ON – both inputs are connected together
INB When ANB SET is OFF
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Electrical Specification
Table 3. NCD57253 ELECTRICAL SPECIFICATION
Description Min Typ Max Unit
VCCA/VCCB Output positive bias power supply (VCC−VEE max) 13 −36 V
VEE Output negative bias power supply 0− −20 V
GNDA / GNDB Output bias ground – connected to the MOSFET source − − −
+5V Input bias power supply (VDDI) 3.3 −22 V
GND Input bias signal and power ground − − −
DIS Disable signal input 0−VDDI V
VCC DC−DC sources optional power supply
(depended on dc−dc)
0− − V
TJOperating junction temperature range −40 −125 °C
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FUNCTIONAL DESCRIPTION
Power Supply (VCC, +5V, VCCA, VCCB)
NCD57253 is designed to support unipolar power supply
on both individual channels.
The evaluation driver board supports two types of output
side power supply:
•On board dc−dc converter.
♦Powered by a common source as the input side of
NCD57253.
♦Powered from external power pin VCC.
•External power supply.
The evaluation driver board is designed to support bipolar
power supply, this is achieved by creating a virtual ground
connected to the MOSFET source. If bipolar power supply
is not required, VEEA / VEEB pin should be connected to
the GNDA / GNDB.
For more detailed settings see the Table 2.
Figure 2. On Board DC−DC Power Converter Powered by a Common Power Source as the Input Side of the Driver
Figure 3. On Board DC−DC Power Converter Powered by a Different Power Source from the VCC Pin
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Figure 4. External Power Supply (No On Board DC−DC Converters)
Signal Inputs (INA, INB)
To prevent output pulse trimming, NCD57253 is
equipped by resettable input functionality.
This function is active when the UVLO or the DISABLE
function is detected.
OUTx will stay LOW until rising edge is detected on the
INx.
Signal Inputs Setup (ANB SET, DT SET)
Complementary Output Setup (ANB)
This function provides complementary signal output from
one PWM input signal on INA.
•Set ANB SET jumper to ON to activate the function,
B−IN jumper should be set to the INA to ensure proper
input signal rising edge reset after UVLO conditions have
disappeared or DISABLE has been deactivated.
•ANB SET should be set to OFF when G−A and G−B are
controlled individually by INA and INB (along with
DISABLE and DT).
Deadtime (DT)
The function provides complementary output signals with
defined deadtime based on the value of the external resistor
R7 (connected between DT pin and GND). The deadtime
can be estimated as tDT (ns) ≈10 x RDT (kW).
If minimum dead time is required, DT SET should remain
float (see Table 2).
•If DT SET is set to OFF, the deadtime control is disabled.
Outputs are controlled by inputs with respect to other
settings such as ANB SET, IN−B.
•If DT SET is set to DT, the deadtime control is active.
Outputs are controlled by inputs with added deadtime.
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TEST SPECIFICATION
This section provides details how to configure the
NCD57253 Evaluation board. Basic laboratory equipment
will be required to perform the tests.
Equipment
•Power supplies
♦3 pcs of DC power supplies providing minimally
25 V/1 A. (or 1 DC power supply + 2 pcs of dc−dc
converters ).
•Function generator
♦Two channel functional generator providing the
required testing frequency.
•Oscilloscope
♦Oscilloscope 2 channel (4 channel optional)
−Passive probes
Bench Test Setup
The bench test setup shows the equipment connections.
Use basic setup procedure as a reference:
•Make sure the power supplies & outputs of signal
generators are powered off / disabled
•Connect function generator to the INA and INB signal
inputs and GND
•Connect power supply positive lead to the +5 V
•Connect power supply negative lead to the GND
•Connect power supplies positive lead to the VCCA /
VCCB
•Connect power supply negative lead to the VEEA / VEEB
•(VEEA/VEEB shorted to the GNDA/GNDB if not used)
•Connect power supply ground lead to the GNDA / GNDB
•Connect oscilloscope probes to G−A, G−B output pins
Figure 5. Test Setup Diagram
Power Up
1. Before the power−up, verify the correct connection
of all signals and power leads
2. Enable power supply. Current consumption
depends on the chosen solution of the secondary
side power supply. When 5 V to +20 V/−5V
dc−dc converters are used, the current
consumption can be up to 300 mA
3. Enable function generator outputs
4. Check the signals at each outputs
Power Down
1. Disable functional generator outputs
2. Disable power supply
3. Disconnect equipment
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Test 1 – Typical Performance Waveforms – Propagation Delay
To set the board, use this setup as a reference.
Make sure the power supplies & outputs of signal generators are powered off / disabled channel
1. VIN SET
a. For powering outputs by using external power supplies −open jumper
b. For using 5 V dc−dc converter – Set jumper to 5 V
c. For using different input voltage dc−dc converter – Set jumper to VCC
i. External power supplies with appropriate voltage need to be connected to VCC pin
2. ANB SET – Set to OFF
3. DT SET – Set to OFF
4. B−IN SET – Set to INB
5. POWER UP the setup
(Legend: C1 – Input A (INA), C2 – Output A (G−A), C3 – Input B (INB), C4 – Output B (G−B))
Figure 6. INPUT and OUTPUT Rise Propagation Delay Waveforms
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Test 2 – Typical Performance Waveforms – Independent 2 Channels Driver
The NCD57253 can work as 2 independent channel driver.
To set the board as 2 independent channel driver, use this setup as a reference.
Make sure the power supplies & outputs of signal generators are powered off / disabled channel
1. VIN SET
a. For powering outputs by using external power supplies −open jumper
b. For using 5 V dc−dc converter – Set jumper to 5 V
c. For using different input voltage dc−dc converter – Set jumper to VCC
i. External power supplies with appropriate voltage need to be connected to VCC pin
2. ANB SET – Set to OFF
3. DT SET – Set to OFF
4. B−IN SET – Set to INB
5. POWER UP the setup
(Legend: C1 – Input A (INA), C2 – Output A (G−A), C3 – Input B (INB), C4 – Output B (G−B))
Figure 8. INPUT and OUTPUT Signals
(Input signals from the external signal generator are in phase)
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