Panasonic MN103SFX1K Bedienungsanleitung

1.1 Overview

The MN103S is a 32-bit micro controller combining ease of use intended for programs development in the C language

with a simple, high-performance architecture made possible through pursuit of cost performance.

Built around a compact 32-bit CPU with a basic instruction word length of 1 byte, this LSI includes internal memory for

instructions and data, a clock generator, bus controller, interrupt controller, watchdog timer, standard peripheral circuitry

such as timers and serial interfaces, PWM circuit best suited to controlling 3- phase motors, arithmetic unit for speed-up

of inverter control and analog circuits. (A/D converters and VGA (Variable Gain Amplifier)) for motor position control.

The MN103S Series high-speed CPU coupled with abundance of peripheral features provides an easy means of devel-

oping on LSI for motor and power control applications requiring fast response a feature previously unavailable with

conventional micro controllers.

MN103SFX1K/X2K/X3K/X5K/X6K/X7K

32-bit Single-chip Microcontroller

PubNo. 232X701-015E

Publication date: April 2018 1

1.2 Product Summary

This manual describes LSI in the following Table 1.2-1 .

Table 1.2-1 Product Summary

LSI ROM size RAM size Classification Package

MN103SFX7K / X3K 256 KB 12 KB Flash EEPROM ver-

sion

LQFP 100 pin

QFP 100 pin

MN103SFX6K / X2K 256 KB 12 KB Flash EEPROM ver-

sion

TQFP 80 pin

LQFP 80 pin

MN103SFX5K / X1K 256 KB 12 KB Flash EEPROM ver-

sion

TQFP 64 pin

This LSI's functions are listed in Table 1.2-2 .

Table 1.2-2 Functions list

Function MN103S

FX7K

MN103S

FX6K

MN103S

FX5K

MN103S

FX3K

MN103S

FX2K

MN103S

FX1K

Number of pins 100 80 64 100 80 64

General purpose ports I/O port 74 54 42 82 62 50

Input port 8 8 8 - - -

Special pin Power pin 10 10 8 10 10 8

Reset pin 1 1 1 1 1 1

Oscillation pin 2 2 2 2 2 2

On-board debugger pin 3 3 3 3 3 3

N.C. pin 2 2 - 2 2 -

Interrupt Internal factor 54 54 48 54 54 48

External interrupt 9 9 8 9 9 8

Watchdog Timer 1 1 1 1 1 1

8-bit Timer 12 12 12 12 12 12

16-bit Timer 6 6 4 6 6 4

Serial interface Clock synchronous/ UART 3 3 3 3 3 3

Complementary 3-phase PWM 2 2 2 2 2 2

10-bit A/D converter Number of units 3 3 3 3 3 3

Number of conversion channels 20 16 12 20 16 12

10-bit D/A converter 2 2 2 2 2 2

Variable Gain Amplifier 2 2 2 - - -

Comparator 2 2 2 2 2 2

MN103SFX1K/X2K/X3K/X5K/X6K/X7K

32-bit Single-chip Microcontroller

PubNo. 232X701-015E

Publication date: April 2018 2

1.3 Features

This LSI's features are described.

CPU (MN103S core)

Structure LOAD/STORE architecture with 5-stage pipeline

Minimum instruction execu-

tion cycle

13.9 ns (72 MHz)

(External oscillation frequency 8MHz, 9 multiplying)

Number of basic instruc-

tions

Number of addressing

modes

Basic instruction length 1 byte

Memory space Linear address space of 4 GB (for instructions / data)

Internal memory

Internal ROM capacity 256 KB (Flash Memory)

Sector size Large sector 32 KB (Total 224 KB)

Small sector 8 KB (Total 32 KB)

Internal RAM capacity 12 KB

Extended calculation function

Extended calculation in-

struction

High-speed multiplication, High-speed division, trigonometric function, absolute value,

square root, LPF, 3-phase/2-phase conversion, PI calculation

Product-sum operation of n-th degree, Saturate calculation

Clock generator

External oscillation (crystal/

ceramic)

4 to 16 MHz

Clock multiplying circuit

(PLL)

4 to 12 multiplying

Operation mode

CPU operation mode NORMAL mode

Standby mode SLEEP mode, HALT mode, STOP mode

Interrupt Controller

Internal interrupt Watchdog timer overflow, System error

Timer, Serial, PWM, A/D conversion

A/D conversion error detection, Comparator detection

External interrupt External interrupt pin input

Edge detection or Level detection can be selected

Reset function

Pin reset Control NRST pin from outside

Software reset Writing to register

Power supply detection reset Detection level: 3.6 V to 4.3 V

MN103SFX1K/X2K/X3K/X5K/X6K/X7K

32-bit Single-chip Microcontroller

PubNo. 232X701-015E

Publication date: April 2018 3

Reset function

Error detection reset Error detection by watchdog timer

Watchdog timer

Detection time 8.192 ms to 2097.15 ms (At External oscillation is 8 MHz.)

Function Non-maskable interrupt generates when 1st overflow is detected.

Forced-reset generates in LSI when 2nd overflow is detected.

8-bit timer

Function Interval timer, Timer pulse output, Event count, Baud rate timer, Cascade connection

16-bit timer

Function Interval timer, Event count, Up/Down count, Timer output, PWM output (Cycle varia-

ble, Pulse width variable), Input capture, One-shot output, Start trigger start, Generation

of Start trigger for A/D conversion

Serial interface 0 and 1

Communication mode Clock synchronous serial/ Full duplex UART

Clock synchronous serial Function Parity error detection, Overrun error detection, Specifica-

tion of First transfer bit, Selection of any transfer size

from 7 to 8 bits

Maximum transfer rate 3.0 Mbps

Full duplex UART Function Parity error detection, Overrun error detection, Framing

error detection, Specification of First transfer bit, Selec-

tion of any transfer size from 7 to 8 bits

Maximum transfer rate 375 kbps

Serial interface 2

Communication mode Clock synchronous serial/ Full duplex UART

Clock synchronous serial Function Overrun error detection, Specification of First transfer bit,

Selection of any transfer size from 2 to 8 bits

Maximum transfer rate 5.0 Mbps

Full duplex UART Function Parity error detection, Overrun error detection, Framing

error detection, Specification of First transfer bit, Selec-

tion of any transfer size from 7 to 8 bits

Maximum transfer rate 300 kbps

Complementary 3-phase PWM timer

Minimum resolution 13.9 ns

Function Triangular wave and saw-tooth wave output, dead time auto-insertion, double buffer up-

date, output protection circuit, output timing variable function

A/D converter

Resolution 10 bits

Number of channels Up to 20 channels in 3 units (There is the share channel.)

Function 16-bit timer, A/D conversion start in synchronization with PWM, Multiple channel con-

version, Conversion channel omitted function, Conversion result error detect function

MN103SFX1K/X2K/X3K/X5K/X6K/X7K

32-bit Single-chip Microcontroller

PubNo. 232X701-015E

Publication date: April 2018 4

D/A converter

Resolution 10 bits

Function Reference of the comparator

VGA (Variable Gain Amplifier)

Gain setting 2 to 20 times

Function Differential input, 3 channels for + side input can be switched (- side is fixed)

Comparator

Function Comparator output cooperates with PWM output. (Pin protection)

Internal flash memory

Rewritable times Large sector (32 KB) 1000 times (Minimum)

Small sector (8 KB) 100000 times (Minimum)

Data retention time 10 years

Package

100 pin LQFP (14 mm square, 0.5 mm pitch, halogen free)

100 pin QFP (18 mm square, 0.65 mm pitch)

80 pin TQFP (12 mm square, 0.5 mm pitch, halogen free)

80 pin LQFP (14 mm square, 0.65 mm pitch, halogen free)

64 pin TQFP (10 mm square, 0.5 mm pitch, halogen free)

* Panasonic "halogen free" semiconductor products refer to the products made of molding resin and interposer which

conform to the following standards.

- Bromine: 900 ppm (Maximum Concentration Value)

- Chlorine: 900 ppm (Maximum Concentration Value)

- Bromine + Chlorine: 1500 ppm (Maximum Concentration Value)

The above-mentioned standards are based on the numerical value described in IEC61249-2-21.

MN103SFX1K/X2K/X3K/X5K/X6K/X7K

32-bit Single-chip Microcontroller

PubNo. 232X701-015E

Publication date: April 2018 5

1.4 Pin

The specifications of pins in this LSI are described as follows.

•Pin configuration

•Pin function

1.4.1 Pin Configuration

Figure 1.4-1 to Figure 1.4-6 show the pin configuration.

P23/SBT1

P30/TM0IO

P57/NPWM02

P56/PWM02

P55/NPWM01

P53/NPWM00

P54/PWM01

MN103SFX7K

CMP1INA/VGA1P0/ADIN07/P97

AVDD50

EXTRG1/IRQ05/P11

CMP0OUT/IRQ06/P12

P27/SBI0

P26/SBT0

P25/SBO0

P24/SBI1

P22/SBO1

P21/SBI2

TM15IO/P85

P86

CMP0INB/ADIN05/P95

CMP1REFA/VGA1N/ADIN06/P96

AVSS

CMP0REFA/VGA0N/ADIN00/P90

DA0OUT/CMP0REFB/ADIN04/P94

IRQ01/P81

IRQ02/P82

IRQ03/P83

TM14IO/P84

LQFP 100pin 0.5mm pitch

P73/TM11IO1

P72/TM11IO0

TM11O5/P77

IRQ00/P80

VDD50

P75/TM11O3

P74/TM11O2

N.C.

VSS

TM11O4/P76

CMP0INA/VGA0P0/ADIN01/P91

VGA0P1/ADIN02/P92

P63/NPWM10

P66/PWM12

P65/NPWM11

P64/PWM11

P87

P60

VGA1P2/ADIN09/PA1

VGA1P1/ADIN08/PA0

P62/PWM10

P67/NPWM12

VGA0P2/ADIN03/P93

100

P46/TM10AIO

P52/PWM00

P51/TM7IO

P50/TM6IO

P47/TM10BIO

P61

P31/TM1IO

P40/TM9AO

P41/TM9BO

P45/TM10BO

P44/TM10AO

P43/TM9BIO

P42/TM9AIO

VSS

P36/TM8AIO

P32/TM2IO

DA1OUT/CMP1REFB/ADIN10/PA2

P17/SBO2

ADIN12/PA4

CMP1INB/ADIN11/PA3

P20/SBT2

P37/TM8BIO

P33/TM3IO

P35/TM5IO

VDD50

P34/TM4IO

ADIN18/PB2

ADIN13/PA5

ADIN14/PA6

ADIN15/PA7

ADIN16/PB0

VDD50

ADIN17/PB1

SCLK

SDATA

NBOOT

TM16IO/P15

TM17IO/P16

OSCI

NRST

ADIN19/PB3

OSCO

NTEST

VSS

CMP1OUT/IRQ07/P13

IRQ08/P14

N.C.

VOUT18

EXTRG0/IRQ04/P10

QFP 100pin 0.65 mm pitch

Figure 1.4-1 Pin Configuration of MN103SFX7K

MN103SFX1K/X2K/X3K/X5K/X6K/X7K

32-bit Single-chip Microcontroller

PubNo. 232X701-015E

Publication date: April 2018 6

CMP1OUT/IRQ07/P13

LQFP 80pin 0.65mm pitch

MN103SFX6K

N.C.

EXTRG0/IRQ04/P10

VOUT18

CMP0OUT/IRQ06/P12

ADIN13/PA5

ADIN14/PA6

ADIN15/PA7

SCLK

SDATA

NRST

NTEST

VDD50

EXTRG1/IRQ05/P11

IRQ08/P14

NBOOT

OSCO

OSCI

VSS

P27/SBI0

P22/SBO1

P23/SBT1

TM17IO/P16

DA1OUT/CMP1REFB/ADIN10/PA2

P17/SBO2ADIN12/PA4 4120

P21/SBI2

CMP1INB/ADIN11/PA3 P20/SBT2

4318

P33/TM3IO

P34/TM4IO

P25/SBO0

P24/SBI1

P26/SBT0

P37/TM8BIO

57 P36/TM8AIO

VSS

VDD50

P32/TM2IO

P31/TM1IO

P55/NPWM01

P54/PWM0166

P35/TM5IO

P43/TM9BIO60

P42/TM9AIO

P46/TM10AIO

P53/NPWM00

P52/PWM00

P51/TM7IO

P47/TM10BIO

P62/PWM10

VGA1P2/ADIN09/PA1

16VGA1P1/ADIN08/PA0

CMP1REFA/VGA1N/ADIN06/P96 14

CMP0INB/ADIN05/P95

TQFP 80pin 0.5mm pitch

CMP1INA/VGA1P0/ADIN07/P97

DA0OUT/CMP0REFB/ADIN04/P94

AVDD50

P56/PWM02

P65/NPWM11

P57/NPWM02

VGA0P2/ADIN03/P93

AVSS 10

2IRQ01/P81

IRQ02/P82

CMP0REFA/VGA0N/ADIN00/P90

CMP0INA/VGA0P0/ADIN01/P91

N.C.

VGA0P1/ADIN02/P92

VSS

VDD50

IRQ03/P83

TM15IO/P85

IRQ00/P80

P73/TM11IO1

P64/PWM11

P63/NPWM10

P72/TM11IO0

P67/NPWM12

P66/PWM12

Figure 1.4-2 Pin Configuration of MN103SFX6K

MN103SFX1K/X2K/X3K/X5K/X6K/X7K

32-bit Single-chip Microcontroller

PubNo. 232X701-015E

Publication date: April 2018 7

P65/NPWM11

MN103SFX5K

P20/SBT2

CMP1OUT/IRQ07/P13

P21/SBI2

P80/IRQ00

VSS

P66/PWM12

P67/NPWM12

VDD50

P54/PWM01

IRQ03/P83

IRQ01/P81

IRQ02/P82

CMP0REFA/VGA0N/ADIN00/P90

CMP0INA/VGA0P0/ADIN01/P91

DA0OUT/CMP0REFB/ADIN04/P94

CMP1REFA/VGA1N/ADIN06/P96

AVDD50

VGA0P1/ADIN02/P92

VGA0P2/ADIN03/P93

AVSS

DA1OUT/CMP1REFB/ADIN10/PA2

TQFP 64pin 0.5mm pitch

CMP0INB/ADIN05/P95

VGA1P2/ADIN09/PA1

CMP1INA/VGA1P0/ADIN07/P97

VGA1P1/ADIN08/PA0

P53/NPWM00

P56/PWM02

P55/NPWM01

P64/PWM11

P63/NPWM10

P62/PWM10

P57/NPWM02

48 P46/TM10AIO

P52/PWM00

P47/TM10BIO

CMP1INB/ADIN11/PA3

P35/TM5IO

P43/TM9BIO

P42/TM9AIO

P34/TM4IO

SCLK

SDATA

NBOOT

OSCO

OSCI

SBO2/P17

VSS

NTEST

VDD50

VOUT18

EXTRG0/IRQ04/P10

EXTRG1/IRQ05/P11

CMP0OUT/IRQ06/P12

NRST

P33/TM3IO

P32/TM2IO

P31/TM1IO

P27/SBI0

P22/SBO1

P23/SBT1

P24/SBI1

P26/SBT0

P25/SBO0

Figure 1.4-3 Pin Configuration of MN103SFX5K

MN103SFX1K/X2K/X3K/X5K/X6K/X7K

32-bit Single-chip Microcontroller

PubNo. 232X701-015E

Publication date: April 2018 8

NRST

CMP0OUT/IRQ06/P12

OSCO

NTEST

VSS

CMP1OUT/IRQ07/P13

IRQ08/P14

N.C.

VOUT18

EXTRG0/IRQ04/P10

EXTRG1/IRQ05/P11

TM16IO/P15

TM17IO/P16

OSCI

ADIN13/PA5

ADIN14/PA6

ADIN15/PA7

ADIN16/PB0

VDD50

ADIN17/PB1

SCLK

SDATA

NBOOT

ADIN19/PB3

VDD50

P34/TM4IO

ADIN18/PB2

P17/SBO2

ADIN12/PA4

P37/TM8BIO

P33/TM3IO

P35/TM5IO

P31/TM1IO

CMP1IN/ADIN11/PA3

P20/SBT2

DA1OUT/CMP1REF/ADIN10/PA2

ADIN09/PA1

VSS

P36/TM8AIO

P32/TM2IO

P61

P60

P40/TM9AO

P41/TM9BO

P45/TM10BO

P44/TM10AO

P43/TM9BIO

P42/TM9AIO

P46/TM10AIO

P52/PWM00

P51/TM7IO

P50/TM6IO

P47/TM10BIO

ADIN08/PA0

ADIN03/P93

100

P62/PWM10

P67/NPWM12

P63/NPWM10

P66/PWM12

P65/NPWM11

P64/PWM11

P87

AVSS

ADIN00/P90

ADIN01/P91

ADIN02/P92

TM11O4/P76

TM11O5/P77

IRQ00/P80

P73/TM11IO1

P72/TM11IO0

VDD50

P75/TM11O3

P74/TM11O2

N.C.

VSS

LQFP 100pin 0.5mm pitch

DA0OUT/CMP0REF/ADIN04/P94

IRQ01/P81

IRQ02/P82

IRQ03/P83

TM14IO/P84

TM15IO/P85

P86

P21/SBI2

P23/SBT1

CMP0IN/ADIN05/P95

ADIN06/P96

ADIN07/P97

AVDD50

P27/SBI0

P26/SBT0

P25/SBO0

P24/SBI1

P22/SBO1

P30/TM0IO

P57/NPWM02

P56/PWM02

P55/NPWM01

P53/NPWM00

P54/PWM01

MN103SFX3K

QFP 100pin 0.65 mm pitch

Figure 1.4-4 Pin Configuration of MN103SFX3K

MN103SFX1K/X2K/X3K/X5K/X6K/X7K

32-bit Single-chip Microcontroller

PubNo. 232X701-015E

Publication date: April 2018 9

LQFP 80pin 0.65mm pitch

P64/PWM11

P63/NPWM10

P72/TM11IO0

P67/NPWM12

P66/PWM12

N.C.

P73/TM11IO1

VSS

VDD50

IRQ03/P83

TM15IO/P85

IRQ00/P80

2IRQ01/P81

IRQ02/P82

ADIN00/P90

ADIN01/P91

ADIN02/P92

ADIN03/P93

ADIN07/P97

DA0OUT/CMP0REF/ADIN04/P94

AVDD50

CMP0IN/ADIN05/P95

16ADIN08/PA0

P56/PWM02

P65/NPWM11

P57/NPWM02

P62/PWM10

AVSS

ADIN06/P96

P46/TM10AIO

P53/NPWM00

P52/PWM00

P51/TM7IO

P47/TM10BIO

P55/NPWM01

P54/PWM01

P35/TM5IO

VSS

P43/TM9BIO60

P42/TM9AIO

P37/TM8BIO

P25/SBO0

P24/SBI1

57 P36/TM8AIO

VDD50

P23/SBT145

P33/TM3IO52

P26/SBT0

DA1OUT/CMP1REF/ADIN10/PA2

P22/SBO1

P21/SBI2

ADIN09/PA1

P17/SBO2ADIN12/PA4 4120

CMP1IN/ADIN11/PA3 P20/SBT242

P32/TM2IO

P31/TM1IO

P27/SBI0

P34/TM4IO

VSS

ADIN13/PA5

ADIN14/PA6

ADIN15/PA7

SCLK

NBOOT

OSCO

SDATA

NRST

TM17IO/P16

N.C.

35EXTRG1/IRQ05/P11

MN103SFX2K

IRQ08/P14

CMP0OUT/IRQ06/P12

CMP1OUT/IRQ07/P13

TQFP 80pin 0.5mm pitch

NTEST

VDD50

EXTRG0/IRQ04/P10

VOUT18

OSCI

Figure 1.4-5 Pin Configuration of MN103SFX2K

MN103SFX1K/X2K/X3K/X5K/X6K/X7K

32-bit Single-chip Microcontroller

PubNo. 232X701-015E

Publication date: April 2018 10

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