Philips LPC213 Series Bedienungsanleitung

UM10120

Volume 1: LPC213x User Manual

Rev. 01 — 24 June 2005 User manual

Document information

Info Content

Keywords LPC2131, LPC2132, LPC2134, LPC2136, LPC2138, LPC2000, LPC213x,

ARM, ARM7, embedded, 32-bit, microcontroller

Abstract An initial LPC213x User Manual revision

User manual Rev. 01 — 24 June 2005 2

Philips Semiconductors UM10120

Volume 1 LPC2131/2/4/6/8 UM

Contact information

For additional information, please visit: http://www.semiconductors.philips.com

For sales office addresses, please send an email to: sales.addresses@www.semiconductors.philips.com

Revision history

Rev Date Description

01 20050624 Initial version

User manual Rev. 01 — 24 June 2005 3

1.1 Introduction

The LPC2131/32/34/36/38 microcontrollers are based on a 16/32 bit ARM7TDMI-S™

CPU with real-time emulation and embedded trace support, that combines the

microcontroller with 32 kB, 64 kB, 128 kB, 256 kB and 512 kB of embedded high speed

Flash memory. A 128-bit wide memory interface and a unique accelerator architecture

enable 32-bit code execution at maximum clock rate. For critical code size applications,

the alternative 16-bit Thumb® Mode reduces code by more than 30 % with minimal

performance penalty.

Due to their tiny size and low power consumption, these microcontrollers are ideal for

applications where miniaturization is a key requirement, such as access control and

point-of-sale. With a wide range of serial communications interfaces and on-chip SRAM

options of 8/16/32 kB, they are very well suited for communication gateways and protocol

converters, soft modems, voice recognition and low end imaging, providing both large

buffer size and high processing power. Various 32-bit timers, single or dual 10-bit

8channel ADC(s), 10-bit DAC, PWM channels and 47 GPIO lines with up to nine edge or

level sensitive external interrupt pins make these microcontrollers particularly suitable for

industrial control and medical systems.

1.2 Features

•16/32-bit ARM7TDMI-S microcontroller in a tiny LQFP64 package

•8/16/32 kB of on-chip static RAM and 32/64/128/256/512 kB of on-chip Flash program

memory. 128 bit wide interface/accelerator enables high speed 60 MHz operation.

•In-System/In-Application Programming (ISP/IAP) via on-chip boot-loader software.

Single Flash sector or full chip erase in 400 ms and 256 bytes programming in 1 ms.

•EmbeddedICE®and Embedded Trace interfaces offer real-time debugging with the

on-chip RealMonitor™ software and high speed tracing of instruction execution.

•One (LPC2131/2) or two (LPC2134/6/8) 8 channel 10-bit A/D converters provide(s) a

total of up to 16 analog inputs, with conversion times as low as 2.44 µs per channel.

•Single 10-bit D/A converter provides variable analog output. (LPC2132/4/6/8 only).

•Two 32-bit timers/external event counters (with four capture and four compare

channels each), PWM unit (six outputs) and watchdog.

•Low power Real-time clock with independent power and dedicated 32 kHz clock input.

•Multiple serial interfaces including two UARTs (16C550), two Fast I2C (400 kbit/s),

SPI™ and SSP with buffering and variable data length capabilities.

•Vectored interrupt controller with configurable priorities and vector addresses.

UM10120

Chapter 1: General information

Rev. 01 — 24 June 2005 User manual

User manual Rev. 01 — 24 June 2005 4

Philips Semiconductors UM10120

Volume 1 Chapter 1: Introductory information

•Up to 47 of 5 V tolerant general purpose I/O pins in tiny LQFP64 package.

•Up to nine edge or level sensitive external interrupt pins available.

•60 MHz maximum CPU clock available from programmable on-chip Phase-Locked

Loop (PLL) with settling time of 100 µs.

•On-chip integrated oscillator operates with external crystal in range of 1 MHz to

30 MHz or with external oscillator from 1 MHz to 50 MHz.

•Power saving modes include Idle and Power-down.

•Individual enable/disable of peripheral functions as well as peripheral clock scaling

down for additional power optimization.

•Processor wake-up from Power-down mode via external interrupt or Real-time Clock.

•Single power supply chip with Power-On Reset (POR) and Brown-Out Detection

(BOD) circuits:

–CPU operating voltage range of 3.0 V to 3.6 V (3.3 V ± 10 %) with 5 V tolerant I/O

pads

1.3 Applications

•Industrial control

•Medical systems

•Access control

•Point-of-sale

•Communication gateway

•Embedded soft modem

•General purpose applications

1.4 Device information

Table 1: LPC2131/2132/2134/2136/2138 device information

Device Number of

pins On-chip

SRAM On-chip

FLASH Number of

10-bit ADC

channels

Number of

10-bit DAC

channels

Note

LPC2131 64 8 kB 32 kB 8 - -

LPC2132 64 16 kB 64 kB 8 1 -

LPC2134 64 16 kB 128 kB 16 1UART1 with full

modem interface

LPC2136 64 32 kB 256 kB 16 1UART1 with full

modem interface

LPC2138 64 32 kB 512 kB 16 1UART1 with full

modem interface

User manual Rev. 01 — 24 June 2005 5

Philips Semiconductors UM10120

Volume 1 Chapter 1: Introductory information

1.5 Architectural overview

The LPC2131/2/4/6/8 consists of an ARM7TDMI-S CPU with emulation support, the

ARM7 Local Bus for interface to on-chip memory controllers, the AMBA Advanced

High-performance Bus (AHB) for interface to the interrupt controller, and the VLSI

Peripheral Bus (VPB, a compatible superset of ARM’s AMBA Advanced Peripheral Bus)

for connection to on-chip peripheral functions. The LPC2131/2/4/6/8 configures the

ARM7TDMI-S processor in little-endian byte order.

AHB peripherals are allocated a 2 megabyte range of addresses at the very top of the

4gigabyte ARM memory space. Each AHB peripheral is allocated a 16 kB address space

within the AHB address space. LPC2131/2/4/6/8 peripheral functions (other than the

interrupt controller) are connected to the VPB bus. The AHB to VPB bridge interfaces the

VPB bus to the AHB bus. VPB peripherals are also allocated a 2 megabyte range of

addresses, beginning at the 3.5 gigabyte address point. Each VPB peripheral is allocated

a 16 kB address space within the VPB address space.

The connection of on-chip peripherals to device pins is controlled by a Pin Connect Block

(see chapter "Pin Connect Block" on page 73). This must be configured by software to fit

specific application requirements for the use of peripheral functions and pins.

1.6 ARM7TDMI-S processor

The ARM7TDMI-S is a general purpose 32-bit microprocessor, which offers high

performance and very low power consumption. The ARM architecture is based on

Reduced Instruction Set Computer (RISC) principles, and the instruction set and related

decode mechanism are much simpler than those of microprogrammed Complex

Instruction Set Computers. This simplicity results in a high instruction throughput and

impressive real-time interrupt response from a small and cost-effective processor core.

Pipeline techniques are employed so that all parts of the processing and memory systems

can operate continuously. Typically, while one instruction is being executed, its successor

is being decoded, and a third instruction is being fetched from memory.

The ARM7TDMI-S processor also employs a unique architectural strategy known as

THUMB, which makes it ideally suited to high-volume applications with memory

restrictions, or applications where code density is an issue.

The key idea behind THUMB is that of a super-reduced instruction set. Essentially, the

ARM7TDMI-S processor has two instruction sets:

•The standard 32-bit ARM instruction set.

•A 16-bit THUMB instruction set.

The THUMB set’s 16-bit instruction length allows it to approach twice the density of

standard ARM code while retaining most of the ARM’s performance advantage over a

traditional 16-bit processor using 16-bit registers. This is possible because THUMB code

operates on the same 32-bit register set as ARM code.

THUMB code is able to provide up to 65% of the code size of ARM, and 160% of the

performance of an equivalent ARM processor connected to a 16-bit memory system.

User manual Rev. 01 — 24 June 2005 6

Philips Semiconductors UM10120

Volume 1 Chapter 1: Introductory information

The ARM7TDMI-S processor is described in detail in the ARM7TDMI-S Datasheet that

can be found on official ARM website.

1.7 On-chip Flash memory system

The LPC2131/2/4/6/8 incorporates a 32, 64, 128, 256 and 512 kB Flash memory system

respectively. This memory may be used for both code and data storage. Programming of

the Flash memory may be accomplished in several ways: over the serial builtin JTAG

interface, using In System Programming (ISP) and UART0, or by means of In Application

Programming (IAP) capabilities. The application program, using the IAP functions, may

also erase and/or program the Flash while the application is running, allowing a great

degree of flexibility for data storage field firmware upgrades, etc. When the

LPC2131/2/4/6/8 on-chip bootloader is used, 32/64/128/256/500 kB of Flash memory is

available for user code.

The LPC2131/2/4/6/8 Flash memory provides minimum of 10,000 erase/write cycles and

10 years of data-retention.

1.8 On-chip Static RAM (SRAM)

On-chip Static RAM (SRAM) may be used for code and/or data storage. The on-chip

SRAM may be accessed as 8-bits, 16-bits, and 32-bits. The LPC2131/2/4/6/8 provide

8/16/32 kB of static RAM respectively.

The LPC2131/2/4/6/8 SRAM is designed to be accessed as a byte-addressed memory.

Word and halfword accesses to the memory ignore the alignment of the address and

access the naturally-aligned value that is addressed (so a memory access ignores

address bits 0 and 1 for word accesses, and ignores bit 0 for halfword accesses).

Therefore valid reads and writes require data accessed as halfwords to originate from

addresses with address line 0 being 0 (addresses ending with 0, 2, 4, 6, 8, A, C, and E in

hexadecimal nottaion) and data accessed as words to originate from adresses with

address lines 0 and 1 being 0 (addresses ending with 0, 4, 8, and C in hexadecimal

notation). This rule applies to both off and on-chip memory usage.

The SRAM controller incorporates a write-back buffer in order to prevent CPU stalls during

back-to-back writes. The write-back buffer always holds the last data sent by software to

the SRAM. This data is only written to the SRAM when another write is requested by

software (the data is only written to the SRAM when software does another write). If a chip

reset occurs, actual SRAM contents will not reflect the most recent write request (i.e. after

a "warm" chip reset, the SRAM does not reflect the last write operation). Any software that

checks SRAM contents after reset must take this into account. Two identical writes to a

location guarantee that the data will be present after a Reset. Alternatively, a dummy write

operation before entering idle or power-down mode will similarly guarantee that the last

data written will be present in SRAM after a subsequent Reset.

User manual Rev. 01 — 24 June 2005 7

Philips Semiconductors UM10120

Volume 1 Chapter 1: Introductory information

1.9 Block diagram

(1) LPC2134/2136/2138 only.

(2) LPC2132/2134/2136/2138 only.

(3) Pins shared with GPIO.

Fig 1. LPC2131/2/4/6/8 block diagram

002aab067

system

clock

SCL0,1

AOUT(2)

P0.31:0

P1.31:16

SDA0,1

TRST(3)

TMS(3)

TCK(3)

TDI(3)

TDO(3) XTAL2

XTAL1

SCK0,1

MOSI0,1

MISO0,1

EINT3:0

8 ×CAP0

8 ×MAT

AD0.7:0

AD1.7:0(1)

PWM6:1

SSEL0,1

TXD0,1

RXD0,1

RTXC2

RTXC1

VBAT

DSR1(1),CTS1(1),

RTS1(1), DTR1(1)

DCD1(1),RI1(1)

AMBA AHB

(Advanced High-performance Bus)

INTERNAL

FLASH

CONTROLLER

AHB BRIDGE

EMULATION TRACE

MODULE

TEST/DEBUG

INTERFACE

AHB

DECODER

AHB TO VPB

BRIDGE VPB

DIVIDER

VECTORED

INTERRUPT

CONTROLLER

SYSTEM

FUNCTIONS

PLL

SPI AND SSP

SERIAL INTERFACES

I2C SERIAL

INTERFACES 0 AND 1

UART0/UART1

REAL TIME CLOCK

WATCHDOG

TIMER

SYSTEM

CONTROL

EXTERNAL

INTERRUPTS

GENERAL

PURPOSE I/O

PWM0

CAPTURE/

COMPARE

TIMER 0/TIMER 1

A/D CONVERTERS

0 AND 1(1)

D/A CONVERTER(2)

32/64/128/

256/512 kB

FLASH

ARM7TDMI-S

LPC2131/2132/2134/2136/2138

INTERNAL

SRAM

CONTROLLER

8/16/32 kB

SRAM

ARM7 local bus

VPB (VLSI

peripheral bus)

RST

User manual Rev. 01 — 24 June 2005 8

2.1 Memory maps

The LPC2131/2/4/6/8 incorporates several distinct memory regions, shown in the

following figures. Figure 2 shows the overall map of the entire address space from the

user program viewpoint following reset. The interrupt vector area supports address

remapping, which is described later in this section.

UM10120

Chapter 2: LPC2131/2/4/6/8 Memory Addressing

Rev. 01 — 24 June 2005 User manual

Fig 2. System memory map

TOTAL OF 32 kB ON-CHIP NON-VOLATILE MEMORY

(LPC2131)

0xC000 0000

0x8000 0000

0x0000 0000

0.0 GB

1.0 GB

2.0 GB

3.75 GB

4.0 GB

3.0 GB

TOTAL OF 64 kB ON-CHIP NON-VOLATILE MEMORY

(LPC2132)

RESERVED ADDRESS SPACE

8 kB ON-CHIP STATIC RAM (LPC2131)

16 kB ON-CHIP STATIC RAM (LPC2132/2134)

32 kB ON-CHIP STATIC RAM (LPC2136/2138)

RESERVED ADDRESS SPACE

BOOT BLOCK

(REMAPPED FROM ON-CHIP FLASH MEMORY)

RESERVED ADDRESS SPACE

AHB PERIPHERALS

VPB PERIPHERALS

3.5 GB

0x4000 4000

0x4000 3FFF

0x4000 8000

0x4000 7FFF

0x4000 0000

0xE000 0000

0xF000 0000

0xFFFF FFFF

TOTAL OF 128 kB ON-CHIP NON-VOLATILE MEMORY

(LPC2134)

TOTAL OF 256 kB ON-CHIP NON-VOLATILE MEMORY

(LPC2136)

TOTAL OF 512 kB ON-CHIP NON-VOLATILE MEMORY

(LPC2138)

0x4000 2000

0x4000 1FFF

0x0000 8000

0x0000 7FFF

0x0001 0000

0x0000 FFFF

0x0002 0000

0x0001 FFFF

0x0004 0000

0x0003 FFFF

0x0008 0000

0x0007 FFFF

User manual Rev. 01 — 24 June 2005 9

Philips Semiconductors UM10120

Volume 1 Chapter 2: Memory map

Figures 3through 5show different views of the peripheral address space. Both the AHB

and VPB peripheral areas are 2 megabyte spaces which are divided up into 128

peripherals. Each peripheral space is 16 kilobytes in size. This allows simplifying the

Fig 3. Peripheral memory map

AHB PERIPHERALS

RESERVED

VPB PERIPHERALS

0xFFFF FFFF

0xFFE0 0000

0xFFDF FFFF

0xF000 0000

0xEFFF FFFF

0xE020 0000

0xE01F FFFF

0xE000 0000

3.5 GB

3.5 GB + 2 MB

3.75 GB

4.0 GB - 2 MB

4.0 GB

Notes:

- AHB section is

128 x 16 kB blocks

(totaling 2 MB).

- VPB section is

128 x 16 kB blocks

(totaling 2 MB).

User manual Rev. 01 — 24 June 2005 10

Philips Semiconductors UM10120

Volume 1 Chapter 2: Memory map

address decoding for each peripheral. All peripheral register addresses are word aligned

(to 32-bit boundaries) regardless of their size. This eliminates the need for byte lane

mapping hardware that would be required to allow byte (8-bit) or half-word (16-bit)

accesses to occur at smaller boundaries. An implication of this is that word and half-word

registers must be accessed all at once. For example, it is not possible to read or write the

upper byte of a word register separately.

Fig 4. AHB peripheral map

VECTORED INTERRUPT CONTROLLER

(AHB PERIPHERAL #0)

0xFFFF F000 (4G - 4K)

0xFFFF C000

0xFFFF 8000

(AHB PERIPHERAL #125)

(AHB PERIPHERAL #124)

(AHB PERIPHERAL #3)

(AHB PERIPHERAL #2)

(AHB PERIPHERAL #1)

(AHB PERIPHERAL #126)

0xFFFF 4000

0xFFFF 0000

0xFFE1 0000

0xFFE0 C000

0xFFE0 8000

0xFFE0 4000

0xFFE0 0000

Dieses Handbuch passt für folgende Modelle

Inhaltsverzeichnis

Andere Philips Mikrocontroller Handbücher

Philips

Philips P89LPC938 Bedienungsanleitung

Philips

Philips LPC2101 Bedienungsanleitung

Philips

Philips P89LPC920 Bedienungsanleitung

Philips

Philips LPC3180 Montage- und Bedienungsanleitung

Philips

Philips LPC2194 Bedienungsanleitung

Philips

Philips LPC214 Series Bedienungsanleitung

Philips

Philips LPC2119 Bedienungsanleitung

Beliebte Mikrocontroller Handbücher anderer Marken

Novatek

Novatek NT6861 Bedienungsanleitung

Espressif Systems

Espressif Systems ESP8266 SDK Einrichtungshandbuch

Nuvoton

Nuvoton ISD61S00 ChipCorder Leitfaden

STMicrolectronics

STMicrolectronics ST7 Assembler Linker Bedienungsanleitung

Texas Instruments

Texas Instruments Chipcon CC2420DK Bedienungsanleitung

Lantronix

Lantronix Intrinsyc Open-Q 865XR SOM Bedienungsanleitung

NEC

NEC 78GK0S/K 1+ Series Montage- und Bedienungsanleitung

Mikroe

Mikroe SEMITECH N-PLC Click Montage- und Bedienungsanleitung

Intel

Intel Agilex Bedienungsanleitung

Cypress

Cypress CY4607 HX2VL Bedienungsanleitung

DIGITAL-LOGIC

DIGITAL-LOGIC MICROSPACE Bedienungsanleitung

Texas Instruments

Texas Instruments TMS320F2837 D Series Bedienungsanleitung

CYPRES

CYPRES CY14NVSRAMKIT-001 Bedienungsanleitung

Espressif Systems

Espressif Systems ESP8266EX Betriebsanleitung

Abov

Abov AC33M8128L Bedienungsanleitung

Laird

Laird BL654PA Bedienungsanleitung

Silicon Laboratories

Silicon Laboratories C8051F800 Bedienungsanleitung

Energy micro

Energy micro EFM32 Giant Gecko Starter Kit Bedienungsanleitung