Philips TEA5880TS Bedienungsanleitung

1. General description

The TEA5880TS stereo FM radio IC dramatically reduces the printed-circuit board area

(only 100 mm2) needed to integrate FM radio functionality into portable devices. This

makes it invaluable for any application where space is at a premium.

Relying on a system host processor for radio tuning, the TEA5880TS is ideally suited for

powerful devices such as PDAs, notebooks, portable CD and MP3 players.

2. Features

■No alignments necessary

■Complete adjustment-free stereo decoder; no external crystal required

■Fully integrated MPX VCO circuit

■Fully integrated low IF selectivity and demodulation

■The full integration level means no or few external components required

■No external FM discriminator needed due to full integration

■Built-in adjacent channel interference total reduction (no 114 kHz, no 190 kHz)

■The level of the incoming signal at which the radio must lock is software programmable

■Due to new tuning concept, the tuning is independent of the channel spacing

■Very high sensitivity due to integrated low noise RF input ampliﬁer

■RF Automatic Gain Control (AGC) circuit

■Standby mode for power-down, no power switch circuitry required

■2.7 V minimum supply voltage

■MPX output for RDS

■3-wire bus

■In combination with the host, fast, low power operation of preset mode, manual search,

automatic search and automatic store are possible

■Host can be in Sleep mode after tuning; a minute retuning is recommended to

compensate for temperature and voltage ﬂuctuations

■Covers all Japanese, European and US bands.

TEA5880TS

Integrated FM stereo radio IC for host processor tuning in

handheld applications

Rev. 02 — 26 April 2004 Preliminary data sheet

Preliminary data sheet Rev. 02 — 26 April 2004 2 of 27

Philips Semiconductors TEA5880TS

Integrated FM stereo radio IC for host processor tuning

3. Quick reference data

Table 1: Quick reference data

CCA

= V

CCD

Symbol Parameter Conditions Min Typ Max Unit

VCCA analog supply voltage 2.7 3.0 5.0 V

VCCD digital supply voltage 2.7 3.0 5.0 V

ICCA analog supply current operating - 17 22 mA

standby - 1 100 µA

ICCD digital supply current operating - 250 500 mA

standby - 1 100 µA

ILED optional stereo LED - 1 2 mA

fFM(ant) FM input frequency 76 - 108 MHz

Tamb ambient temperature VCCA = VCC(VCO) = VCCD = 3 V −10 - +75 °C

VCCA = VCC(VCO) = VCCD = 5 V −40 - +85 °C

FM overall system parameters

Vi(RF) RF sensitivity input

voltage fRF = 76 MHz to 108 MHz; ∆f = 22.5 kHz;

fmod = 1 kHz; (S+N)/N = 26 dB;

de-emphasis = 75 us;

BAF = 300 Hz to 15 kHz; left = right

-13µV

SUPpilot pilot suppression ∆fpilot = 6.75 kHz; ∆f = 68.5 kHz 40 dB

IP3in in-band 3rd order

intercept point at LNA

input

-95-dBµV

IP3out out-band 3rd order

intercept point at LNA

input

-95-dBµV

S−300 LOW side 300 kHz

selectivity ∆f = −300 kHz; fRF = 76 MHz to 108 MHz - 40 - dB

S+300 HIGH side 300 kHz

selectivity ∆f = 300 kHz; fRF = 76 MHz to 108 MHz - 50 - dB

S−200 LOW side 200 kHz

selectivity ∆f = −200 kHz; fRF = 76 MHz to 108 MHz - 30 - dB

S+200 HIGH side 200 kHz

selectivity ∆f = 200 kHz; fRF = 76 MHz to 108 MHz - 40 - dB

IR image rejection fRF = 76 MHz to 108 MHz - 26 - dB

VAUDL;

VAUDR

left and right audio output

voltage VRF = 1 mV; left = right; ∆f = 22.5 kHz;

fmod = 1 kHz - 100 - mV

(S+N)/N maximum signal plus

noise-to-noise ratio VRF = 1 mV; left = right; ∆f = 22.5 kHz;

fmod = 1 kHz de-emphasis = 75 µs;

BAF = 300 Hz to 15 kHz

48 56 - dB

αcs stereo channel

separation VRF = 1 mV; right = 1 and left = 0 or

right = 0 and left = 1; fmod = 1 kHz;

∆fpilot = 6.75 kHz; ∆fleft = 68.5 kHz and

∆fright = 0 or ∆fright = 68.5 kHz and ∆fleft = 0

15 25 - dB

Preliminary data sheet Rev. 02 — 26 April 2004 3 of 27

Philips Semiconductors TEA5880TS

Integrated FM stereo radio IC for host processor tuning

4. Ordering information

THD total harmonic distortion VRF = 1 mV; left = right; ∆f = 75 kHz;

fmod = 1 kHz; BAF = 300 Hz to 15 kHz - 0.7 1.5 %

VRF = 1 mV; left = right; ∆f = 22.5 kHz;

fmod = 1 kHz; BAF = 300 Hz to 15 kHz - 0.2 0.7 %

DEEM integrated de-emphasis - 50/75 - µs

Table 1: Quick reference data

…continued

CCA

= V

CCD

Symbol Parameter Conditions Min Typ Max Unit

Table 2: Ordering information

Type number Package

Name Description Version

TEA5880TS SSOP24 plastic shrink small outline package; 24 leads; body width 5.3 mm SOT340-1

xxxx xxxxxxxxxxxxxxxxxxxxxxxxxxxxxx x xxxxxxxxxxxxxx xxxxxxxxxx xxx xxxxxx xxxxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxxxxxxxxxxxx

xxxxx xxxxxx xx xxxxxxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxx xxxxxxx xxxxxxxxxxxxxxxxxxx

xxxxxxxxxxxxxxxx xxxxxxxxxxxxxx xxxxxx xx xxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxxxxxxxxxxxxxx xxxxxxx

xxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxx xxxxx x x

Preliminary data sheet Rev. 02 — 26 April 2004 4 of 27

Philips Semiconductors TEA5880TS

Integrated FM stereo radio IC for host processor tuning

5. Block diagram

Depending on the antenna design the ﬁlter components at pins 1 and 2 may not be necessary. The only two remaining coils connected to pin

17 to 20 can be replaced by printed-circuit board traces that will ﬁt underneath the TEA5880TS resulting in a design without any external

components; see Section 14 for details on the printed-circuit board coils.

Fig 1. Block diagram.

001aaa665

QUADRATURE

MIXER

STABILISATOR

QUADRATURE

OSCILLATOR TUNING

SYSTEM

SELECTIVITY DEMODULATOR

POWER

SWITCH

STEREO

DECODER DE-EMPHASIS

50/75 µs

DIGITAL

INTERFACE

MICROCONTROLLER

DE-EMPHASIS

15 kHz MIXER

LEVEL VOLTAGE

GENERATOR

TEA5880TS

68 7

2117 18 19 20

4 3, 13, 24

VCCA

RFIN

RFGND

LR1 VCC1 VCC1 LL1 reserved R/W CLOCK

AUDL

AUDR

MPX

DATA

VCCD GND LED n.c.

12 14, 15, 16, 22, 23

xxxx xxxxxxxxxxxxxxxxxxxxxxxxxxxxxx x xxxxxxxxxxxxxx xxxxxxxxxx xxx xxxxxx xxxxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxxxxxxxxxxxx

xxxxx xxxxxx xx xxxxxxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxx xxxxxxx xxxxxxxxxxxxxxxxxxx

xxxxxxxxxxxxxxxx xxxxxxxxxxxxxx xxxxxx xx xxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxxxxxxxxxxxxxx xxxxxxx

xxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxx xxxxx x x

Preliminary data sheet Rev. 02 — 26 April 2004 5 of 27

Philips Semiconductors TEA5880TS

Integrated FM stereo radio IC for host processor tuning

Fig 2. Block diagram (no external components).

001aaa666

STABILISATOR

QUADRATURE

OSCILLATOR TUNING

SYSTEM

SELECTIVITY DEMODULATOR

POWER

SWITCH

STEREO

DECODER DE-EMPHASIS

50/75 µs

DIGITAL

INTERFACE

MICROCONTROLLER

DE-EMPHASIS

15 kHz MIXER

LEVEL VOLTAGE

GENERATOR

TEA5880TS

68 7

2117 18 19 20

4 3, 13, 24

VCCA

LR1 VCC1 VCC1 LL1 reserved R/W CLOCK

AUDL

AUDR

MPX

DATA

VCCD GND LED n.c.

12 14, 15, 16, 22, 23

QUADRATURE

MIXER

RFIN

RFGND

Preliminary data sheet Rev. 02 — 26 April 2004 6 of 27

Philips Semiconductors TEA5880TS

Integrated FM stereo radio IC for host processor tuning

6. Pinning information

6.1 Pin description

Table 3: Pin description

Symbol Pin Description

RFIN 1 RF input

RFGND 2 RF ground

GND 3 ground

VCCD 4 digital supply voltage

VCCA 5 analog supply voltage

R/W 6 digital read/write command input

DATA 7 bidirectional digital data line

CLOCK 8 digital data clock line input

MPX 9 FM MPX signal output

AUDL 10 audio left channel output

AUDR 11 audio right channel output

LED 12 stereo LED output

GND 13 ground

n.c. 14 not connected

n.c. 15 not connected

n.c. 16 not connected

LR1 17 coil right

VCC1 18 internal analog voltage

VCC1 19 internal analog voltage

LL1 20 coil left

reserved 21 reserved for testing use

n.c. 22 not connected

n.c. 23 not connected

GND 24 ground

Preliminary data sheet Rev. 02 — 26 April 2004 7 of 27

Philips Semiconductors TEA5880TS

Integrated FM stereo radio IC for host processor tuning

7. Functional description

7.1 FM quadrature mixer

The FM quadrature mixer converts FM RF (76 MHz to 108 MHz) to an IF of 110 kHz. The

FM quadrature mixer provides inherent image rejection.

7.2 Quadrature oscillator

The internally tuned LC VCO provides the Local Oscillator (LO) signal for the FM

quadrature mixer. The VCO frequency range is 150 MHz to 217 MHz.

7.3 Selectivity

Fully integrated I and Q channel IF ﬁlter.

7.4 Demodulator

The FM quadrature demodulator is an integrated PLL demodulator.

7.5 Level voltage generator and analog-to-digital converter

The level voltage is analog-to-digital converted with 3 bits and output via the data line.

7.6 IF counter

The IF counter outputs a 16-bit count result via the data line.

7.7 Mute

The digital interface controls the audio mute and output level.

Fig 3. Pin conﬁguration.

TEA5880TS

RFIN GND

RFGND n.c.

GND n.c.

VCCD reserved

VCCA LL1

R/W VCC1

DATA VCC1

CLOCK LR1

MPX n.c.

AUDL n.c.

AUDR n.c.

LED GND

001aaa667

Preliminary data sheet Rev. 02 — 26 April 2004 8 of 27

Philips Semiconductors TEA5880TS

Integrated FM stereo radio IC for host processor tuning

7.8 Stereo decoder

The PLL stereo decoder is adjustment free. The stereo decoder can be switched to mono

via the digital interface.

8. Digital interface (3-wire bus)

The TEA5880TS has a 3-wire bus with read/write, clock and data line.

The register set of the TEA5880TS can be accessed via the digital interface.

The pins given in Table 4 are deﬁned for the digital interface of the TEA5880TS.

Table 4: Digital interface pins

Pin number Name Type Description Remark

Pin 6 R/W input LOW is read from TEA5880TS;

HIGH is write to TEA5880TS

Pin 8 CLOCK input clock rising edge

Pin 7 DATA input/output bidirectional data

Fig 4. Digital interface block diagram.

001aaa668

OUTPUT

SOURCE

SELECTOR

CONTROL

ADDRESS

DECODER

CONTROL

REST OF THE

REGISTERS

STATUS REGISTER

15 BITS SIPO (SERIAL IN PARALLEL OUT)

stereo LED

stereo clock

IF OSC

R/W

FM OSC

CLOCK

DATA

COUNTER 1 (16 bits)

16 BITS PISO (PARALLEL IN SERIAL OUT)

R/W

11 bits data

4 bits data

16 bits data 16 bits data

CLOCK R/W

R/W

enable

counter 1

control bits

1-bit data

Preliminary data sheet Rev. 02 — 26 April 2004 9 of 27

Philips Semiconductors TEA5880TS

Integrated FM stereo radio IC for host processor tuning

8.1 Register description

[1] The application should write logic 0 to this register at start-up to ensure that the device functions correctly.

Table 5: TEA5880TS registers description

Address Register name Access Operation Data width Clocks

0000b VADC write only VADC register 11 bits 15

0001b CTRL_C write only control register C 11 bits 15

0010b CTRL_A write only control register A 11 bits 15

0011b OSC_STEREO write only oscillator stereo

decoder clock 11 bits 15

0100b CTRL_B write only control register B 11 bits 15

0101b CAP_FM write only capacitor bank FM 11 bits 15

0110b OSC_IF write only oscillator IF 11 bits 15

0111b OSC_FM write only oscillator FM 11 bits 15

- STATUS read only status register 16 bits 15

- COUNTER read only counter register 16 bits 15

Table 6: VADC - (address 0h) bit description

Bit Symbol Description

14 to 11 - address bits

10 to 6 VADC2[4:0] controls the width ﬁlter

5 - not applicable; should be written to logic 0

4 to 0 VADC1[4:0] controls the center ﬁlter

Table 7: CTRL_C - (address 1h) bit description[1]

Bit Symbol Description

14 to 11 - address bits

10 and 9 - reserved for production test; should be written to logic 0

8 - reserved for swapping counters1 and 2; should be written to logic 0

7 to 4 - not applicable; should be written to logic 0

3 to 1 - reserved for time delay selection (counter 2); application should keep

bits 3 to 1 at logic 0; see Table 8

0 - reserved for enable counter 2; should be written to logic 0

Table 8: Time delay selection

Value Decimal Stop value

000b 0 count 2

001b 1 count 8

010b 2 count 32

011b 3 count 128

100b 4 count 512

101b 5 count 2048

110b 6 count 8192

111b 7 count 32768

Preliminary data sheet Rev. 02 — 26 April 2004 10 of 27

Philips Semiconductors TEA5880TS

Integrated FM stereo radio IC for host processor tuning

[1] The frequency is decreased when increasing the content of this register.

Table 9: CTRL_A - (address 2h) bit description

Bit Symbol Description

14 to 11 - address bits

10 to 7 OUTPUT_

SELECT[3:0] selects an internal circuit as output for measurement purpose;

see Table 10

6 STE_PMUTE mutes the stereo PLL when set to logic 1; this bit should be

set during calibration of the stereo decoder clock and should be

cleared during normal operation

5 DEM_PMUTE mutes the demodulator PLL when set to logic 1; this bit

should be set during calibration of the IF frequency and should

be cleared during normal operation

4 STE_INT_OFF# turns off the stereo integrator loop when set to logic 0

3 EN_MEAS# enables measurement when set to logic 0

2 AMUTE mutes the audio when set to logic 1

1 FM enables the FM circuitry when set to logic 1

0 - reserved for AM circuitry; should be written to logic 0

Table 10: Description of OUTPUT_SELECT bits

Symbol Value Decimal Output selected

OS-NONE 0000b 0 no output selected

OS_FM_OSC 0001b 1 FM oscillator

OS_NA2 0010b 2 not deﬁned

OS_CNT2_RDY_NA 0011b 3 reserved for counter 2 ready output

OS_NA4 0100b 4 not deﬁned

OS_STEREO_DEC 0101b 5 stereo decoder clock

OS_NA6 0110b 6 not deﬁned

OS_STEREO_LED 0111b 7 stereo LED

OS_NA8 1000b 8 not deﬁned

OS_IF_OSC 1001b 9 IF oscillator

OS_INTERRUPT_NA 1010b 10 reserved for interrupt output

OS_PISO 1011b 11 PISO output (reading STATUS / COUNTER

OS_NA12 1100b 12 not deﬁned

OS_RDS_NA 1101b 13 reserved for RDS output

OS_NA14 1110b 14 not deﬁned

OS_NA15 1111b 15 not deﬁned

Table 11: OSC_STEREO - (address 3h) bit description[1]

Bit Symbol Description

14 to 11 - address bits

10 to 0 SO[10:0] 11-bit digital-to-analog converter for adjusting the stereo decoder clock

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