Quectel EC20 Service-Handbuch
TITLEPROJECT
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EC20 Reference Design
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A2
Module Interface
1. Keep all RESERVED and unused pins unconnected.
Notes:
2. Pin 73~84 and 117~140 are unused in the design. You can ignore them in schematic and PCB decal.
Module Interface
3. The DBG_RXD/DBG_TXD, CTS/RTS/DCD and SD functions are not supported on EC20-E currently.
1WAKEUP_IN
2AP_READY
3RESERVED
4W_DISABLE#
5NET_MODE
6NET_STATUS
7VDD_EXT
8GND
9GND
10 USIM_GND
11 DBG_RXD
12 DBG_TXD
13 RESERVED
14 USIM_VDD
15 USIM_DATA
16 USIM_CLK
17 USIM_RST
18 RESERVED
19 GND
20 RESET_N
21 PWRKEY
22 GND
23 SD_INS_DET
24 PCM_IN*
25 PCM_OUT*
26 PCM_SYNC*
27 PCM_CLK*
28 SD1_DATA3
29 SD1_DATA2
30 SD1_DATA1
31 SD1_DATA0
32 SD1_CLK
33 SD1_CMD
34 VDD_SDIO
35 ANT_DIV
36 GND
37
RESERVED
38
RESERVED
39
RESERVED
40
RESERVED
41
I2C_SCL
42
I2C_SDA
43
RESERVED
44
ADC1
45
ADC0
46
GND
47
ANT_GNSS
48
GND
49
ANT_MAIN
50
GND
51
GND
52
GND
53
GND
54
GND
55
RESERVED 56
GND 57
VBAT_RF 58
VBAT_RF 59
VBAT_BB 60
VBAT_BB 61
STATUS 62
RI 63
DCD 64
CTS 65
RTS 66
DTR 67
TXD 68
RXD 69
USB_DP 70
USB_DM 71
USB_VBUS 72
GND
115 RESERVED
116 RESERVED
113
RESERVED 114
RESERVED
U101-A
85
GND 86
GND 87
GND 88
GND 89
GND 90
GND 91
GND 92
GND 93
GND 94
GND 95
GND 96
GND 97
GND 98
GND 99
GND 100
GND 101
GND 102
GND 103
GND 104
GND 105
GND 106
GND 107
GND 108
GND 109
GND 110
GND 111
GND 112
GND
U101-B
[8] NET_STATUS
[2,4,5,7] VDD_EXT
[4] USIM_VDD
[1,3,8]VBAT
[8]
STATUS
[4]
RXD_EC20
[4]
DTR_EC20[4]
TXD_EC20
[4]
RI_EC20
[8] NET_MODE
[2]RESET_N
[2,8]PWRKEY
[5] PCM_IN
[5] PCM_OUT
[5]PCM_SYNC
[5]PCM_CLK
[6]ANT_DIV
[1,3,8]
VBAT
[2,8] USB_VBUS
[2,8] USB_DM
[2,8] USB_DP
[2] W_DISABLE#
[2] AP_READY
[4] USIM_GND
[4] USIM_CLK
[4] USIM_RST
[4] USIM_DATA
[6]
ANT_MAIN
[6]
ANT_GNSS
[5]
I2C_SDA [5]
I2C_SCL
[8]DBG_RXD
[8] DBG_TXD
[4]
CTS_EC20[4]
RTS_EC20
[4]
DCD_EC20
[7]SD1_DATA3
[7]SD1_DATA2
[7] SD1_DATA1
[7]SD1_DATA0
[7]SD1_CLK
[7]SD1_CMD
[7]VDD_SDIO
[7]SD_INS_DET
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EC20 Reference Design
A2
Notes:
1. U201 represents customer's MCU.
2. EC20 can only work as a USB device and support FS/HS mode. To communicate with USB interface,
VBUS_CONTROL = High level, Q201 conducts.
Reserved
5V power source from main board.
It is used to reset the module.It is used to turn on or off the module.
MCU Interface
MCU needs to support USB host or OTG function. The VBUS pins of MCU and EC20 need to be
provided by 5V power for USB detection, and VBUS_CONTROL turns on and off VBUS power supply.
3. AP_READY can be configured to high level detection and low level detection. For more details about AP_READY,
please refer to the document <Quectel_EC20_Hardware_Design> and <Quectel_EC20_AT_Commands_Manual>.
AP_READY High level detection AP_READY Low level detection
4. Transistor circuits (Q203~Q207) are used for level translation.
The necessary control circuit
MCU Interface
R202 0R
R201 0R
G
SD
Q201 SI2333CDS-T1
Q202
DTC043ZEBTL
R204
10K
C201
NM
1
VDD 2
GND 3
TXD 4
RXD 5
DTR 6
RI 7
CTS 8
RTS 9
DCD
12
USB_DM 13
USB_ID 14
GPIO_01 15
GPIO_02 16
GPIO_03 17
GPIO_04
10
USB_VBUS 11
USB_DP
18
GPIO_05 19
GPIO_06 20
GPIO_07
U201
Q203
DTC043ZEBTL
R205
10K
Q206
DTC043ZEBTL
R206
47K
R203 0R
Q205
DTC043ZEBTL
Q204
DTC043ZEBTL
Q207
2SA2018
R209
100K
R208
4.7K
R207
10K
VDD_MCU
[4]
TXD_MCU [4]
RXD_MCU[4]
DTR_MCU
[4]
RI_MCU
[1,8]
USB_DP
[1,8]
USB_DM
[1,2,8]
USB_VBUS
[2]
ON/OFF_MCU[2]
RESET_MCU
[2]
VBUS_CONTROL
DC_5V [1,2,8]
USB_VBUS
[2] VBUS_CONTROL
[2]
W_DISABLE_M [2]
SLEEP_STATUS
VDD_EXT
[1]
W_DISABLE#
[2] W_DISABLE_M
VDD_EXT
[1,2]
AP_READY
[2]SLEEP_STATUS
[1]
RESET_N
[2] RESET_MCU
[1,8]
PWRKEY
[2] ON/OFF_MCU
VDD_EXT
[2]SLEEP_STATUS
[1,2]
AP_READY
VDD_MCU
[4]
CTS_MCU [4]
RTS_MCU [4]
DCD_MCU
[7]
SD_PWR_EN
[3]
VBAT_EN
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EC20 Reference Design
A2
e.g. 5V
LDO Application
It is used when the input voltage is below 7V.
VBAT = (R302/R303+1)*1.24 = 3.88V
DC-DC Application
It is used when the input voltage is above 7V. Use DC-DC to convert high input
e.g. DC12V IN DC-DC DC 5V out LDO DC 3.8V out for module
voltage to 5V, and LDO will generate 3.8V typical voltage for the module.
VDD_3.0V = (R305/R306+1)*1.207 = 3.0V
Supply Power for PCM Codec and SD Card
Close to the module VBAT pins
Note:
VBAT should be routed in star mode to VBAT_BB and VBAT_RF pins.
Power Supply Design
VBAT Design
Connect to VBAT_BB pins
Connect to VBAT_RF pins
Power Design
+
C303
470uF
1EN
2IN
3GND
4
OUT
5ADJ
U301 MIC29302WU
C304
100nF
C302
100nF
+
C301
470uF
R302
100K
1%
R303
47K
1% 1IN
3EN
5
OUT
4
BP
2GND
U302 SGM2019-ADJ
C316
4.7uF
R305
63.4K
1%
R306
42.2K
1%
C317
100nF
R304 51K
C314
1uF
C315
100nF
+
C305
100uF
D301
PZ3D4V2H
R301
51K
C306
100nF C307
33pF
C308
10pF
C310
100nF C311
33pF
C312
10pF
+
C309
100uF
R307
470R
D302
TVS
Q301
DTC043ZEBTL
DC_IN VBAT
VDD_3.0V
VBAT
[1,3,8]
VBAT
[1,3,8]
VBAT
VBAT
[2] VBAT_EN
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DATE 2015/3/30
EC20 Reference Design
A2
1. R401~R403 are applied to suppress the EMI spurious transmission
Notes:
2. R404 can improve anti-jamming capability of the USIM circuit, and
USIM and UART Design
and enhance the ESD protection.
it should be placed close to the USIM connector.
UART Translation IC Solution
UART Transistor Solution (Recommend)
3. VCCA should not exceed VCCB. For more information about TXS0108E,
please refer to the datasheet from TI.
4. If you need to enable high baud rate, it is highly recommended to install
a 1nF capacitor (C407/C408) on transistor circiut.
USIM and UART Design
5. The DTR transistor circuit is similar with RTS interface, and the RI and DCD
transistor circuit is similar with CTS interface.
C401 100nF
1
2
3
4
5
6
U401 ESDA6V8AV6
C403
33pF C404
33pF
C402
33pF
R401 22R
R402 22R
R403 22R
R404
15K
GND
VPP
I/OCLK
RST
VCC
J401 C405
100nF
R406
120K
R405
10K
C406 100nF
Q401
2SC4617TLQ Q402 2SC4617TLQ
R408
4.7K
R407
4.7K
C407
1nF R409
4.7K
R410
4.7K C408
1nF
Q403
2SC4617TLQ
R412
4.7K
R411
4.7K
Q404 2SC4617TLQ
R413
4.7K
R414
4.7K
6A5
7A6
8A7
9A8
10 OE
5A4
4A3
19
VCCB
20
B1
18
B2
14
B6 13
B7 12
B8 11
GND
3A2
2VCCA
1A1
17
B3 16
B4 15
B5
U402
TXS0108E
USIM_VDD
[1]USIM_RST
[1]USIM_CLK
[1]USIM_DATA
USIM_VDD
[1]
USIM_GND
VDD_EXT
VDD_EXT VDD_MCU
[1,4] TXD_EC20
[1,4] RXD_EC20
[1] RI_EC20
[1] DTR_EC20
[2,4]
RXD_MCU
[2,4]
TXD_MCU
[2]
DTR_MCU
[2]
RI_MCU
[2,4] TXD_MCU [1,4]
RXD_EC20
VDD_EXTVDD_EXT
[2,4] RXD_MCU [1,4]
TXD_EC20
VDD_EXTVDD_MCU
VDD_EXT
[1,4]
RTS_EC20
[2,4] RTS_MCU
VDD_EXT VDD_MCU
[2,4] CTS_MCU [1,4]
CTS_EC20
VDD_EXT
[2,4]
CTS_MCU
[2,4]
RTS_MCU
[1,4] CTS_EC20
[1,4] RTS_EC20
[1]DCD_EC20 [2]
DCD_MCU
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SIZE VER
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1.0
DATE 2015/3/30
EC20 Reference Design
A2
Audio Design
Audio - Handset Application
Close to
Audio - Earphone Application
earphone interface
Note: It is needed to add audio amplifer when the speaker impedance is less than 32ohm. Audio Design
CTIA OMTP
R519/R521
R518/R520 M
M
NM
NM
4
1
3
2
J502
Handset
D504
ESD9X5.0ST5G
D505
C537
33pF
C539
33pF
C540
10pF
C538
10pF
C541
33pF
C536
10pF
C544
10pF C545
33pF C546
10pF C547
33pF
C543
33pF
C542
10pF
C527
10pF
C528
33pF
C529
4.7uF
F501 0R
F502 0R
F504 0R
F503 0R
D506
PESD5V0S1BL
D507
2IN1P/DMC_DAT
3IN2P
4IN2N/JD2
5
DACREF 6
AVDD
7AGND
10
LOUTR/N
11
CPN2
12
CPP2
13
CPN1
14
CPP1
15
CPVDD
16
CPVPP
18
CPVREF
19
CPVEE
20
HPO_L
21 ADCDAT1
22 DACDAT1
23 LRCK1
26
SCL
27
SDA
28 GPIO1/IRQ1
29
DBVDD
30
DCVDD
31
MICVDD
32 MICBIAS1
8
VREF2
24 BCLK1
1JD1
9
LOUTL/P
17
HPO_R
25 MCLK
33 DGND
U501
ALC5616
C505
4.7uF
C504
4.7uF
C503
100nF
R501 0R
C502
4.7uF
C501
100nF
C509
2.2uF
C510
100nF
C506
4.7uF
C507
100nF
C508
2.2uF
C515 2.2uF
C516 2.2uF
C511 4.7uF R502
0R
R507 NM_10K
R508
4.7K
R509
4.7K
C523 4.7uF
C521 2.2uF
C522 2.2uF
R512 0R
R-0805
R503 0R
R504 0R
R505 0R
R506 0R
C512
NM
C513
NM
C514
NM
C524 2.2uF
C525 2.2uF
R510
1K
R511
1.5K
R513
1K
R514
1.5K
C526
10uF
R515 0R
1
2
3
4
5
J501
Earphone
C517 1uF
C518 1uF
C519 1uF
C520 1uF
R516 0R
R517 0R
C530
10pF
C531
33pF
D501
ESD9X5.0ST5G
R519 NM_0R
R518 0R
R520 0R
R521 NM_0R
D502
PESD5V0S1BL
C532
10pF
C533
33pF
D503
PESD5V0S1BL
C534
10pF
C535
33pF
[5] SPK_P
[5] MIC_P
[5] MIC_N
[5] MIC_N
[5] SPK_N
VDD_3.0V
VDD_EXT
VDD_3.0V [1]
I2C_SDA [1]
I2C_SCL
VDD_EXT
VDD_EXT
[1]PCM_OUT
[1] PCM_IN
[1]PCM_CLK
[1]PCM_SYNC
[5]MIC+
[5] MIC-
[5]
SPK_P [5]
SPK_N
MICBIAS
[5] MIC_P
[5] MIC_N
MICBIAS
[5]
MIC+[5]
MIC-
VDD_EXT
[5]
SPK_R[5]
SPK_L
[5] SPK_R
[5] SPK_L
[5] MIC_P
[5]
MIC_P
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DATE 2015/3/30
EC20 Reference Design
A2
Main Antenna Interface Diversity Antenna Interface
C601 and C602 are reserved for impedance matching.
RF and GNSS Design
1. You can choose an external LDO according to the active antenna to supply power (VDD left).
Notes:
GNSS Antenna Circuit
2. If you design the antenna circuit with passive antenna, the R603 and L603 are not needed.
Active Antenna /
RF and GNSS Design
C603 and C604 are reserved for impedance matching.
C601
NM
R601 0R
C603
NM
R602 0R
J601
Main antenna J602
Diversity antenna
C602
NM C604
NM
L603
47nH
C605
0.1uF
R603
10R
C606 100pF
J603
Passive Antenna
C607
NM C608
NM
12
D601
LXES15AAA1-117
[1]
ANT_MAIN [1]
ANT_DIV
[1]
ANT_GNSS
VDD
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VER
87
1.0
DATE 2015/3/30
EC20 Reference Design
A2
SD Design
Notes:
1. The RC circuit on SD lines is recommended to be reserved for adjust.
2. Route SD lines with 50ohm trace impedance.
3. Total routing length < 100mm is recommended.
4. Spacing to all other signals with more than 2x line width.
5. The parasitic capacitance of ESD components should be smaller than 15pF.
SD Design
C702
33pF
C701
0.1uF
R702 33R
R703 0R
R705 0R
R706 0R
R707 0R
R713
120K
D707
ESD9X3.3ST5G
R714 1K
CMD
DATA3
DATA2
DATA0
DATA1
VSS
VDD
CLK
DETECT
J701
SDCARD
G
SD
Q701 SI2333CDS-T1
Q702
DTC043ZEBTL
R701
10K
C703
NM
C704
NM C705
NM C706
NM C707
NM C708
NM
R708
51K R709
51K R710
51K R711
51K R712
51K
R704 0R
D701
ESD9L5.0ST5G
D702 D703 D704 D705 D706
VDD_EXT
[1]
SD_INS_DET
[3,5]VDD_3.0V
[2] SD_PWR_EN
[1] SD1_CLK
[1] SD1_CMD
[1]SD1_DATA3
[1] SD1_DATA2
[1] SD1_DATA1
[1] SD1_DATA0
[1] VDD_SDIO
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EC20 Reference Design
A2
Indicators
Indicator and Test Point
2. Refer to the document <Quectel_EC20_Hardware_Design> for more details about NET_MODE and NET_STATUS.
Notes:
1. Module STATUS is open drain output.
Reserved Test Points
Notes:
1. Both USB and debug UART interface are reserved for software debug.
3. Keep USB test points as close as possible to USB pins.
Other Design
2. USB interface can be used to upgrade firmware either.
Q802
DTC043ZEBTL
R803
2.2K
D803
Q801
DTC043ZEBTL
R802
2.2K
D802
R801
2.2K
D801
4
5
6
3
2
1
7
8
J801
D806
SD12
D807
ESD9X3.3ST5G
D805
ESD9L5.0ST5G
D804
ESD9L5.0ST5G
D808
ESD9X3.3ST5G
D809
ESD9X3.3ST5G
[1]NET_STATUS
VBAT
[1] NET_MODE
VBAT
[1]STATUS
VBAT
[1,3,8]
VBAT
[1,2]
PWRKEY
[1,2]
USB_DP
[1,2]
USB_DM
[1,2]
USB_VBUS
[1]
DBG_RXD
[1]
DBG_TXD
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1
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