Renesas R8C/18 Series Bedienungsanleitung

www.renesas.com

REJ09B0222-0130

16 R8C/18 Group, R8C/19 Group

Hardware Manual

RENESAS 16-BIT SINGLE-CHIP MCU

R8C FAMILY / R8C/1x SERIES

Rev.1.30

Revision Date: Apr 14, 2006

All information contained in these materials, including products and product specifications,

represents information on the product at the time of publication and is subject to change by

Renesas Technology Corp. without notice. Please review the latest information published

by Renesas Technology Corp. through various means, including the Renesas Technology

Corp. website (http://www.renesas.com).

Keep safety first in your circuit designs!

Notes regarding these materials

1. Renesas Technology Corp. puts the maximum effort into making semiconductor products

better and more reliable, but there is always the possibility that trouble may occur with

them. Trouble with semiconductors may lead to personal injury, fire or property damage.

Remember to give due consideration to safety when making your circuit designs, with ap-

propriate measures such as (i) placement of substitutive, auxiliary circuits, (ii) use of non-

flammable material or (iii) prevention against any malfunction or mishap.

1. These materials are intended as a reference to assist our customers in the selection of the

Renesas Technology Corp. product best suited to the customer's application; they do not

convey any license under any intellectual property rights, or any other rights, belonging to

Renesas Technology Corp. or a third party.

2. Renesas Technology Corp. assumes no responsibility for any damage, or infringement of

any third-party's rights, originating in the use of any product data, diagrams, charts, pro-

grams, algorithms, or circuit application examples contained in these materials.

3. All information contained in these materials, including product data, diagrams, charts, pro-

grams and algorithms represents information on products at the time of publication of these

materials, and are subject to change by Renesas Technology Corp. without notice due to

product improvements or other reasons. It is therefore recommended that customers con-

tact Renesas Technology Corp. or an authorized Renesas Technology Corp. product dis-

tributor for the latest product information before purchasing a product listed herein.

The information described here may contain technical inaccuracies or typographical errors.

Renesas Technology Corp. assumes no responsibility for any damage, liability, or other

loss rising from these inaccuracies or errors.

Please also pay attention to information published by Renesas Technology Corp. by vari-

ous means, including the Renesas Technology Corp. Semiconductor home page (http://

www.renesas.com).

4. When using any or all of the information contained in these materials, including product

data, diagrams, charts, programs, and algorithms, please be sure to evaluate all informa-

tion as a total system before making a final decision on the applicability of the information

and products. Renesas Technology Corp. assumes no responsibility for any damage, liabil-

ity or other loss resulting from the information contained herein.

5. Renesas Technology Corp. semiconductors are not designed or manufactured for use in a

device or system that is used under circumstances in which human life is potentially at

stake. Please contact Renesas Technology Corp. or an authorized Renesas Technology

Corp. product distributor when considering the use of a product contained herein for any

specific purposes, such as apparatus or systems for transportation, vehicular, medical,

aerospace, nuclear, or undersea repeater use.

6. The prior written approval of Renesas Technology Corp. is necessary to reprint or repro-

duce in whole or in part these materials.

7. If these products or technologies are subject to the Japanese export control restrictions,

they must be exported under a license from the Japanese government and cannot be im-

ported into a country other than the approved destination.

Any diversion or reexport contrary to the export control laws and regulations of Japan and/

or the country of destination is prohibited.

8. Please contact Renesas Technology Corp. for further details on these materials or the

products contained therein.

General Precautions in the Handling of MPU/MCU Products

The following usage notes are applicable to all MPU/MCU products from Renesas. For detailed usage notes on the

products covered by this manual, refer to the relevant sections of the manual. If the descriptions under General

Precautions in the Handling of MPU/MCU Products and in the body of the manual differ from each other, the description

in the body of the manual takes precedence.

1. Handling of Unused Pins

Handle unused pins in accord with the directions given under Handling of Unused Pins in the manual.

 The input pins of CMOS products are generally in the high-impedance state. In operation with an

unused pin in the open-circuit state, extra electromagnetic noise is induced in the vicinity of LSI, an

associated shoot-through current flows internally, and malfunctions occur due to the false

recognition of the pin state as an input signal become possible. Unused pins should be handled as

described under Handling of Unused Pins in the manual.

2. Processing at Power-on

The state of the product is undefined at the moment when power is supplied.

 The states of internal circuits in the LSI are indeterminate and the states of register settings and pins

are undefined at the moment when power is supplied.

In a finished product where the reset signal is applied to the external reset pin, the states of pins are

not guaranteed from the moment when power is supplied until the reset process is completed.

In a similar way, the states of pins in a product that is reset by an on-chip power-on reset function

are not guaranteed from the moment when power is supplied until the power reaches the level at

which resetting has been specified.

3. Prohibition of Access to Reserved Addresses

Access to reserved addresses is prohibited.

 The reserved addresses are provided for the possible future expansion of functions. Do not access

these addresses; the correct operation of LSI is not guaranteed if they are accessed.

4. Clock Signals

After applying a reset, only release the reset line after the operating clock signal has become stable.

When switching the clock signal during program execution, wait until the target clock signal has

stabilized.

 When the clock signal is generated with an external resonator (or from an external oscillator) during

a reset, ensure that the reset line is only released after full stabilization of the clock signal. Moreover,

when switching to a clock signal produced with an external resonator (or by an external oscillator)

while program execution is in progress, wait until the target clock signal is stable.

5. Differences between Products

Before changing from one product to another, i.e. to one with a different type number, confirm that the

change will not lead to problems.

 The characteristics of MPU/MCU in the same group but having different type numbers may differ

because of the differences in internal memory capacity and layout pattern. When changing to

products of different type numbers, implement a system-evaluation test for each of the products.

How to Use This Manual

1. Purpose and Target Readers

This manual is designed to provide the user with an understanding of the hardware functions and electrical

characteristics of the MCU. It is intended for users designing application systems incorporating the MCU. A basic

knowledge of electric circuits, logical circuits, and MCUs is necessary in order to use this manual.

The manual comprises an overview of the product; descriptions of the CPU, system control functions, peripheral

functions, and electrical characteristics; and usage notes.

Particular attention should be paid to the precautionary notes when using the manual. These notes occur

within the body of the text, at the end of each section, and in the Usage Notes section.

The revision history summarizes the locations of revisions and additions. It does not list all revisions. Refer

to the text of the manual for details.

The following documents apply to the R8C/18 Group, R8C/19 Group. Make sure to refer to the latest versions of these

documents. The newest versions of the documents listed may be obtained from the Renesas Technology Web site.

Document Type Description Document Title Document No.

Datasheet Hardware overview and electrical characteristics R8C/18 Group,

R8C/19 Group

Datasheet

REJ03B0124

Hardware manual Hardware specifications (pin assignments,

memory maps, peripheral function

specifications, electrical characteristics, timing

charts) and operation description

Note: Refer to the application notes for details on

using peripheral functions.

R8C/18 Group,

R8C/19 Group

Hardware Manual

This hardware

manual

Software manual Description of CPU instruction set R8C/Tiny Series

Software Manual REJ09B0001

Application note Information on using peripheral functions and

application examples

Sample programs

Information on writing programs in assembly

language and C

Available from Renesas

Technology Web site.

Renesas

technical update Product specifications, updates on documents,

etc.

2. Notation of Numbers and Symbols

The notation conventions for register names, bit names, numbers, and symbols used in this manual are described

below.

(1) Register Names, Bit Names, and Pin Names

Registers, bits, and pins are referred to in the text by symbols. The symbol is accompanied by the word

“register,” “bit,” or “pin” to distinguish the three categories.

Examples the PM03 bit in the PM0 register

P3_5 pin, VCC pin

(2) Notation of Numbers

The indication “b” is appended to numeric values given in binary format. However, nothing is appended to the

values of single bits. The indication “h” is appended to numeric values given in hexadecimal format. Nothing

is appended to numeric values given in decimal format.

Examples Binary: 11b

Hexadecimal: EFA0h

Decimal: 1234

3. Register Notation

The symbols and terms used in register diagrams are described below.

*1 Blank: Set to 0 or 1 according to the application.

0: Set to 0.

1: Set to 1.

X: Nothing is assigned.

*2 RW: Read and write.

RO: Read only.

WO: Write only.

−: Nothing is assigned.

*3• Reserved bit

Reserved bit. Set to specified value.

*4• Nothing is assigned

Nothing is assigned to the bit. As the bit may be used for future functions, if necessary, set to 0.

• Do not set to a value

Operation is not guaranteed when a value is set.

• Function varies according to the operating mode.

The function of the bit varies with the peripheral function mode. Refer to the register diagram for information

on the individual modes.

XXX Register

Symbol Address After Reset

XXX XXX 00h

Bit NameBit Symbol RW

b7 b6 b5 b4 b3 b2 b1 b0

XXX bits 1 0: XXX

0 1: XXX

1 0: Do not set.

1 1: XXX

b1 b0

XXX1

XXX0

XXX4

Reserved bits

XXX5

XXX7

XXX6

Function

Nothing is assigned. If necessary, set to 0.

When read, the content is undefined.

XXX bit

Function varies according to the operating

mode.

Set to 0.

(b3)

(b2)

XXX bits

0: XXX

1: XXX

4. List of Abbreviations and Acronyms

Abbreviation Full Form

ACIA Asynchronous Communication Interface Adapter

bps bits per second

CRC Cyclic Redundancy Check

DMA Direct Memory Access

DMAC Direct Memory Access Controller

GSM Global System for Mobile Communications

Hi-Z High Impedance

IEBus Inter Equipment bus

I/O Input/Output

IrDA Infrared Data Association

LSB Least Significant Bit

MSB Most Significant Bit

NC Non-Connection

PLL Phase Locked Loop

PWM Pulse Width Modulation

SFR Special Function Registers

SIM Subscriber Identity Module

UART Universal Asynchronous Receiver/Transmitter

VCO Voltage Controlled Oscillator

A - 1

SFR Page Reference B - 1

1. Overview 1

1.1 Applications.................................................................................................1

1.2 Performance Overview................................................................................2

1.3 Block Diagram.............................................................................................4

1.4 Product Information.....................................................................................5

1.5 Pin Assignments..........................................................................................7

1.6 Pin Functions.............................................................................................10

2. Central Processing Unit (CPU) 13

2.1 Data Registers (R0, R1, R2, and R3)........................................................14

2.2 Address Registers (A0 and A1).................................................................14

2.3 Frame Base Register (FB) ........................................................................14

2.4 Interrupt Table Register (INTB).................................................................14

2.5 Program Counter (PC) ..............................................................................14

2.6 User Stack Pointer (USP) and Interrupt Stack Pointer (ISP).....................14

2.7 Static Base Register (SB)..........................................................................14

2.8 Flag Register (FLG)...................................................................................14

2.8.1 Carry Flag (C).....................................................................................14

2.8.2 Debug Flag (D)...................................................................................14

2.8.3 Zero Flag (Z).......................................................................................14

2.8.4 Sign Flag (S).......................................................................................14

2.8.5 Register Bank Select Flag (B)............................................................14

2.8.6 Overflow Flag (O)...............................................................................14

2.8.7 Interrupt Enable Flag (I)......................................................................15

2.8.8 Stack Pointer Select Flag (U).............................................................15

2.8.9 Processor Interrupt Priority Level (IPL) ..............................................15

2.8.10 Reserved Bit.......................................................................................15

3. Memory 16

3.1 R8C/18 Group...........................................................................................16

3.2 R8C/19 Group...........................................................................................17

Table of Contents

A - 2

4. Special Function Registers (SFRs) 18

5. Resets 22

5.1 Hardware Reset ........................................................................................24

5.1.1 When Power Supply is Stable............................................................24

5.1.2 Power On............................................................................................24

5.2 Power-On Reset Function.........................................................................26

5.3 Voltage Monitor 1 Reset ...........................................................................27

5.4 Voltage Monitor 2 Reset............................................................................27

5.5 Watchdog Timer Reset..............................................................................27

5.6 Software Reset..........................................................................................27

6. Programmable I/O Ports 28

6.1 Functions of Programmable I/O Ports.......................................................28

6.2 Effect on Peripheral Functions..................................................................28

6.3 Pins Other than Programmable I/O Ports..................................................28

6.4 Port settings ..............................................................................................35

6.5 Unassigned Pin Handling..........................................................................39

7. Voltage Detection Circuit 40

7.1 VCC Input Voltage.....................................................................................46

7.1.1 Monitoring Vdet1 ................................................................................46

7.1.2 Monitoring Vdet2 ................................................................................46

7.1.3 Digital Filter.........................................................................................46

7.2 Voltage Monitor 1 Reset............................................................................48

7.3 Voltage Monitor 2 Interrupt and Voltage Monitor 2 Reset.........................49

8. Processor Mode 51

8.1 Processor Modes ......................................................................................51

9. Bus 52

10. Clock Generation Circuit 53

10.1 Main Clock.................................................................................................60

10.2 On-Chip Oscillator Clocks.........................................................................61

10.2.1 Low-Speed On-Chip Oscillator Clock.................................................61

10.2.2 High-Speed On-Chip Oscillator Clock................................................61

A - 3

10.3 CPU Clock and Peripheral Function Clock................................................62

10.3.1 System Clock......................................................................................62

10.3.2 CPU Clock..........................................................................................62

10.3.3 Peripheral Function Clock (f1, f2, f4, f8, and f32)...............................62

10.3.4 fRING and fRING128..........................................................................62

10.3.5 fRING-fast...........................................................................................62

10.3.6 fRING-S..............................................................................................62

10.4 Power Control............................................................................................63

10.4.1 Standard Operating Mode..................................................................63

10.4.2 Wait Mode ..........................................................................................64

10.4.3 Stop Mode..........................................................................................66

10.5 Oscillation Stop Detection Function ..........................................................68

10.5.1 How to Use Oscillation Stop Detection Function................................68

10.6 Notes on Clock Generation Circuit............................................................70

10.6.1 Stop Mode and Wait Mode.................................................................70

10.6.2 Oscillation Stop Detection Function....................................................70

10.6.3 Oscillation Circuit Constants...............................................................70

10.6.4 High-Speed On-Chip Oscillator Clock................................................70

11. Protection 71

12. Interrupts 72

12.1 Interrupt Overview.....................................................................................72

12.1.1 Types of Interrupts..............................................................................72

12.1.2 Software Interrupts.............................................................................73

12.1.3 Special Interrupts................................................................................74

12.1.4 Peripheral Function Interrupt..............................................................74

12.1.5 Interrupts and Interrupt Vectors..........................................................75

12.1.6 Interrupt Control..................................................................................77

12.2 INT Interrupt..............................................................................................85

12.2.1 INT0 Interrupt .....................................................................................85

12.2.2 INT0 Input Filter..................................................................................86

12.2.3 INT1 Interrupt .....................................................................................87

12.2.4 INT3 Interrupt .....................................................................................88

12.3 Key Input Interrupt.....................................................................................90

12.4 Address Match Interrupt............................................................................92

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