Rohm LAPIS ML610Q305 Bedienungsanleitung

FEDL610Q306-03

Issue Date: Aug. 7, 2023

ML610Q305/306

8-bit Microcontroller with Voice Output Function

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GENERAL DESCRIPTION

ŸPlease see the “Notes” and the “Notes for product usage” in this document.

Equipped with a 8-bit CPU nX-U8/100, the ML610Q305/306 is a high-performance 8-bit CMOS microcontroller that integrates

a wide variety of peripherals such as timer, synchronous serial port, successive approximation type 10-bit A/D converter and

voice output function. The nX-U8/100 CPU is capable of executing instructions efficiently on a

one-instruction-per-clock-pulse basis through parallel processing by the 3-stage pipelined architecture. The ML610Q305/306

is also equipped with a flash memory* that has achieved low voltage and low power consumption (at read) equivalent to mask

ROM, so it is best suited to battery-driven applications such as alarm and portable devices. In addition, it has an on-chip

debugging function, which allows software debugging/rewriting with the LSI mounted on the board.

FEATURES

•CPU

−8-bit RISC CPU (CPU name: nX-U8/100)

−Instruction system: 16-bit instructions

−Instruction set: Transfer, arithmetic operations, comparison, logic operations, multiplication/division, bit

manipulations, bit logic operations, jump, conditional jump, call return stack manipulations, arithmetic shift, and so on

−On-Chip debug function

−Minimum instruction execution time

Approx 30.5 µs (@32.768kHz system clock)

Approx 0.244 µs (@4.096 MHz system clock)@VDD=2.0 to 5.5V

Approx 0.122 µs (@8.192 MHz system clock)@VDD=2.2 to 5.5V

•Internal memory

−Has 96-Kbyte flash ROM(48K ×16-bits) built in. (1 K byte of test domain that it cannot be used is included)

−Has 2-Kbyte flash ROM built in. (area in which self rewriting is possible (512byte ×4))

−Internal 1Kbyte RAM (1K ×8 bits)

•Interrupt controller

−2 non-maskable interrupt sources

Internal source: 1(Watchdog timer)

External source: 1(NMI)

−24 maskable interrupt sources

Internal source: 16(SSIO0, SSIO1, UART, I2C bus master/slave interface, Timer 0, Timer 1, Timer 2, Timer 3,

A/D converter, Voice sound reproduction, Speaker pin short detection, TBC128Hz, TBC32Hz,

TBC16Hz, TBC2Hz)

External source: 8(P80, P81, P82, P83, P84, P85, P86, P87)

•Time base counter

−Low-speed time base counter ×1 channel

−High-speed time base counter ×1 channel

•Watchdog timer

−Generates a non-maskable interrupt upon the first overflow and a system reset occurs upon the second

−Free running

−Overflow period: 4 types selectable (125ms, 500ms, 2s, and 8s at 32.768kHz)

*: This product uses SuperFlash® technology licensed from Silicon Storage Technology, Inc. SuperFlash®

is a registered trademark of Silicon Storage Technology, Inc.

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•Timers

−8 bits ×4ch (16-bit configuration available)

•Voice output function

−Voice synthesis method: 4-bit ADPCM2 / non-linear 8-bit PCM / straight 8-bit PCM /

straight 16-bit PCM / HQ-ADPCM

−Sampling frequency: 8kHz, 16kHz, 32 kHz, 10.7kHz, 21.3 kHz, 6.4kHz, 12.8kHz, 25.6 kHz

•Successive approximation type A/D converter

−10-bit A/D converter

−Input: 3ch (ch0-2:External input) (for ML610Q305) /

4ch (ch0-3:External input) (for ML610Q306)

−Conversion time: 24.4 μs per channel at 4.096MHz VDD≥2.2V

−Conversion time: 12.2 μs per channel at 8.192MHz VDD≥2.5V

−Continuous conversion / Single conversion selectable

•Synchronous serial port

−2ch

−Master/slave selectable

−LSB first/MSB first selectable

−8-bit length/16-bit length selectable

•UART

−Half-duplex × 1ch

−TXD/RXD

−Bit length, parity/no parity, odd parity/even parity, 1 stop bit/2 stop bits

−Positive logic/negative logic selectable

−Built-in baud rate generator

•I2C bus interface

−Master function: standard mode (100 kbps) and Fast mode (400 kbps)

−Slave function: standard mode (100 kbps) and Fast mode (400 kbps)

•General-purpose ports

−Input-only port ×1ch

−Output-only port ×3ch (including secondary functions)

−Input/output port ×12ch (including secondary functions)

(P40 to P42 uses also as an A/D converter input port.) (for ML610Q305)

×15ch (including secondary functions)

(P40 to P43 uses also as an A/D converter input port.) (for ML610Q306)

•Speaker amplifier(D-class) output power

−1.0W(at 5.0V)/0.45W(at 3.0V)

−Disconnection detection circuit

−Speaker pin short detection circuit

•Reset

−Reset through the RESET_N pin

−Power-on reset generation when powered on

−Reset by the watchdog timer (WDT) overflow

−PLL oscillation stop detection reset

−Low level detection (LLD) reset

•Clock

−Low-speed clock

Built-in RC oscillation (32.768 kHz)

−High-speed clock

Built-in PLL oscillation (Approx. 1.024MHz / 2.048MHz / 4.096MHz / 8.192MHz)

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•Power management

−STOP mode: Stop of oscillation (Operations of CPU and peripheral circuits are stopped.)

−HALT mode: Instruction execution by CPU is suspended (peripheral circuits are in operating states).

−Clock gear: The frequency of high-speed system clock can be changed by software (1/2, 1/4, 1/8, or 1/16 of the

oscillation clock)

−Block control function: Operation of an intact functional block circuit is powerd down. (register reset and clock stop)

•Shipment

−32-pin WQFN（P-WQFN32-0505-0.50-A63）

ML610Q305-xxxGD (blank product: ML610Q305-NNNGD)

−32-pin TQFP（P-TQFP32-0707-0.80-ZK6 or P-TQFP32-0707-0.80-Z6K6）

ML610Q305-xxxTB (blank product: ML610Q305-NNNTB)

−36-pin WQFN（P-WQFN36-0606-0.50-A63）

ML610Q306-xxxGD (blank product: ML610Q306-NNNGD)

xxx: ROM code number

•Guaranteed operating range

−Operating temperature: −40°C to 85°C

−Operating voltage: VDD = 2.0V to 5.5V, SPVDD = 2.0V to 5.5V

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BLOCK DIAGRAM

ML610Q305/306 Block Diagram

* : Secondary or tertiary function

*1:Select I/O port or A/D converter input terminal

Program Memory

（Flash）

96Kbyte

Data Flash

2Kbyte

RAM

1KByte

Interrupt

Controller

CPU (nX-U8/100)

Timing

Controller

Instruction

Decoder

BUS

Controller

Instruction

TBC

INT

8bit Timer

Data-bus

TEST0

RESET_N

OSC

POWER

VDDL

RESET &

TEST

ALU

EPSW1

～

PSW

ELR1

～

ECSR1

～

DSR/CSR

GREG

0～15

VDD

VSS

On-Chip

ICE

SSIO

SCK0*

SIN0*

SOUT0*

INT

WDT

INT

10bit-ADC

VREF

INT

LSCLK*

OUTCLK*

VOICECNT

SCK1*

SIN1*

SOUT1*

SPP

SPM

TEST1_N

LLD

SPVSS

SPVDD

AIN0 to AIN2*1 (Q305)

AIN0 to AIN3

*1(Q306)

GPIO

INT

I2C

Master/Slave

INT

SDA*

SCL*

50 to P57

D-class

Speaker

Amplifier

UART

INT

RXD0*

TXD0*

P80 to P87

P40 to P42*1(Q305) or

40 to P431 (Q306)

P20 to P22

NMI

P90(Q305) or

P90 to P92(Q306

)

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PIN CONFIGURATION

Pin Layout of ML610Q305 32pin WQFN Package(Top View)

P22/LED2 1

P20/LED0 4

P80/EXI0/SDA/SIN0 5

P81/EXI1/SCL/SCK0 6

TEST1_N 7

9TEST0

10 P82/EXI2/SOUT0

15 SPM

14 SPP

12 RESET_N

11 P83/EXI3

16 SPM

NMI 32

P87/EXI7/TXD0 31

P41/AIN1/SCK1/SCK0 27

P40/AIN0/SIN1/SIN0 28

REF

P86/EXI6/RXD0/SOUT1 30

P42/AIN2/SOUT1/SOUT0 26

24 V

DDL

23 V

22 P85/EXI5/SCK1

21 P84/EXI4/SIN1

19 SPV

17 SPV

P21/LED1 2

(TOP VIEW)

WQFN32

P90 8

13 SPP

18 SPV

20 SPV

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Pin Layout of ML610Q305 32pin TQFP Package(Top View)

P42/AIN2/SOUT1/SOUT0

（

TOP VIEW

）

TQFP32

SPM

SPP

RESET_N

P83/EXI3

P82/EXI2/SOUT0

TEST0

SPVDD

SPV

P22/LED2

P21/LED1

VSS

P20/LED

P80/EXI0/SDA/SIN0

P81/EXI1/SCL/SCK0

TEST1_N

P90

P40/AIN0/SIN1/SIN0

P41/AIN1/SCK1/SCK0

P85/EXI5/SCK1

P84/EXI4/SIN1

VDD

NMI

P87/EXI7/TXD0

P86/EXI6/RXD0/SOUT1

VREF

DDL

SPV

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Pin Layout of ML610Q306 36pin WQFN Package(Top View)

（NC）: No Connection

P20/LED0 5

11 TEST0

P86/EXI6/RXD0/SOUT1 34

25 P92

P91 1

P21/LED13

P80/EXI0/SDA/SIN0 6

P81/EXI1/SCL/SCK0 7

NMI 36

P87/EXI7/TXD0 35

P41/AIN1/SCK1/SCK0 31

P40/AIN0/SIN1/SIN0 32

REF

P42/AIN2/SOUT1/SOUT0 30

P22/LED2 2

(TOP VIEW)

WQFN36

TEST1_N 8

P43/AIN3 29

P90 9

18 SPM

10 (NC)

17 SPM

16 SPP

15 SPP

13 P83/EXI3

12 P82/EXI2/SOUT0

14 RESET_N

24 P85/EXI5/SCK1

23 P84/EXI4/SIN1

22 SPV

21 SPV

20 SPV

19 SPV

27 V

DDL

26 V

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LIST OF PIN

In the I/O column, “—” denotes a power pin, “I” an input pin, “O” an output pin, and “I/O” an input/output pin.

36pin

WQFN

32pin

WQFN

/TQFP

Primary function

Secondary/Tertiary function

Pin name I/O Description

Secondary/

Tertiary

Pin name I/O Description

15, 16 13, 14 SPP O

Positive output pin of the

built-in speaker amplifier





17, 18 15, 16 SPM O

Negative output pin of the

built-in speaker



19, 20 17, 18 SPVss 

Negative power supply pin for

built-in speaker amplifier



21, 22 19, 20 SPVDD 

Positive power supply pin for

built-in speaker amplifier



4, 26

3, 23

VSS



Negative power supply pin



27 24 VDDL 

Power supply for internal logic

(internally generated)



VDD



Positive power supply pin



33 29 VREF 

Reference power supply pin

for successive-approximation

type ADC

   

RESET_N

Reset input pin



TEST0

I/O

Input/output pin for testing



TEST1_N

Input pin for testing



36 32 NMI I

Input port,

non-maskable interrupt

   

P20/LED0

Output port / LED port

Secondary

LSCLK

Low-speed clock output

P21/LED1

Output port / LED port

Secondary

OUTCLK

high-speed clock output

P22/LED2

Output port / LED port



P90

I/O

Input port/Output port



P91

I/O

Input port/Output port



P92

I/O

Input port/Output port



32 28 P40/AIN0 I/O

Input port/Output port

/Successive-approximation

type ADC input0

Secondary SIN1 I SSIO1 data input

Tertiary SIN0 I SSIO0 data input

31 27 P41/AIN1 I/O

Input port/Output port

/Successive-approximation

type ADC input1

Secondary SCK1 I/O SSIO1 clock input/output

Tertiary SCK0 I/O SSIO0 clock input/output

30 26 P42/AIN2 I/O

Input port/Output port

/Successive-approximation

type ADC input2

Secondary SOUT1 O SSIO1 data output

Tertiary SOUT0 O SSIO0 data output

29 P43/AIN3 I/O

Input port/Output port

/Successive-approximation

type ADC input3



6 5 P80/EXI0 I/O

Input port/Output port /

External interrupt

Secondary

SDA

I/O

I2C data input/ output

Tertiary

SIN0

SSIO0 data input

7 6 P81/EXI1 I/O

Input port/Output port /

External interrupt

Secondary

SCL

I/O

I2C clock input/output

Tertiary

SCK0

I/O

SSIO0 clock input/output

12 10 P82/EXI2 I/O

Input port/Output port /

External interrupt

Tertiary SOUT0 O SSIO0 data output

13 11 P83/EXI3 I/O Input port/Output port /

External interrupt

  

23 21 P84/EXI4 I/O

Input port/Output port /

External interrupt

Tertiary SIN1 I SSIO1 data input

24 22 P85/EXI5 I/O

Input port/Output port /

External interrupt

Tertiary SCK1 I/O SSIO1 clock input/output

34 30 P86/EXI6 I/O

Input port/Output port /

External interrupt

Secondary

RXD0

UART0 data input

Tertiary

SOUT1

SSIO1 data output

35 31 P87/EXI7 I/O

Input port/Output port /

External interrupt

Secondary TXD0 O UART0 data output

Note:

The function which is not chosen is lost when either a secondary function or a tertiary function is chosen. However, when

using it as an input, read-out of an input data is possible at a port n data register (PnD).

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PIN DESCRIPTION

In the I/O column, “—” denotes a power pin, “I” an input pin, “O” an output pin, and “I/O” an input/output pin.

Pin name I/O Description

Primary/

Secondary/

Tertiary

Logic

Power supply

—

Negative power supply pin

—

Positive power supply pin

—

DDL

—

Positive power supply pin for internal logic (internally generated)

Connect the capacitor CL(1uF)( Refer to Measuring circuit 1) to

VSS

—

SPV

—

Negative power supply pin for built-in speaker amplifier

—

SPV

—

Positive power supply pin for built-in speaker amplifier

—

REF

—

Reference power supply pin for successive-approximation type ADC

—

Test

TEST0

I/O

Input/output pin for testing. Has a pull-down resistor built in.

—

Positive

TEST1_N

Input pin for testing. Has a pull-up resistor built in.

—

Negative

System

RESET_N I

Reset input pin

. When this pin is set to a “L”level, the device is

placed in system reset mode and the internal circuit is initialized

If after that this pin is set to a “H”level, program execution starts

This pin has a pull-up resistor built in.

— Negative

LSCLK O

Low-speed clock output. This function is allocated to the secondary

function of the P20 pin.

Secondary —

OUTCLK O High-speed clock output. This function is allocated to the secondary

function of the P21 pin.

Secondary —

General-purpose Output port

P20 to P22 O

General-purpose output ports.

Provided with a secondary function. Cannot be used as ports if

their secondary function is used.

Primary Positive

General-purpose Input/output port

P40 to P42 I/O

General-purpose input/output ports.

Provided with a tertiary function. Cannot be

used as ports if their

tertiary function is used.

Primary Positive

P43

I/O

General-purpose input/output port. (built into ML610Q306)

Primary Positive

P80 to P87 I/O

General-purpose input/output ports.

Provided with a secondary function or a tertiary func

tion. Cannot

be used as ports if their secondary function or tertiary function is

used.

Primary Positive

P90

I/O

General-purpose input/output ports.

Primary Positive

P91 to P92

I/O

General-purpose input/output port. (built into ML610Q306)

Primary

Positive

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Pin name I/O Description

Primary/

Secondary/

Tertiary

Logic

C bus interface

SDA I/O

I2C data input/output pin. This pin is used as the secondary

function of the P80 pin. This pin has an Nch open drain output.

When using this pin as a function of the I2C

, externally connect a

pull-up resistor.

Secondary Positive

SCL I/O

I2C clock output pin. This pin is used as the secondary function

of the P81 pin. This pin has an Nch open drain output. When

using this pin as a function of the I2C, externally connect a

pull-up resistor.

Secondary Positive

Synchronous serial (SSIO)

SIN0 I

Synchronous serial data input pin. Allocated to the tertiary

function of the P40 pin and P80 pin.

Tertiary Positive

SCK0 I/O

Synchronous serial clock input/output pin. Allocated to the

tertiary function of the P41 pin and P81 pin.

Tertiary —

SOUT0 O

Synchronous serial data output pin. Allocated to the tertiary

function of the P42 pin and P82 pin.

Tertiary Positive

SIN1 I

Synchronous serial data input pin. Allocated to the tertiary

function of the P84 pin and the secondary function of the P40

pin.

Secondary/

Tertiary Positive

SCK1 I/O

Synchronous serial clock input/output pin. Allocated to the

tertiary function of the P85 pin and the secondary func

tion of the

P41 pin.

Secondary/

Tertiary —

SOUT1 O

Synchronous serial data output pin. Allocated to the tertiary

function of the P86 pin and the secondary function of the P42

pin.

Secondary/

Tertiary Positive

UART

TXD0 O

UART data output pin. Allocated to the secondary function of the

P87 pin.

Secondary Positive

RXD0 I

UART data input pin. Allocated to the secondary function of the

P86 pin.

Secondary Positive

External interrupt

NMI I

External non-maskable interrupt input pin. The interrupt occurs

on both the rising and falling edges.

Primary Positive/

Negative

EXI0 to 7 I

External maskable interrupt input pins. It is possible, for each bit,

to specify whether the interrupt is enabled and select the

interrupt edge by software. Allocated to the primary function of

the P80 to P87 pins.

Primary Positive/

Negative

LED drive

LED0 to 2 O

Pins for LED driving. Allocated to the primary function of the P20

to P22 pins.

Primary Positive/

Negative

Voice output function

SPP

Positive output pin of the internal speaker amplifier.

—

SPM

Negative output pin of the internal speaker amplifier.

—

Successive-approximation type A/D converter

AIN0 to 2 I

Analog inputs to Ch0 to Ch2 of the successive-approximation

type A/D converter. Allocated to the primary function of the

P40

to P42 pins.

Primary —

AIN3 I

Analog inputs to Ch3 of the successive-approximation type A/D

converter.(built into ML610Q306) Allocated to the primary

function of the P43 pins.

Primary —

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