Samsung KS57C2308 Bedienungsanleitung

KS57C2308/P2308/C2316/P2316 PRODUCT OVERVIEW

1-1

1PRODUCT OVERVIEW

OVERVIEW

The KS57C2308/C2316 single-chip CMOS microcontroller has been designed for high performance using

Samsung's newest 4-bit CPU core, SAM47 (Samsung Arrangeable Microcontrollers).

With features such as LCD direct drive capability, 8-bit timer/counter, and serial I/O, the KS57C2308/C2316 offer

an excellent design solution for a wide variety of applications that require LCD functions.

Up to 40 pins of the 80-pin QFP package can be dedicated to I/O. Six vectored interrupts provide fast response

to internal and external events. In addition, the KS57C2308/C2316's advanced CMOS technology provides for

low power consumption and a wide operating voltage range.

OTP

The KS57C2308/C2316 microcontroller is also available in OTP (One Time Programmable) version,

KS57P2308/P2316. KS57P2308/P2316 microcontroller has an on-chip 8/16-Kbyte one-time-programmable

EPROM instead of masked ROM. The KS57P2308/P2316 is comparable to KS57C2308/C2316, both in function

and in pin configuration.

PRODUCT OVERVIEW KS57C2308/P2308/C2316/P2316

1-2

FEATURES

Memory

–512 ×4-bit RAM

–8 K ×8-bit ROM (KS57C2308/P2308)

–16 K ×8-bit ROM (KS57C2316/P2316)

I/O Pins

–Input only: 8 pins

–I/O: 24 pins

–Output: 8 pins sharing with segment driver

outputs

LCD Controller/Driver

–Maximum 16-digit LCD direct drive capability

–32 segment, 4 common pins

–Display modes: Static, 1/2 duty (1/2 bias),

1/3 duty (1/2 or 1/3 bias), 1/4 duty (1/3 bias)

8-Bit Basic Timer

–Programmable interval timer

–Watchdog timer

8-Bit Timer/Counter 0

–Programmable 8-bit timer

–External event counter

–Arbitrary clock frequency output

–Serial I/O interface clock generator

Watch Timer

–Real-time and interval time measurement

–Four frequency outputs to BUZ pin

–Clock source generation for LCD

8-Bit Serial I/O Interface

–8-bit transmit/receive mode

–8-bit receive only mode

–LSB-first or MSB-first transmission selectable

–Internal or external clock source

Bit Sequential Carrier

–Support 16-bit serial data transfer in arbitrary

format

Interrupts

–Three internal vectored interrupts

–Three external vectored interrupts

–Two quasi-interrupts

Memory-Mapped I/O Structure

–Data memory bank 15

Two Power-Down Modes

–Idle mode (only CPU clock stops)

–Stop mode (main or sub system oscillation stops)

Oscillation Sources

–Crystal, ceramic, or RC for main system clock

–Crystal or external oscillator for subsystem clock

–Main system clock frequency: 4.19 MHz (typical)

–Subsystem clock frequency: 32.768 kHz

–CPU clock divider circuit (by 4, 8, or 64)

Instruction Execution Times

–0.95, 1.91, 15.3 µs at 4.19 MHz (main)

–122 µs at 32.768 kHz (subsystem)

Operating Temperature

–– 40 °Cto 85 °C

Operating Voltage Range

–1.8 Vto 5.5 V

Package Type

– 80-pin QFP

KS57C2308/P2308/C2316/P2316 PRODUCT OVERVIEW

1-3

BLOCK DIAGRAM

Interrupt

Control

Block

Instruction

Program

Counter

Program

Status Word

Stack

Pointer

Arithmetic and Logic Unit

Instruction Decoder

Clock

RESET XIN

XTIN

Internal

Interrupts

INT0, INT1,INT2

P3.0/LCDCK

P3.1/LCDSY

P3.2

P3.3

I/O Port 3

512 x 4-Bit

Data

Memory

8/16-Kbyte

Program

Memory

LCD Drive/

Controller

BIAS

VLC0-VLC2

LCDCK/P3.0

LCDSY/P3.1

COM0-COM3

SEG0-SEG23

P8.0-P8.7/

SEG24-SEG31

P2.3/BUZ

XOUT

XTOUT

P6.0-P6.3/

KS0-KS3 I/O Port 6

P7.0-P7.3/

KS4-KS7 I/O Port 7

P4.0-P4.3 I/O Port 3

P5.0-P5.3 I/O Port 4

8-Bit Timer/

Counter 0

P1.3/TCL0

P2.0/TCLO0

P8.0-P8.7/

SEG24-SEG31 I/O Port 8

P1.0/INT0

P1.1/INT1

P1.2/INT2

P1.3/TCL0

Input Port 1

P2.0/TCLO0

P2.1

P2.2/CLO

P2.3/BUZ

I/O Port 2

Basic

Timer

4-Bit

Accumulator

FLAGS

P0.0/INT4

P0.1/SCK

P0.2/SO

P0.3/SI

I/O Port 0

Serial I/O

Port

P0.2

/SO P0.3

/SI

P0.1

/SCK

Watch-Dog

Timer Watch

Timer

Figure 1-1.KS57C2308/C2316 Simplified Block Diagram

PRODUCT OVERVIEW KS57C2308/P2308/C2316/P2316

1-4

PIN ASSIGNMENTS

SEG19

SEG20

SEG21

SEG22

SEG23

P8.0/SEG24

P8.1/SEG25

P8.2/SEG26

P8.3/SEG27

P8.4/SEG28

P8.5/SEG29

P8.6/SEG30

P8.7/SEG31

P7.3/KS7

P7.2/KS6

P7.1/KS5

P7.0/KS4

P6.3/KS3

P6.2/KS2

P6.1/KS1

P6.0/KS0

P5.3

P5.2

P5.1

KS57C2308

KS57C2316

(TOP VIEW)

SEG2

SEG1

SEG0

COM0

COM1

COM2

COM3

BIAS

VLC0

VLC1

VLC2

VDD

VSS

XOUT

XIN

TEST

XTIN

XTOUT

RESET

P0.0/INT4

P0.1/SCK

P0.2/SO

P0.3/SI

P1.0/INT0

P1.1/INT1

P1.2/INT2

P1.3/TCL0

P2.0/TCLO0

P2.1

P2.2/CLO

P2.3/BUZ

P3.0/LCDCK

P3.1/SCDSY

P3.2

P3.3

P4.0

P4.1

P4.2

P4.3

P5.0

SEG3

SEG4

SEG5

SEG6

SEG7

SEG8

SEG9

SEG10

SEG11

SEG12

SEG13

SEG14

SEG15

SEG16

SEG17

SEG18

Figure 1-2.KS57C2308/C2316 80-QFP Pin Assignment Diagram

KS57C2308/P2308/C2316/P2316 PRODUCT OVERVIEW

1-5

PIN DESCRIPTIONS

Table 1-1. KS57C2308/C2316 Pin Descriptions

Pin Name Pin

Type Description Number Share

Pin Reset

Value Circuit

Type

P0.0

P0.1

P0.2

P0.3

I/O

4-bit input port.

1-bit and 4-bit read and test are possible.

4-bit pull-up resistors are software assignable.

INT4

SCK

Input A-1

D *

A-1

P1.0

P1.1

P1.2

P1.3

I4-bit input port.

1-bit and 4-bit read and test are possible.

4-bit pull-up resistors are software assignable.

INT0

INT1

INT2

TCL0

Input A-1

P2.0

P2.1

P2.2

P2.3

I/O 4-bit I/O port.

1-bit and 4-bit read/write and test are possible.

4-bit pull-up resistors are software assignable.

TCLO0

–

CLO

BUZ

Input D

P3.0

P3.1

P3.2

P3.3

I/O 4-bit I/O port.

1-bit and 4-bit read/write and test are possible.

Each individual pin can be specified as input

or output. 4-bit pull-up resistors are software

assignable.

LCDCK

LCDSY Input D

P4.0–

P4.3

P5.0–

P5.3

I/O 4-bit I/O ports. N-channel open-drain output up

to 5 V. 1-, 4-, and 8-bit read/write and test are

possible. Ports 4 and 5 can be paired to

support 8-bit data transfer. 4-bit pull-up

resistors are software assignable.

36–43 – Input E

P6.0–

P6.3

P7.0–

P7.3

I/O 4-bit I/O ports. Port 6 pins are individually

software configurable as input or output. 1-bit

and 4-bit read/write and test are possible. 4-bit

pull-up resistors are software assignable. Ports

6 and 7 can be paired to enable 8-bit data

transfer.

44–51 KS0–KS3

KS4–KS7 Input D *

P8.0–

P8.7 OOutput port for 1-bit data (for use as CMOS

driver only) 59–52 SEG24–

SEG31 Output H-16

SEG0–

SEG23 OLCD segment signal output 3–1,

80–60 –Output H-15

SEG24–

SEG31 OLCD segment signal output 59–52 P8.0–P8.7 Output H-16

COM0–

COM3 OLCD common signal output 4–7 – Output H-15

VLC0–VLC2 –LCD power supply. Voltage dividing resistors

are assignable by mask option 9–11 SCLK

SDAT – –

BIAS –LCD power control 8 – – –

LCDCK I/O LCD clock output for display expansion 32 P3.0 Input D

PRODUCT OVERVIEW KS57C2308/P2308/C2316/P2316

1-6

Table 1-1. KS57C2308/C2316 Pin Descriptions (Continued)

Pin Name Pin

Type Description Number Share

Pin Reset

Value Circuit

Type

LCDSY I/O LCD synchronization clock output for LCD

display expansion 33 P3.1 Input D

TCL0 I/O External clock input for timer/counter 0 27 P1.3 Input A-1

TCLO0 I/O Timer/counter 0 clock output 28 P2.0 Input D

SI ISerial interface data input 23 P0.3 Input A-1

SO I/O Serial interface data output 22 P0.2 Input D *

SCK I/O Serial I/O interface clock signal 21 P0.1 Input D *

INT0

INT1 IExternal interrupts. The triggering edge for

INT0 and INT1 is selectable. Only INT0 is

synchronized with the system clock.

25 P1.0

P1.1 Input A-1

INT2 IQuasi-interrupt with detection of rising edge

signals. 26 P1.2 Input A-1

INT4 IExternal interrupt input with detection of rising

or falling edge 20 P0.0 Input A-1

KS0–KS7 I/O Quasi-interrupt inputs with falling edge

detection. 44–51 P6.0–P7.3 Input D *

CLO I/O CPU clock output 30 P2.2 Input D

BUZ I/O 2, 4, 8 or 16 kHz frequency output for buzzer

sound with 4.19 MHz main system clock or

32.768 kHz subsystem clock.

31 P2.3 Input D

XIN,

XOUT –Crystal, ceramic or RC oscillator pins for main

system clock. (For external clock input, use

XIN and input XIN‘s reverse phase to XOUT)

15,14 – – –

XTIN,

XTOUT –Crystal oscillator pins for subsystem clock.

(For external clock input, use XTIN and input

XTIN's reverse phase to XTOUT)

17,18 – – –

VDD –Main power supply 12 – – –

VSS –Ground 13 – – –

RESET –Reset signal 19 – Input B

TEST –Test signal input (must be connected to VSS)16 – – –

NOTES:

1. Pull-up resistors for all I/O ports are automatically disabled if they are configured to output mode.

2. D *Type has a schmitt trigger circuit at input.

KS57C2308/P2308/C2316/P2316 PRODUCT OVERVIEW

1-7

PIN CIRCUIT DIAGRAMS

VDD

P-CHANNEL

N-CHNNEL

Figure 1-3.Pin Circuit Type A

SCHMITT TRIGGER

VDD

P-CHANNEL

PULL-UP

RESISTOR

ENABLE

Figure 1-4.Pin Circuit Type A-1 (P1, P0.0, P0.3)

VDD

P-CHANNEL

DATA

OUTPUT

DISABLE

N-CHANNEL

OUT

Figure 1-5.Pin Circuit Type C

P-CHANNEL

PULL-UP

RESISTOR

ENABLE

DATA

OUTPUT

DISABLE

CIRCUIT TYPE A

I/O

VDD

CIRCUIT

TYPE C

Figure 1-6.Pin Circuit Type D

(P0.1, P0.2, P2, P3, P6, P7)

PRODUCT OVERVIEW KS57C2308/P2308/C2316/P2316

1-8

DATA

OUTPUT

ENABLE

VDD

P-CH

RESISTOR

ENABLE

N-CH

PULL-UP

RESISTOR

I/O

CIRCUIT TYPE A

VDD

PNE

Figure 1-7.Pin Circuit Type E (P4, P5)

VLC0

VLC1

LCD SEGMENT/

COMMON DATA

VLC2

OUT

Figure 1-8.Pin Circuit Type H-15 (SEG/COM)

VLC0

VLC1

LCD SEGMENT/

& PORT 8 DATA

VLC2

VDD

OUT

Figure 1-9.Pin Circuit Type H-16 (P8)

SCHMITT TRIGGER

VDD

Figure 1-10.Pin Circuit Type B (RESET)

KS57C2308/P2308/C2316/P2316 ADDRESS SPACES

2-1

2ADDRESS SPACES

PROGRAM MEMORY (ROM)

OVERVIEW

ROM maps for KS57C2 308/C2316 devices are mask programmable at the factory. KS57C2308 has 8K ×8-bit

program memory and KS57C2316 has 16K ×8-bit program memory, aside from the differences in the ROM size

the two products are identical in other features. In its standard configuration, the device's 8,192 ×8-bit (16,384 ×

8-bit)program memory has four areas that are directly addressable by the program counter (PC):

—12-byte area for vector addresses

—96-byte instruction reference area

—20-byte general-purpose area

—8064-byte general-purpose area (KS57C2308)

—16256-byte general-purpose area (KS57C2316)

General-Purpose Program Memory

Two program memory areas are allocated for general-purpose use: One area is 20 bytes in size and the other is

8,064-bytes (16,256-bytes).

Vector Addresses

A 12-byte vector address area is used to store the vector addresses required to execute system resets and

interrupts. Start addresses for interrupt service routines are stored in this area, along with the values of the

enable memory bank (EMB) and enable register bank (ERB) flags that are used to set their initial value for the

corresponding service routines. The 16-byte area can be used alternately as general-purpose ROM.

REF Instructions

Locations 0020H–007FH are used as a reference area (look-up table) for 1-byte REF instructions. The REF

instruction reduces the byte size of instruction operands. REF can reference one 2-byte instruction, two 1-byte

instructions, and one 3-byte instruction which are stored in the look-up table. Unused look-up table addresses can

be used as general-purpose ROM.

Table 2-1. Program Memory Address Ranges

ROM Area Function Address Ranges Area Size (in Bytes)

Vector address area 0000H–000BH12

General-purpose program memory 000CH–001FH 20

REF instruction look-up table area 0020H–007FH 96

General-purpose program memory 0080H–1FFFH (KS57C2308)

0080H–3FFFH (KS57C2316) 8064 (KS57C2308)

16256 (KS57C2316)

ADDRESS SPACES KS57C2308/P2308/C2316/P2316

2-2

GENERAL-PURPOSE MEMORY AREAS

The 20-byte area at ROM locations 000CH–001FH and the 8,064-byte (16,256-byte)area at ROM locations

0080H–1FFFH (0080H–3FFFH) are used as general-purpose program memory. Unused locations in the vector

address area and REF instruction look-up table areas can be used as general-purpose program memory.

However, care must be taken not to overwrite live data when writing programs that use special-purpose areas of

the ROM.

VECTOR ADDRESS AREA

The 12-byte vector address area of the ROM is used to store the vector addresses for executing system resets

and interrupts. The starting addresses of interrupt service routines are stored in this area, along with the enable

memory bank (EMB) and enable register bank (ERB) flag values that are needed to initialize the service routines.

12-byte vector addresses are organized as follows:

NOTE: PC13 is used for KS57C2316/P2316 microcontroller.

To set up the vector address area for specific programs, use the instruction VENTn. The programming tips on the

next page explain how to do this.

VECTOR ADDRESS AREA

(12 Bytes)

GENERAL-PURPOSE AREA

(20 Bytes)

INSTRUCTION

REFERENCE

AREA

GENERAL-PURPOSE AREA

(8,064 Bytes/

16,256 Bytes)

1FFFH

3FFFH

0080H

007FH

0020H

001FH

000CH

000BH

0000H

Figure 2-1. ROM Address Structure

76543210

RESET

INTB/INT4

INT0

INT1

INTT0

0000H

0002H

0004H

0006H

0008H

000AH

INTS

Figure 2-2.Vector Address Structure

EMB ERB PC13 (note) PC12 PC11 PC10 PC9 PC8

PC7 PC6 PC5 PC4 PC3 PC2 PC1 PC0

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