Samsung FLEX-MUXONENAND KFKAGH6Q4M Bedienungsanleitung

Flex-MuxOneNAND4G(KFM4GH6Q4M-DEBx)

- 1 -

FLASH MEMORY

Flex-MuxOneNAND8G(KFN8GH6Q4M-DEBx)

Flex-MuxOneNAND16G(KFKAGH6Q4M-DEBx)

KFM4GH6Q4M

KFN8GH6Q4M

KFKAGH6Q4M

4Gb Flex-MuxOneNAND M-die

* Samsung Electronics reserves the right to change products or specification without notice.

INFORMATION IN THIS DOCUMENT IS PROVIDED IN RELATION TO SAMSUNG PRODUCTS,

AND IS SUBJECT TO CHANGE WITHOUT NOTICE.

NOTHING IN THIS DOCUMENT SHALL BE CONSTRUED AS GRANTING ANY LICENSE,

EXPRESS OR IMPLIED, BY ESTOPPEL OR OTHERWISE,

TO ANY INTELLECTUAL PROPERTY RIGHTS IN SAMSUNG PRODUCTS OR TECHNOLOGY. ALL

INFORMATION IN THIS DOCUMENT IS PROVIDED

ON AS "AS IS" BASIS WITHOUT GUARANTEE OR WARRANTY OF ANY KIND.

1. For updates or additional information about Samsung products, contact your nearest Samsung office.

2. Samsung products are not intended for use in life support, critical care, medical, safety equipment, or similar

applications where Product failure could result in loss of life or personal or physical harm, or any military or

defense application, or any governmental procurement to which special terms or provisions may apply.

Flex-MuxOneNAND‚ is a trademark of Samsung Electronics Company, Ltd. Other names and brands may be

claimed as the property of their rightful owners.

Flex-MuxOneNAND4G(KFM4GH6Q4M-DEBx)

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FLASH MEMORY

Flex-MuxOneNAND8G(KFN8GH6Q4M-DEBx)

Flex-MuxOneNAND16G(KFKAGH6Q4M-DEBx)

Revision History

Document Title

Flex-MuxOneNAND

Revision History

Revision No.

0.0

0.1

History

1. Initial issue.

1. Corrected errata.

2. Chapter 1.3 Product Features revised.

3. Chapter 2.8.16 Start Address8 Register F107 revised.

4. Chapter 2.8.18 Command Register F220h revised.

5. Chapter 2.8.19 System Configuration 1 Register F221h corrected errata.

6. Chapter 2.8.21 Controller Status Register F240h revised.

7. Chapter 2.8.22 Interrupt Status Register F241h revised.

8. Chapter 3.1.2 Load Data Into Buffer Command.

9. Chapter 3.3 Reset Mode Operation revised.

10. Chapter 3.3.1 Cold Reset Mode Operation revised.

11. Chapter 3.4.3 NAND Array Write Protection States corrected errata.

12. Chapter 3.4.3.1 Unlocked NAND Array Write Protection State.

13. Chapter 3.4.4 Data Protection Operation Flow Diagram revised.

14. Chapter 3.4.4 All Block Unlock Flow Diagram revised.

15. Chapter 3.6 Load Operation Flow Chart Diagram revised.

16. Chapter 3.6.1 Superload Operation revised.

17. Chapter 3.6.2 LSB Page Recovery Read updated.

18. Chapter 3.8 Synchronous Write revised.

19. Chapter 3.9 Program Operation Flow Diagram revised.

Program Interleave Flow Chart updated.

20. Chapter 3.9.1 Cache Program Operation Flow diagram revised.

21. Chapter 3.9.2 Interleave Cache Program Operation revised.

22. Chapter 3.10 Copy-Back Program Operation with Random Data Input

Flow Chart revised.

23. Chapter 3.11.1 Block Erase Operation Flow Chart revised.

Erase Interleave Flow Chart updated.

24. Chapter 3.12 Partition Information Block corrected errata.

25. Chapter 3.12.1 PI Block Load Operation revised.

26. Chapter 3.12.2 PI Block Boundary Information setting updated.

27. OTP Operation revised.

28. Chapter 3.13.2 OTP Block Program Operation revised.

29. Chapter 3.13.3 OTP Block Lock Operation and Flow Chart revised.

30. Chapter 3.13.4 1st Block OTP Lock Operation revised.

31. Chapter 3.13.5 OTP and 1st Block OTP Lock Operation revised.

32. Chapter 3.16 Invalid Block Operation revised.

33. Chapter 4.1 Absolute Maximum Ratings revised.

34. Chapter 4.2 Operating Conditions revised.

35. Chapter 4.3 DC Characteristics revised.

36. Chapter 5.1 AC Test Conditions revised.

37. Chapter 5.3 Valid Block Characteristics revised.

38. Chapter 5.4 AC Characteristics for Synchronous Burst Read revised.

39. Chapter 5.8 AC Characteristics for Burst Write Operation revised.

40. Chapter 5.9 AC Characteristics for Load/Program/Erase Performance

revised.

41. Chapter 6.15 Cold Reset Timing revised.

42. Chapter 7.3 Partition of Flex-MuxOneNAND corrected errata.

Draft Date

Nov. 28, 2006

Aug. 13, 2007

Remark

Advanced

Preliminary

Flex-MuxOneNAND4G(KFM4GH6Q4M-DEBx)

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FLASH MEMORY

Flex-MuxOneNAND8G(KFN8GH6Q4M-DEBx)

Flex-MuxOneNAND16G(KFKAGH6Q4M-DEBx)

Revision History

Revision No.

0.2

1.0

1.1

History

1. Corrected errata.

2. Chapter 2.1 Detailed Product Description revised.

3. Chapter 2.2 Definitions revised.

4. Chapter 2.8.3 Device ID Register F001h(R) revised.

5. Chapter 2.8.8 Technology Register F006h(R) revised.

6. Chapter 2.8.10 Start Address2 Register F101h(R/W) revised.

7. Chapter 2.8.16 Start Address8 Register F107h(R/W) revised.

8. Chapter 2.8.18 Command Register F220h(R/W) revised.

9. Chapter 2.8.22 Interrupt Status Register F241h(R/W) revised.

10. Chapter 3.1 Command Based Operation revised.

11. Chapter 3.3 Reset Mode Operation revised.

12. Chapter 3.4.3 NAND Array Write Protection States revised.

13. Chapter 3.4.3.1 Unlocked NAND Array Write Protection State revised.

14. Chapter 3.4.3.3 Locked-tight NAND Array Write Protection State

revised.

15. Chapter 3.4.4 NAND Flash Array Write Protection State Diagram

revised.

16. Chapter 3.6.2 LSB Page Recovery Read revised.

17. Chapter 3.7.2 Synchronous Read Mode Operation revised.

18. Chapter 3.7.2.1 Continuous Linear Burst Read Operation revised.

19. Chapter 3.9 Program Operation revised.

20. Chapter 3.9.1 Cache Program Operation revised.

21. Chapter 3.9.2 Interleave Cache Program Operation revised.

22. Chapter 3.11.1 Block Erase Operation revised.

23. Chapter 3.11.2 Erase Suspend / Erase Resume Operation revised.

24. Chapter 3.12 Partition Information (PI) Block(SLC Only) revised.

25. Chapter 3.12.1 PI Block Boundary Information setting revised.

26. Chapter 3.12.1.1 PI Block Access mode entry revised.

27. Chapter 3.12.1.2 PI Block Erase revised.

28. Chapter 3.12.1.3 PI Block Program Operation revised.

29. Chapter 3.12.1.4 PI Update revised.

30. Chapter 3.13 OTP Operation (SLC only) revised.

31. Chapter 3.13.1 OTP Block Load Operation revised.

32. Chapter 3.16.2 Invalid Block Replacement Operation revised.

33. Chapter 5.5 AC Characteristics for Asynchronous Read revised.

34. Chapter 6.3 Asynchronous Read(VA Transition Before AVD Low) tOEH

removed.

35. Chapter 6.4 Asynchronous Read(VA Transition After AVD Low) tOEH

removed.

36. Chapter 7.4 DDP and QDP Description inserted.

1. New Format(font size, color etc.)

2. Corrected errata.

3. Added a comment(Chapter 3.11.1 & 3.12.1.2 & 3.12.1.3 & 3.12.1.4)

4. Chapter 2.8.17 Start Buffer Register F200h (R/W) revised.

5. Chapter 3.1.2 Load Data Into Buffer Command revised.

6. Chapter 3.12.2 PI Block Load Operation revised.

7. Chapter 4.3 DC Characteristics revised.

1. Chapter 3.6.2 LSB Page Recovery read flow chart revised.

2. Chapter 3.9.1 Cache Program Operation revised.

3. Chapter 3.13.1 OTP Block Read Operation Flow Chart revised.

4. Chapter 3.13.2 OTP Block Program Operation Flow Chart revised.

5. Chapter 3.13.3 OTP Block Lock Operation Flow Chart revised.

6. Chapter 3.13.4 1st Block OTP Lock Operation revised.

7. Chapter 3.13.5 OTP and 1st Block OTP Lock Operation Flow Chart

revised.

Draft Date

Oct. 30, 2007

Feb. 04, 2008

Aug. 07, 2008

Remark

Preliminary

Final

Flex-MuxOneNAND4G(KFM4GH6Q4M-DEBx)

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FLASH MEMORY

Flex-MuxOneNAND8G(KFN8GH6Q4M-DEBx)

Flex-MuxOneNAND16G(KFKAGH6Q4M-DEBx)

1.0 INTRODUCTION

This specification contains information about the Samsung Electronics Company Flex-MuxOneNAND‚ Flash memory product family. Sec-

tion 1.0 includes a general overview, revision history, and product ordering information.

Section 2.0 describes the Flex-MuxOneNAND device. Section 3.0 provides information about device operation. Electrical specifications and

timing waveforms are in Sections 4.0 through 6.0. Section 7.0 provides additional application and technical notes pertaining to use of the Flex-

MuxOneNAND. Package dimensions are found in Section 8.0

1.1 Ordering Information

Density Part No. VCC(core & IO) Temperature PKG

4Gb KFM4GH6Q4M-DEBx 1.8V(1.7V~1.95V) Extended 63FBGA(LF)

8Gb KFN8GH6Q4M-DEBX 1.8V(1.7V~1.95V) Extended 63FBGA(LF)

16Gb(TBD) KFKAGH6Q4M-DEBX 1.8V(1.7V~1.95V) Extended 63FBGA(LF)

K F x x H 6 Q 4 M - D E x x

Samsung

OneNAND Memory

Device Type

M : Mux type Single Chip

N : Mux type Dual Chip

K: Mux type Quad Chip

Density

4G : 4Gb

8G : 8Gb

AG : 16Gb(TBD)

Operating Temperature Range

E = Extended Temp. (-30 C to 85 C)

Page Architecture

4: 4KB Page

Version

1st Generation

Product Line designator

B : Include Bad Block

D : Daisy Sample

Operating Voltage Range

Q : 1.8V(1.7 V to 1.95V)

Package

D : FBGA(Lead Free)

Organization

6: x16 Organization

Speed

6 : 66MHz

8 : 83MHz

Technology

H : Flex

Flex-MuxOneNAND4G(KFM4GH6Q4M-DEBx)

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FLASH MEMORY

Flex-MuxOneNAND8G(KFN8GH6Q4M-DEBx)

Flex-MuxOneNAND16G(KFKAGH6Q4M-DEBx)

1.2 General Overview

Flex-MuxOneNANDis a monolithic integrated circuit with a NAND Flash array using a NOR Flash interface.

The chip integrates system features including:

A BootRAM(1KB) and bootloader

4KB DataRAM buffers

A High-Speed x16 Host Interface

On-chip Error Correction

On-chip NOR interface controller

This on-chip integration enables system designers to reduce external system logic and use high-density NAND Flash in applications that

would otherwise have to use more NOR components.

Flex-MuxOneNAND takes advantage of the higher performance NAND program time, low power, and high density and combines it with the

synchronous read performance of NOR. The NOR Flash host interface makes Flex-MuxOneNAND an ideal solution for mobile applications

that have large, advanced multimedia applications and operating systems and need high performance.

When integrated into a Samsung Multi-Chip-Package with Samsung Mobile DDR SDRAM, designers can complete a high-performance, small

footprint solution.

The device operates up to a maximum host-driven clock frequency of 66MHz / 83MHz for synchronous reads at Vcc(or Vccq. Refer to chapter

4.2) with 4~7-clock latency. Appropriate wait cycles are determined by programmable read latency.

Flex-MuxOneNAND provides for multiple sector read operations by assigning the number of sectors to be read in the sector counter register.

The device includes one block-sized OTP (One Time Programmable) area and user-controlled 1st block OTP(Block 0) that can be used to

increase system security or to provide identification capabilities.

Flex-MuxOneNAND4G(KFM4GH6Q4M-DEBx)

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FLASH MEMORY

Flex-MuxOneNAND8G(KFN8GH6Q4M-DEBx)

Flex-MuxOneNAND16G(KFKAGH6Q4M-DEBx)

1.3 Product Features

Device Architecture

Design Technology:

Supply Voltage:

Host Interface:

5KB Internal BufferRAM:

NAND Array:

Device Performance

Host Interface Type:

Programmable Burst Read Latency:

Multiple Reset Modes:

Low Power Dissipation:

Reliable CMOS Floating-Gate Technology

System Hardware

Voltage detector generating internal reset signal from Vcc

Hardware reset input (RP)

Data Protection Modes

User-controlled One Time Programmable(OTP) area

Internal 4bit ECC

Internal Bootloader supports Booting Solution in system

Handshaking Feature

Detailed chip information

Package size

4G products

8G products

16G products(TBD)

M die

1.8V (1.7V ~ 1.95V)

16 bit

1KB BootRAM, 4KB DataRAM

SLC : (4K+128)B Page Size

(256K+8K)B Block Size (64pages)

MLC : (4K+128)B Page Size

(512K+16K)B Block Size (128pages)

Synchronous Burst Read

- Up to 66MHz / 83MHz clock frequency

- Linear Burst 4-, 8-, 16-, 32-words with wrap around

- Continuous 1K words Sequential Burst

Synchronous Write

- Up to 66MHz / 83MHz clock frequency

- Linear Burst 4-, 8-, 16-, 32-, 1K-words with wrap around

- Continuous 1K words Sequential Burst

Asynchronous Random Read

- 76ns access time

Asynchronous Random Write

Latency 3,4(Default),5,6 and 7

1~40MHz : Latency 3 available

1~66MHz : Latency 4,5,6 and 7 available

Over 66MHz : Latency 6,7 available

Cold/Warm/Hot/NAND Flash Core Reset

Typical Power,

- Standby current : 10uA (Single)

- Synchronous Burst Read current(66MHz/83MHz, single) : 20/25mA

- Synchronous Burst Write current(66MHz/83MHz, single) : 20/25mA

- Load current : 50mA

- Program current : 35mA

- Erase current : 40mA

- Endurance : 50K Program/Erase Cycles (SLC)

10K Program/Erase Cycles (MLC)

- Data Retention : 10 Years(SLC) /10 Years(MLC)

- Write Protection for BootRAM

- Write Protection for NAND Flash Array

- Write Protection during power-up

- Write Protection during power-down

- INT pin indicates Ready / Busy

- Polling the interrupt register status bit

- by ID register

63ball, 10mm x 13mm x max 1.0mmt , 0.8mm ball pitch FBGA

63ball, 10mm x 13mm x max 1.2mmt , 0.8mm ball pitch FBGA

63ball, 10mm x 13mm x max 1.4mmt , 0.8mm ball pitch FBGA (TBD)

Flex-MuxOneNAND4G(KFM4GH6Q4M-DEBx)

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FLASH MEMORY

Flex-MuxOneNAND8G(KFN8GH6Q4M-DEBx)

Flex-MuxOneNAND16G(KFKAGH6Q4M-DEBx)

2.0 DEVICE DESCRIPTION

2.1 Detailed Product Description

The Flex-MuxOneNAND is an advanced generation, high-performance MLC NAND-based Flash memory(Which can be programmed as both

SLC and MLC).

It integrates on-chip a convertible(SLC and MLC) NAND Flash Array memory with two independent data buffers, boot RAM buffer, a page

buffer for the Flash array, and a one-time-programmable block.

The combination of these memory areas enable high-speed pipelining of reads from hostBufferRAMPage Bufferand NAND Flash Array.

Clock speeds up to 66MHz / 83MHz with a x16 wide I/O yields a 83MByte/second in SLC and 71MByte/second in MLC read bandwidth

The Flex-MuxOneNAND also includes a Boot RAM and boot loader. This enables the device to efficiently load boot code at device startup

from the NAND Array without the need for off-chip boot device.

One block of the NAND Array is set aside as an OTP memory area, and 1st Block (Block 0) can be used as OTP area. This area, available to

the user, can be configured and locked with secured user information.

On-chip controller interfaces enable the device to operate in systems without NAND Host controllers.

2.2 Definitions

B (capital letter) Byte, 8bits

W (capital letter) Word, 16bits

b (lower-case letter) Bit

ECC Error Correction Code

Calculated ECC ECC that has been calculated during a load or program access

Written ECC ECC that has been stored as data in the NAND Flash array or in the BufferRAM

BufferRAM On-chip internal buffer consisting of BootRAM and DataRAM

BootRAM A 1KB portion of the BufferRAM reserved for Boot Code buffering

DataRAM A 4KB portion of the BufferRAM reserved for Data buffering (2KB x2)

Sector Part of a Page of which 512B is the main data area and 16B is the spare data area.

Data unit Possible data unit to be read from memory to BufferRAM or to be programmed to memory.

- 4224B of which 4096 is in main area and 128B in spare area

DDP Dual Die Package

QDP Quad Die Package

OTP One Time Programmable

Flex-MuxOneNAND4G(KFM4GH6Q4M-DEBx)

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FLASH MEMORY

Flex-MuxOneNAND8G(KFN8GH6Q4M-DEBx)

Flex-MuxOneNAND16G(KFKAGH6Q4M-DEBx)

2.3 Pin Configuration

2.3.1 4Gb (KFM4GH6Q4M) / 8Gb (KFN8GH6Q4M)

(TOP VIEW, Balls Facing Down)

63ball FBGA Flex-MuxOneNAND Chip

63ball, 10mm x 13mm x max 1.0mmt , 0.8mm ball pitch FBGA(4Gb)

63ball, 10mm x 13mm x max 1.2mmt , 0.8mm ball pitch FBGA (8Gb)

NC NC NC NC

NC NC NC

NC NC NC NC

INT NC NC NC NC NC

WE RP ADQ1 VSS VSS ADQ2

ADQ3 ADQ7 ADQ14 OE ADQ6 VCC

ADQ8 ADQ11 ADQ4 ADQ5 ADQ12 VCC

ADQ0 NC ADQ15 ADQ10 ADQ9

CE ADQ13 NC NC NC

AVD NC NC NC

NC NC NC NC NC

Core

CLK

RDY

Flex-MuxOneNAND4G(KFM4GH6Q4M-DEBx)

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FLASH MEMORY

Flex-MuxOneNAND8G(KFN8GH6Q4M-DEBx)

Flex-MuxOneNAND16G(KFKAGH6Q4M-DEBx)

2.3.2 16Gb Product (KFKAGH6Q4M) (TBD)

(TOP VIEW, Balls Facing Down)

63ball FBGA OneNAND Chip

63ball, 10mm x 13mm x max 1.4mmt , 0.8mm ball pitch FBGA

NC NC NC NC

NC NC NC

CE2

INT2

NC NC NC NC

INT1 NC NC NC NC NC

WE RP ADQ1 VSS VSS ADQ2

ADQ3 ADQ7 ADQ14 OE ADQ6 VCC

ADQ8 ADQ11 ADQ4 ADQ5 ADQ12 VCC

ADQ0 NC ADQ15 ADQ10 ADQ9

CE1 ADQ13 NC NC

AVD NC NC NC

NC NC NC NC

Core

CLK

RDY

Flex-MuxOneNAND4G(KFM4GH6Q4M-DEBx)

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FLASH MEMORY

Flex-MuxOneNAND8G(KFN8GH6Q4M-DEBx)

Flex-MuxOneNAND16G(KFKAGH6Q4M-DEBx)

2.4 Pin Description

NOTE :

Do not leave power supply(Vcc-Core/Vcc-IO, VSS) disconnected.

Pin Name Type Nameand Description

Host Interface

ADQ15~ADQ0 I/O

Multiplexed Address/Data bus

- Inputs for addresses during read operation, which are for addressing BufferRAM & Register.

- Inputs data during program and commands for all operations, outputs data during memory array/

Data pins float to high-impedance when the chip is deselected or outputs are disabled.

INT / INT1 O

Interrupt

Notifies the Host when a command is completed. After power-up, it is at hi-z condition. Once IOBE is set to 1, it does not float

to hi-z condition even when CE is disabled or OE is disabled. Especially, only when reset(Cold, Warm, Hot, NAND Flash

Core) command in DDP are issued, it operates as open drain output with internal resistor (~50Kohm). The INT is the interrupt

for Single or DDP device. The INT1 is the interrupt for the first DDP device(KFN8GH6Q4M) in QDP(KFKAGH6Q4M)

INT2 O Interrupt

The INT2 is the interrupt for the second DDP device(KFN8GH6Q4M) in QDP(KFKAGH6Q4M)

RDY O Ready

Indicates data valid in synchronous read modes and is activated while CE is low

CLK I

Clock

CLK synchronizes the device to the system bus frequency in synchronous read mode.

The first rising edge of CLK in conjunction with AVD low latches address input.

WE IWrite Enable

WE controls writes to the bufferRAM and registers. Datas are latched on the WE pulse’s rising edge

AVD I

Address Valid Detect

Indicates valid address presence on address inputs. During asynchronous read operation, all addresses are valid while AVD

is low, and during synchronous read operation, all addresses are latched on CLK’s rising edge while AVD is held low for one

clock cycle.

> Low : for asynchronous mode, indicates valid address; for burst mode, causes starting address to be latched on rising edge

on CLK

> High : device ignores address inputs

RP I

Reset Pin

When low, RP resets internal operation of Flex-MuxOneNAND. RP status is do not care during power-up

and bootloading. When high, RP level must be equivalent to Vcc-IO / Vccq level.

CE / CE1 I

Chip Enable

CE-low activates internal control logic, and CE-high deselects the device, places it in standby state,

and places DQ in Hi-Z.

The CE input enables device for Single or DDP .

The CE1 input enables the first DDP device(KFN8GH6Q4M) in QDP(KFKAGH6Q4M)

CE2 IChip Enable

The CE2 input enables the second DDP device(KFN8GH6Q4M) in QDP(KFKAGH6Q4M)

OE IOutput Enable

OE-low enables the device’s output data buffers during a read cycle.

Power Supply

VCC-Core

/ Vcc

Power for Flex-MuxOneNAND Core

This is the power supply for Flex-MuxOneNAND Core.

VCC-IO

/ Vccq

Power for Flex-MuxOneNAND I/O

This is the power supply for Flex-MuxOneNAND I/O

Vcc-IO / Vccq is internally separated from Vcc-Core / Vcc.

VSS Ground for Flex-MuxOneNAND

etc.

DNU Do Not Use

Leave it disconnected. These pins are used for testing.

NC No Connection

Lead is not internally connected.

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