Samsung MUXONENAND A-DIE KFN4G16Q2A Bedienungsanleitung

MuxOneNAND2G(KFM2G16Q2A-DEBx)

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FLASH MEMORY

MuxOneNAND4G(KFN4G16Q2A-DEBx)

KFM2G16Q2A

KFN4G16Q2A

2Gb MuxOneNAND A-die

INFORMATION IN THIS DOCUMENT IS PROVIDED IN RELATION TO SAMSUNG PRODUCTS,

AND IS SUBJECT TO CHANGE WITHOUT NOTICE.

NOTHING IN THIS DOCUMENT SHALL BE CONSTRUED AS GRANTING ANY LICENSE,

EXPRESS OR IMPLIED, BY ESTOPPEL OR OTHERWISE,

TO ANY INTELLECTUAL PROPERTY RIGHTS IN SAMSUNG PRODUCTS OR TECHNOLOGY. ALL

INFORMATION IN THIS DOCUMENT IS PROVIDED

ON AS "AS IS" BASIS WITHOUT GUARANTEE OR WARRANTY OF ANY KIND.

1. For updates or additional information about Samsung products, contact your nearest Samsung office.

2. Samsung products are not intended for use in life support, critical care, medical, safety equipment, or similar

applications where Product failure could result in loss of life or personal or physical harm, or any military or

defense application, or any governmental procurement to which special terms or provisions may apply.

MuxOneNAND‚ is a trademark of Samsung Electronics Company, Ltd. Other names and brands may be

claimed as the property of their rightful owners.

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FLASH MEMORY

MuxOneNAND4G(KFN4G16Q2A-DEBx)

Revision History

Document Title

MuxOneNAND

Revision History

Revision No. History Draft Date Remark

0.0

0.1

0.2

1.0

1.1

1.11

1.2

1. Initial issue.

1. Corrected errata.

2. Chapter 3.3.1 Cold Reset Mode Operation revised.

3. Chapter 6.17 Cold Reset Timing revised.

4. Chapter 5.9 AC Characteristics for Load/Program/Erase Performance

revised.

1. Corrected errata.

2. Chapter 3.3 Reset Mode Operation revised.

3. Chapter 5.5 AC Characteristics for Asynchronous Read tOEH removed.

4. Chapter 5.9 AC Characteristics for Load/Program/Erase Performance

tINTW removed.

5. Chapter 6.5 Asynchronous Read (VA Transition Before AVD Low) tOEH

removed.

6. Chapter 6.6 Asynchronous Read (VA Transition After AVD Low) tOEH

removed.

7. Chapter 6.12 Program Operation Timing tINTW removed.

8. Chapter 6.16 Block Erase Operation Timing tINTW removed.

1. Corrected errata.

1. Chapter 1.4 Product Features revised.

2. Chapter 2.8.4 Version ID Register F002h revised.

3. Chapter 2.8.22 Interrupt Status Register F241h (R/W) revised.

4. Chapter 3.4.4 Data Protection Operation Flow Diagram revised.

5. Chapter 3.4.4 All Block Unlock Flow Diagram revised.

6. Chapter 5.8 AC Characteristics for Burst Write Operation revised.

1. Chapter 2.8.21 : Description of OTP Lock status and 1st block OTP Lock

status revised.

2. Chapter 3.6 Load Operation Flow Chart Diagram revised.

3. Chapter 3.8 Cache Read Flow Chart revised.

4. Chapter 3.9.5 Synchronous Burst Block Read Operation Flow Chart

revised.

5. Chapter 3.12 Copy-Back Program Operation Flow Chart revised.

6. Chapter 3.12.1 Copy-Back Program Operation with Random Data Input

Flow Chart revised.

7. Chapter 3.13.1 Block Erase Operation Flow Chart revised.

8. Chapter 3.13.3 Multi Block Erase/ Multi Block Erase Verify Read Flow

Chart revised.

9. Chapter 3.13.4 Erase Suspend and Erase Resume Operation Flow Chart

revised.

10. Chapter 3.14.1 OTP Block Read Operation Flow Chart revised.

11. Chapter 3.14.2 OTP Block Program Operation Flow Chart revised.

12. Chapter 3.14.3 OTP Block Lock Operation Flow Chart revised.

13. Chapter 3.14.4 1st Block OTP Lock Operation Flow Chart revised.

14. Chapter 3.14.5 OTP and 1st Block OTP Lock Operation Flow Chart

revised.

1. Chapter 2.4 Pin Description revised.

2. Chapter 3.4.3.1 Unlocked NAND Array Write Protection State revised.

3. Chapter 3.4.3.3 Locked-tight NAND Array Write Protection State revised.

4. Chapter 3.4.4 All Block Unlock Flow Diagram revised.

5. Chapter 7.1.3 Determining Rp Value revised.

Jul. 13, 2007

Sep. 06, 2007

Oct. 26, 2007

Dec. 13, 2007

Mar. 27, 2008

Apr. 07, 2008

Dec. 09, 2008

Advanced

Preliminary

Final

MuxOneNAND2G(KFM2G16Q2A-DEBx)

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FLASH MEMORY

MuxOneNAND4G(KFN4G16Q2A-DEBx)

Revision No. History Draft Date Remark

1.3 1. Corrected errata.

2. Chapter 2.8.18 Command Register F220h (R/W) revised.

3. Chapter 3.4.3 NAND Array Write Protection states revised.

4. Chapter 3.4.3.3 Locked-tight NAND Array Write Protection State revised.

Dec. 16, 2008 Final

MuxOneNAND2G(KFM2G16Q2A-DEBx)

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FLASH MEMORY

MuxOneNAND4G(KFN4G16Q2A-DEBx)

1.0 INTRODUCTION

This specification contains information about the Samsung Electronics Company MuxOneNAND‚ Flash memory product family. Section 1.0

includes a general overview, revision history, and product ordering information.

Section 2.0 describes the MuxOneNAND device. Section 3.0 provides information about device operation. Electrical specifications and tim-

ing waveforms are in Sections 4.0 through 6.0. Section 7.0 provides additional application and technical notes pertaining to use of the Mux-

OneNAND. Package dimensions are found in Section 8.0

1.1 Flash Product Type Selector

Samsung offers a variety of Flash solutions including NAND Flash, MuxOneNANDand NOR Flash. Samsung offers Flash products both

component and a variety of card formats including RS-MMC, MMC, CompactFlash, and SmartMedia.

To determine which Samsung Flash product solution is best for your application, refer the product selector chart.

Density Part No. VCC(core & IO) Temperature PKG

2Gb KFM2G16Q2A-DEBx 1.8V(1.7V~1.95V) Extended 63FBGA(LF)

4Gb KFN4G16Q2A-DEBx 1.8V(1.7V~1.95V) Extended 63FBGA(LF)

Application Requires

Samsung Flash Products

NAND MuxOneNANDNOR

Fast Random Read 

Fast Sequential Read 

Fast Write/Program 

Multi Block Erase (Max 64 Blocks) 

Erase Suspend/Resume 

Copyback (EDC) (ECC)

Lock/Unlock/Lock-Tight 

ECC External (Hardware/Software) Internal X

Scalability 

MuxOneNAND2G(KFM2G16Q2A-DEBx)

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FLASH MEMORY

MuxOneNAND4G(KFN4G16Q2A-DEBx)

1.2 Ordering Information

1.3 Architectural Benefits

MuxOneNAND is a highly integrated non-volatile memory solution based around a NAND Flash memory array.

The chip integrates system features including:

A BootRAM and bootloader

Two independent bi-directional 2KB DataRAM buffers

A High-Speed x16 Host Interface

On-chip Error Correction

On-chip NOR interface controller

This on-chip integration enables system designers to reduce external system logic and use high-density NAND Flash in applications that

would otherwise have to use more NOR components.

MuxOneNAND takes advantage of the higher performance NAND program time, low power, and high density and combines it with the syn-

chronous read performance of NOR. The NOR Flash host interface makes MuxOneNAND an ideal solution for applications like G3 Smart

Phones, Camera Phones, and mobile applications that have large, advanced multimedia applications and operating systems, but lack a

NAND controller.

When integrated into a Samsung Multi-Chip-Package with Samsung Mobile DDR SDRAM, designers can complete a high-performance,

small footprint solution.

KF X XX 16 Q 2 A - D E X X

Samsung

MuxOneNAND Memory

Device Type

M: Single Chip

N: Dual Chip

Density

2G : 2Gb

4G : 4Gb

Operating Temperature Range

E: Extended Temp. (-30 C to 85 C)

Page Architecture

2: 2KB Page

Version

A: 2nd Generation

Product Line designator

B : Include Bad Block

D: Daisy Sample

Operating Voltage Range

Q : 1.8V(1.7 V to 1.95V)

Package

D: FBGA(Lead Free)

Organization

16 : x16 Organization

Speed

6 : 66MHz

8: 83MHz

MuxOneNAND2G(KFM2G16Q2A-DEBx)

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FLASH MEMORY

MuxOneNAND4G(KFN4G16Q2A-DEBx)

1.4 Product Features

Device Architecture

Design Technology:

Supply Voltage:

Host Interface:

5KB Internal BufferRAM:

SLC NAND Array:

Device Performance

Host Interface Type:

Programmable Burst Read Latency:

Multiple Sector Read/Write:

Multiple Reset Modes:

Multi Block Erase:

Low Power Dissipation:

Reliability

System Hardware

Voltage detector generating internal reset signal from Vcc

Hardware reset input (RP)

Data Protection Modes

User-controlled One Time Programmable(OTP) area

Internal 2bit EDC / 1bit ECC

Internal Bootloader supports Booting Solution in system

Handshaking Feature

Detailed chip information

Packaging

2G products

4G DDP products

A die

1.8V (1.7V ~ 1.95V)

16 bit

1KB BootRAM, 4KB DataRAM

(2K+64)B Page Size, (128K+4K)B Block Size

Synchronous Burst Read

- Up to 83MHz clock frequency

- Linear Burst 4-, 8-, 16-, 32-words with wrap around

- Continuous 1K words Sequential Burst

Synchronous Burst Block Read

- Up to 83MHz clock frequency

- Linear Burst 4-, 8-, 16-, 32-, 1K-words with no-wrap

- Continuous (1K words) 64 Page Sequential Burst

Synchronous Write

- Up to 83MHz clock frequency

- Linear Burst 4-, 8-, 16-, 32-, 1K-words with wrap around

- Continuous 1K words Sequential Burst

Asynchronous Random Read

- 76ns access time

Asynchronous Random Write

Latency 3,4(Default),5,6 and 7.

1~40Mhz : Latency 3 available

1~66Mhz : Latency 4,5,6 and 7 available

Over 66Mhz : Latency 6,7 available.

Up to 4 sectors using Sector Count Register

Cold/Warm/Hot/NAND Flash Core Resets

up to 64 Blocks

Typical Power,

- Standby current : 10uA (Single)

- Synchronous Burst Read current(66MHz/83MHz, single) : 20/25mA

- Synchronous Burst Write current(66MHz/83MHz, single) : 20/25mA

- Load current : 30mA

- Program current : 25mA

- Erase current : 20mA

- Multi Block Erase current : 20mA

- Data retention 10year after 10K Program/Erase Cycles

- Data retention 1year after 100K Program/Erase Cycles

- Write Protection for BootRAM

- Write Protection for NAND Flash Array

- Write Protection during power-up

- Write Protection during power-down

- INT pin indicates Ready / Busy

- Polling the interrupt register status bit

- by ID register

63ball, 10mm x 13mm x max 1.0mmt , 0.8mm ball pitch FBGA

63ball, 10mm x 13mm x max 1.2mmt , 0.8mm ball pitch FBGA

MuxOneNAND2G(KFM2G16Q2A-DEBx)

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FLASH MEMORY

MuxOneNAND4G(KFN4G16Q2A-DEBx)

1.5 General Overview

MuxOneNAND‚ is a monolithic integrated circuit with a NAND Flash array using a NOR Flash interface. This device includes control logic, a

NAND Flash array, and 5KB of internal BufferRAM. The BufferRAM reserves 1KB for boot code buffering (BootRAM) and 4KB for data buffer-

ing (DataRAM), split between 2 independent buffers. It has a x16 Host Interface and a random access time speed of ~76ns.

The device operates up to a maximum host-driven clock frequency of 66MHz / 83MHz for synchronous reads at Vcc(or Vccq. Refer to chapter

4.2) with minimum 4-clock (66MHz) / 6-clock (83MHz) latency. Below 40MHz it is accessible with minimum 3-clock latency. Appropriate wait

cycles are determined by programmable read latency.

MuxOneNAND provides for multiple sector read operations by assigning the number of sectors to be read in the sector counter

register. The device includes one block-sized OTP (One Time Programmable) area and user-controlled 1st block OTP(Block 0) that can be

used to increase system security or to provide identification capabilities.

The attached datasheets are prepared and approved by SAMSUNG Electronics. SAMSUNG Electronics CO., LTD. reserve the right to

change the specifications. SAMSUNG Electronics will evaluate and reply to your requests and questions about device. If you have any ques-

tions, please contact the SAMSUNG branch office near you.

MuxOneNAND2G(KFM2G16Q2A-DEBx)

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FLASH MEMORY

MuxOneNAND4G(KFN4G16Q2A-DEBx)

2.0 DEVICE DESCRIPTION

2.1 Detailed Product Description

The MuxOneNAND is an advanced generation, high-performance NAND-based Flash memory.

It integrates on-chip a single-level-cell (SLC) NAND Flash Array memory with two independent data buffers, boot RAM buffer, a page buffer for

the Flash array, and a one-time-programmable block.

The combination of these memory areas enable high-speed pipelining of reads from hostBufferRAMPage Bufferand NAND Flash Array.

Clock speeds up to 66MHz / 83MHz with a x16 wide I/O yields a 108MByte/second bandwidth.

The MuxOneNAND also includes a Boot RAM and boot loader. This enables the device to efficiently load boot code at device startup from the

NAND Array without the need for off-chip boot device.

One block of the NAND Array is set aside as an OTP memory area, and 1st Block (Block 0) can be used as OTP area. This area, available to

the user, can be configured and locked with secured user information.

On-chip controller interfaces enable the device to operate in systems without NAND Host controllers.

2.2 Definitions

B (capital letter) Byte, 8bits

W (capital letter) Word, 16bits

b (lower-case letter) Bit

ECC Error Correction Code

Calculated ECC ECC that has been calculated during a load or program access

Written ECC ECC that has been stored as data in the NAND Flash array or in the BufferRAM

BufferRAM On-chip internal buffer consisting of BootRAM and DataRAM

BootRAM A 1KB portion of the BufferRAM reserved for Boot Code buffering

DataRAM A 4KB portion of the BufferRAM reserved for Data buffering

Sector

Part of a Page of which 512B is the main data area and 16B is the spare data area.

It is also the minimum Load/Program/Copy-Back Program unit

during a 1~4 sector operation is available.

Data unit

Possible data unit to be read from memory to BufferRAM or to be programmed to memory.

- 528B of which 512B is in main area and 16B in spare area

- 1056B of which 1024B is in main area and 32B in spare area

- 1584B of which 1536B is in main area and 48B in spare area

- 2112B of which 2048B is in main area and 64B in spare area

MuxOneNAND2G(KFM2G16Q2A-DEBx)

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FLASH MEMORY

MuxOneNAND4G(KFN4G16Q2A-DEBx)

2.3 Pin Configuration

2.3.1 2Gb Product (KFM2G16Q2A)

(TOP VIEW, Balls Facing Down)

63ball FBGA MuxOneNAND Chip

63ball, 10mm x 13mm x max 1.0mmt , 0.8mm ball pitch FBGA

NC NC NC NC

INT NC NC NC NC NC

NC NC NC

WE RP ADQ1 VSS VSS ADQ2

ADQ3 ADQ7 ADQ14 OE ADQ6 VCC

ADQ8 ADQ11 ADQ4 ADQ5 ADQ12 VCC

ADQ0 NC ADQ15 ADQ10 ADQ9

CE ADQ13 NC NC NC

AVD NC NC NC

NC NC NC NC NC

NC NC NC NC

Core

CLK

RDY

MuxOneNAND2G(KFM2G16Q2A-DEBx)

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FLASH MEMORY

MuxOneNAND4G(KFN4G16Q2A-DEBx)

2.3.2 4Gb Product (KFN4G16Q2A)

(TOP VIEW, Balls Facing Down)

63ball FBGA MuxOneNAND Chip

63ball, 10mm x 13mm x max 1.2mmt , 0.8mm ball pitch FBGA

NC NC NC NC

INT NC NC NC NC NC

NC NC NC

WE RP ADQ1 VSS VSS ADQ2

ADQ3 ADQ7 ADQ14 OE ADQ6 VCC

ADQ8 ADQ11 ADQ4 ADQ5 ADQ12 VCC

ADQ0 NC ADQ15 ADQ10 ADQ9

CE ADQ13 NC NC NC

AVD NC NC NC

NC NC NC NC NC

NC NC NC NC

Core

CLK

RDY

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