Sharp ER-1910 Bedienungsanleitung

fevmeriieereesnn

ER-

2395

SHARP

SERVICE

MANUAL

The

photo

shows

Model

ER-1920.

CODE

:

00ZER23895SMHE

ELECTRONIC

CASH

REGISTER

SECTION

2

HARDWARE

ER-1910/1920

MODEL

ER-2385/2395

ER-1910/1920

(Europe

Version)

ER-2385/2395

(U.S.A.,

Canada,

South

Africa

Version)

The

photo

shows

Model

ER-2395.

CONTENTS

1.

REFERENCE

DOCUMENTS.

.......ccsccccsssessesscessecsessesessesecstsesatecasavsesesanseeeeees

a

2.

BLOCK

DIAGRAM

.........eeeeeeeeee.

Eo

hae

esse

eee

cee

2

3.

CPU

AND

KDC

DESCRIPTIONS

ou..cccccccssescssesesssssessssesstssstssststsaseescarevseseeees

2

4.

CIRCUIT

DESCRIPTIONS.

........c.ccccssscsssssssecsscecsessecsecesocerssesesecsesesesseaesesesseeeenare

3

5.

FUNCTIONS

FOR

POWER

FAILURE

AND

MOTOR

LOCK

........cecsecseeeseeeeeee

7

6.

ADJUSTMENTS.

......cccccccecescesesesessesessseseeseatstsesatsrsecstavenes

eeeennute

tacseeieuats

8

7.

TEST

FUNCTIONS.

.....ccccccccesseseseseesecesseseeeeeees

ee

ate

ees

8

8.

SERVICE

PRECAUTION

ON

THE

CPU

AND

OUTER

ROM

REPLACEMENT

.........cscsssssssessssssssecssessecssecssesssessesseesessseseeseeaes

12

Note:

The

service

manual

of

the

above

models

is

consisted

of

four

major

manuals

as

follows.

Therefore,

please

refer

to

other

manuals

together

with

this

service

manuals

in

your

service.

1-1.

Section

1

programming

manuals

for

U.S.A.,

Canada,

South

Africa,

@te.

.......

ee

ceeeeeeeereeens

00ZER2395SMBE

1-2.

Section

1

Basic

manuals

for

Europe,

@tC.

.............

cee

ceeecsccccecsessssesseseeseeeeeseeseeesessetsaaenseaseeseeseeens

00ZER1920SMBE

2.

Section

2

Hardware

description

for

all

countries

(except

JAPAN)

............

cc

eessttecessetseeestteneeeees

O0OZER2395SMHE

3.

Circuit

diagram

and

PWB

layout

for

all

COUNTIES.

2.0.0.0...

cc

ceeetetesseeeneneeteeeeteeeenneesanerteseeeens

0OZER2395CD1M

4.

“Printer

mantial

{or

all

COUNIMIOCS

.

ccc.

cetsaasceeebeds

iinciieceiceceeuds

ee

eebnin

cd

naa

Sedeeaeeennied

one

eedeeanee

00OZCR802ASM/M

Note:

Europe

Version

=

U.K.,

W.

Germany,

Australia

and

others.

A

SHARP

CORPORATION

ER-

2395

1.

Reference

Documents

—s_—>

Applicable

areaandmodels

U.K.,

Germany,

U.S.A.,

Canada,

South

Australia

and

others

.

Africa

and

others

ER-1910

ER-1920

ER-2385

~~

ER-2395

Manual

code

Section

1

Basic

manual

..|

Specification,

SRV

00ZER1920SMBE

Section

1

Prog.

manual

Programming,

option

etc.

O0ZER2395SMBE

‘.

;

Circuit

description.

2)

Section

2

Hardware

Dig.,

Service

option

etc.

00ZER2395SMHE

3)

Circuit

diagram

Main

board,

key

.

~

CR-802,

812,911A

00ZCR802SM//E

-CR-802A,

812A

00ZCR802ASM/M

~CR-911D

~

00ZCR911DSM/M

Manual

name

Contents

—

Ss

—

4)

Printer

manual

Onan

|

eesiccrtaesrinton

|

;

SUSA)

©

(Except

U.S.A.)

2.

Block

Diagram

|

ER-1920,

ER-2395

\|

Drawer

B,

D,

E

only

,

J|

(Option)

|

-

Lf

pier

Tien

eis

eoriae

ss

Operator

side

Customer

side

4

Buzzer

|

..:

Idisp.

(9

digit)

disp.

(9

digit)

ay

dh

a:

|

;

..

Driver

.

SC

1033C

a

|

CR-812A

or

|

;

[

CR-911D

|

:

|

L

VDD

|

ee

|

SOS

ROM

VDD

|

a

(27128

or

27256)

|

_

VPO

|

Paid

ae

|

Main

P.W.B.

|

anne

Regulator

;

|_|

Rectifier

ae

ee

|

y.

ee

circuit

DC—DC

VDISP

|

VCC

|

Converter

VDD

|

VB

;

fats

ash

el

nee

ee

Ak ee

ae

peth

ea

taeeccttaes

sey

ta

dak,

ai,

Gentil

Keyboard

AC

Fig.

2-1

ER-

2395

3.

CPU

description

3-1.

CPU

(SC1033C)

The

SC1033C

is

a

single

chip

microprocessor

which

has

an

internal

ROM,

RAM,

and

serial

I/O.

configuration

DBO|

2|

|

63]

AZ

DB1|

3]

62]

A12

DB2

A8

DB8

|

60]

AQ

DB4|

6|

159]

All

DB5|

7

A10

DB6]

8|

Al4

DB7[

9]

56]

A13

CS1

55]

A6

SHEN[11|

54]

A5

POFF

|

12

/58]A4

WR

|

13

|

|52)A8

RD}

14|

A2

DRS

Al

1

DF

|

16]

A0

SCK

MG

8

BZ

MG7

LDRQ|

19]

|

46|

MG

6

PC1

|

20|

MG5

STH{21]

|

MG4

HTS

[22]

43]

MG8

RES

(23|

MG2

x2

[ea].

MG1

X1

|

40]

RCOM

Al5

|

26|

[39]

JCOM

PEOUT

|

27

|

38|

RF

PEIN

|

28]

JF

A15

[29

|

36]

STMP

CS2

[30

[35]

DR

a|

31

MG

10

GND

|

82|

MGQ..

Fig.

3-1.

3-2.

Signal

description

—

[PinNo.

[Signainame|

VO

[

_Deseripfon

——SC*d

ce

CC

TT

2

I/O

ete

10

|

68

[IN

|

chipsets

eonects

wah

AB)

Shift

enable

es,

Data bus

line

|

ia

[WA

[OUT

|

Wit

signal

romalynatused)

[a4

[AD

[OUT

[Readsinal

Se

pees

|

aoe

onan

colina

pee

[18

[az

[OUT

|

Buzzersignl

SSS

|

20

[por

[In|

Neuse

ion,

array

somanTo

GND)

[21

[StH

[IN

ebitserialinput(KOG)

22

|

Hs

[our

|

stseratoupu

oo)

(3a

[

REST_|_

IN

_|

Reset

input

‘as

eS

enem

|

a

|

28_|

Xt

_|

—_|

SMH

oscil

Ai5

Address

bus,

A15:

|

28

|

PEIN,

|

IN

|PEsignalinput

30

[85

[

OUT

|

Chip

select?

(normaliynot

used)

SOSROM

Pc Ge

CT

NE

2

GIN

Se

OND

a

es

ee

38

[wee

|

OUT

|

Printer

magnets

|

34

|

MGi0

|

OUT

|

PrintermagnettO

|

35

|

DR

|

OUT

|

Draweropensignal

|

36

|

STMP

|

OUT

|

Stampsional

|

387

|

QUT

|

Journalfeedsignal

|

|e

or

Rested

-

39}.

COM

|

OUT

|

Journal

common

signal.

-

at

wet

our

|

Pitermagnett

[aa

[

waa

|

OUT

|

Printermegnet2

[43

|

wigs

[OUT

|

Printer

magnet’

|

Printer

magnet

4

|

MG5—_|

OUT

|

Printer

magnet

5

=

Printer

magnet

|

“MG7__|

OUT

Printer

magnet

8

_

|

_OUT

|

Address

bus,

AO

|

7

Address

bus,

At

:

OUT

|

Address

bus,

A2

Address

bus,

A3

-

OUT

|

Address

bus,

A4

,

|

84

|

AS

|

OUT

|

Address

bus,

AS

OUT

|

Address

bus,

A6

:

Address

bus,

A13

OUT

|

Address

bus,

A14

Address

bus,

A10

OUT

|

Address

bus,

A11

|

Address

bus,

AQ

mot

OUT

Address

bus,

A8

Address

bus,

A12

OUT

|

Address

bus,

A7

ae

VOD

(rechargeable

battery

voltage

during

power

down)

3-3.

KDC

(4PD7507-036)

The

»PD7507-036

is

called

KDC

(Key

Display

Controller)

which

is

used

to

control

the

keyboard,

display,

and

clock.

Communication

is

performed

with

the

SC1033C

CPU

via

the

8-bit

serial

interface.

Xi

—

p20

a

P2i[

3

SHEN

[_4]

a

RES1

a

36]

P41

Pees

P

40

Pil

aa]

P53

Pi2[

8|

P52

Pis[

9

P51

he

P50

Ee

30

|

P63

oa

P62

P33

i

ts

P60

P71

De

P72

STH

P78

=

RESET[

18|

.

est

LDRQ

yep

[20

121

|CL2

Fig.

3-2

3-4.

Signal

description

(0

a

Shift

enable

OUT

|

Reset

signal

Key

return

signal

10

|

oS

a

eo

vispay

drive

signal

hay

&

scan

signal

eS

eee

ee

te

|

Fr

[OUT

|

Disa

crve

signal

hey

scan

signal

OUT

,

Display

drive

V

Display

drive

g-

Display

drive

f

Display

drive

e

Display

drive

d

Display

drive

c

-

Display

drive

b.

—

Display

drivea

Display

drive

DP

hm

ER=2395

4.

Circuit

description

4-1.

Oscillation

circuit

(1)

CPU

clock

|

«

aaeia

ete:

~-S$C1088C

Crystal

|

Fig.

4-1

The

basic

clock

is

created

in

the

3MHz

crystal

oscillator

and

connected

directly

with

the

CPU.

The

following

SHOWS

the

waveforms

of

signals,

X1

and

X2.

(

3MHz

)

GND

—_——

dU

HEV

«

-

+3V

1

NAAALNEV

NA

so

+1V

0.33

BS

(2)

KDC

(Key

Display

Controller)

clock

32.768KH

z

®

Clock

for

timer/calender

—

C6

83PF

X2

X1

KDC

“PD

7507C

CL1

—086

ex

Basic

clock

to

UPD7507C

~

Fig.

4-3

©

From

this

circuit

is

delivered

the

timer,

calendar,

and

«PD7505C

basic

clock.

1)

Timer

and

calendar

clock

Clock

frequency

generated

across

X1

and

X2

is

adjusted

by

the

trimmer

capacitor

(C5)

and

supplied

to

the

KDC.

The

trimmer

capacitor

has

been

factory

adjusted

using

the

error

meter,

it

should

never

be

readjusted.

2)

»PD7507C

basic

clock

Clock

frequency

coming

across

CL1

and

CL2

is

adjusted

by

the

©

potentiometer

(VR1)

and

supplied

to

the

KDC.

|

Even.

if

this.

frequency.

is

observed

on

the

oscilloscope,

it.

would

not

be

possible

to

see

an

exact

waveform

because

of

a

_capacitance.

in.

the

probe.

_

..

sega»

_

So,

one

of

the

following

two

methods

may

‘be

used.

[Adjustment-1]

|

| |

OE

cates

Observe

on

the

oscilloscope

the

waveform

on

the

test

1

(pin

3)

of

the

«PD7505C

and

adjust

it.

using.

VR

so

that

the

following

waveform

can

be

seen.

reer

5V

TP

1

|

GND

+-———

8.8

~

9.0ms

——+

Fig.

4-4

ER-~2395

[Adjustment-2]

Execute

Job

#15

in

the

SRV

ode!

‘and

adjust

VR

‘so

thal

the

waveform

on

TP1

should

be

as

shown

below...

TP1

_

890

10pse

ee

Fig.

4-5

4-2.

Reset

circuit.

—

RES

1

MPD

7507C

[RID

22KQ

SC

1088.C

Fig.4-6

|

Timings

Power

on

Power

off

+5V

QV

BY

ov

+5V

OV

+5V

0V

+5V

4-3.

PE

circuit.

_

Mode

switch

«—-—-—-—

—--}-

©

ane

oe

When

the

mode

switch

is

set

to

any

‘position

other

than

OFF,

the

switch

shown

in

the

figure

above

turns

on.

(VO

connected:

with

P-ON.)

@

becomes

about

18V

via

ZD3.

‘As

the

power

is

turned

on,

VCC

generated

in

the

DC-DC

converter

turns

to

5V.

Voltage

at

point

(©)

of

C16

gradually

increases

by

VCC.

When

VO

disengages

from

P-ON

inside

the

(PE)

mode

switch,

the

charge

in'C16

is

discharged

to

the

direction

shown

with

©

because

the

voltage

at

point

@

“Becomes

null.

So,

the

voltagé

at

point

©)

drops

down

to

GND

level.

<——

Power

on

=

Printer

in

action

PE,

OY

tt—Ctst—<Cs~ststsSSC

Fig.

4-9

The

PE

signal

is

waveform

shaved

within

the

SC1033C

through

the

NOT

gate

and

supplied

to

the

CPU

and

KDC

(y%PD7507).

4-4.

Battery

circuit

Vcc

(5.0V

)

Vop

(

5.0V

)

SC

.1083C

Se

ee

transformer

(4-pin)

KDC

(

#PD

7507)

Fig.

4-10

———>

:

Battery

recharge

current

Henan

=»

:

Battery

discharge

current

Voltage

at

each

point

is

as

follows:

AC

supply

Point

@:

-.

tess

a

ee

Pa

ee

4-5.

Communication

between

the

CPU

and

the

KDC

(uPD7507C)

|

SC1033C

side

;

I

+5V

=p

VRAM

8—Bit

|

8—Bit

Serial

Port,

Port

F--

|

8-Bit

Serial

Port

|

Bit

Serial

|

8-Bit

Serial

Port

|

er

ee

|

wi

we

wmad

-

LDRQ

—+

INTO

=

yPD7507C

SHEN

=

P22

-—086

(HOST)

“i

:

ae

(SLAVE)

-

GND

P00

RESET

GND

Fig.

4-11

STH

—

:

Serial

input

HTS

_

:

Serial

output

SCK

—

:

Shift

clock

-

-LDRQ.

-:-Load-request

SHEN

_:

Shift

enable

RES1

:

System

reset

coe

PE

:

Power

down

eelecion

:

evanee

:

ROCs

reset.

ae

(1)

During

power

off

Be

Power

is

supplied

to

the

KDC

«

even

if

the

power

is

off.

During

this

period,

the

KDC

performs

the

following

operations.

(KDC

operating

voltage

is

+3V

to

+7V)

1)

Keeping

time

for

the

timer

and

calendar.

2)

Detection

of

the

PE

signal

level...

The

KDC

checks

the

POF

ea

at

500msec.*

-

LOW

CLI/CL2

ba

500mS

RIA,

MMM

=

===

pan

ayes

ge

ae

=

ie

Fig.

4-12

“Power

c

on.

|

Vcc

\

|

PEIN

RES

I

SHEN

~

LDRQ.

|

ok

:

t

|

“|

|

i

|

SCK

8

clocks

©

Data

process

by

CPU

ER=2395

The

CPU

(SC1033C)

is

not

operating

as’+5V

is

notin

supply

during

power

off.

(2)

When

power

is

turned

on.

When

the

power

is

turned

on,

PE

is

foised

high

and

sent

to

the

KDC.

The

KDC

having

received

a

ee

State

of

PE,

the

KDC

|

issues

RES1.

to

reset

the

CPU.

|

(3)

When

power

is

turned

off

x

2

ee

co

When

the

power

is

turned

off,

PE

is

forced

low

and’

directly

sent

to

the

CPU.

After

the.

CPU.

finishes

executing.the

required

processing,

it

sends

LDRQ

and

SCK

to

the

KDC.

leat

-

send

R

AEST

cue

CPU

thus

received

RES1

is.

then:

reset.

a

Power

off

i

(¢——

%§

RES1

generating

condition:

SCK

=

low

at

a

low

to

_

high

transition

of

LDRQ.

—|

@

.

Reset

is

released

from

the

CPU

upon

detecting

the

mode

and

key

input.

Fig.

4-13

(4)

KDC

reset

When

the

mode

switch

is

turned

on

in

the

SRV2

mode,

RESET

is

forced

high (5V)

and

the

KDC

is

reset.

RES1

is

pulled

down

with

a

12KQ,

resistor,

the

CPU

is

reset

by

the

RES1.

When

it

is

changed

from

the

SRV2

to

SRV1

mode,

RESET

is

forced

low

and

the

KDC

is

released

from

the

reset.

Then,

the

KDC

turns

RES1

‘high

to

release

the

CPU

from

the

reset.

SRV

2

SRV2--SRV1

'

:

RESET

a

KDC

starts

SCK

Fig.

4-14

~The

CPU

initializes

every

ey

and

reads

ine

‘start

condition.

REST

“2

QV

others

are

high

impedance

P21,

380~388,

70~78

(5)

Data

transfer

between

the

CPU

and

the

KDC

~~

Data

is

transferred

through

the

CPU

and

KDC

8-bit

serial

port

in

synchronization.

with

SCK

received

from

the

CPU...

To

transfer

data

from

the

CPU

to

the

KDC,

the

STH

line

is

used.

To

transfer

data

from

the

KDC

to

the

CPU,

the

HTS

line

is

used.

Data

transfer

can

take

place

with

a

SHEN

which

is

an

output

from

the

KDC.

When

the

CPU

senses

a

high

state

of

SHEN,

it

responds

with

SCK

to

carry

out

data

transfer.

When

data

transfer

has

been

completed,

the

CPU

sends

a.LDRQ

to

the

KDC

to

inform

that

the

CPU

has

finished

meen:

and

sending.

|

ER-2395

_

4-6.

Key

and

switch

read.

P20-P21,

P30-P38.

KDC

#MPD7507C

O86

YP

Key

sye.-Matrix.

Receipt.

1

;

on/OFF

SW

|

.P10-P13

P60—P62

_

47KOX7

Fig.

4-15

Signal

description

P20,

P21,

P30~P33,

P70~P73:

Key.

anid

Switch

scan

signal

P10~P13;

P60~P62:

Key

and’

switch

returns

signal

RESET:

KDC

reset

signal

P20,

P21,

P30~P33,

P70~P73

are

not

only

used

for

the

key

and

switch

scan

signals,

but

also

used

for

display

digits,

except

for

P20.

P20,

P21,

P30~P33,

P70~P73

are

issued

from

the

KDC

at

all

times,

‘and,

at

the

same

time,

and

the

KDC

checks

a

high

state

of

P10~P13,

P60~P62

tos

see

if.which

key

or.switch

is.at

ON...

|

Iscan

cycle=10.Ims

P30

Pll

v

rc

on

a)

P

62

key

-

Fig.

A-

16

Fig.4-16

shows

that

the

[RA]

key

is

being

depressed:

for

Pit

is

at

a

high

level

in

the

time

of

P33.

When

the

KDC

recognizes

the

key

depressed,

data

is

sent

on

the

STH

line

in

response

to

the

request

from

the

CPU.

4-7.

Display

control

.

as

|

DRIVER

CPU

KDC

SC

1038C

ae

Tet

d

Pies

Fig.

es

Te

Signal

description

*1:

P20,

P30~P33,

P70~P73(1G~9G):

Display

digit

signal

:

*2:

P43~P40,

P53~P50,

P63(a~g,

WV,

DP):

Display

segment

signal

P43

(DP):

Decimal

point

1°

§$C1083C

-

VPO

The

display

data

is

sent

from

the

CPU

to

the

KDC

with

the

HTS

signal

and

displayed

via

the

display

tube

driver..Once

the

KDC

received

the

display

data

from

the

CPU,

the

display

i

is

controlled

by

the

KDC

until

a

is

received.

|

Display

tube

driver

|

Since

a

fluorescent

tube

is

used

for

the

display,

the’

‘digplay

digit

and

segment

signals

are

operated

by

about

+34V.

The

LB1292

is

used

to

convert

the

signal

from

the

TTL

level

to

the

+34V

level.

an

i

P

ey)

GND

+

34-V

:

+5V-

High

|

High

:

+34V

it

a

Np

Low

:

GND

LB1292:

Driverx6

circuits

For

more

details

of

the

aiiae

tube,

refer

to

Cash

Register

Basic

..Manual,

Chapter.

9-3.

.

sie

4-8.

Printer

control

-

LB1234&

4

MG

1—MG10

Printer

CR802A,

CR812A

or

CR911D

Signal

name

RM1~RM10

_

:

Receipt

magnet

select

signal

JMi~JM10

:

Recording

magnet

select

signal

JF-JF_

:

Journal

feed

signal

RF-RF

:

Receipt

feed

signal

STMP-STAMP_:

Stamp

signal

a

:

Printer

interface

signal

IDF

:

Motor

drive

signal

JCOM

:

Journal

common

signal

RCOM

:

Receipt

common

signal

_

.

For

detail

of

printer,

refer

to

CR802A, CR812A,

CR911D,

CR-802,

CR-812,

and

CR-911A

Printer

Manual.

Motor

drive

circuit

eee

nee

ee

eee

ee

eee

ete

me

cme

TON

25B926

Q5

Printer

motor

Fig.4-20

_

With

a

high

state

of

IDF,

the

base

voltage

of

Q7

starts

to

decrease

via

1C4

and

Q7

goes

active

which

causes

ION

to

flow

through

the

-

motor

to

run

it.

‘When

IDF

goes

low,

Q7

comes

inactive

and

-

turns

on.

With

this,

igs

is

$

applied,

to

a

the

motor

quickly.

.

4-9.

Drawer

control

[Without

option

drawer]

VPO

2SD1509

|

R4

SC

10838

C

Drawer

open

sensor

Fig.

4-21

The

DR

signal

output

from

the

35

of

the

SC1033

drives

Q2

to

apply

current

to

the

drawer

magnet.

D1

is

used

to

prevent

a

counter-electromotive

force.

[With

délion

drawers]

7

Option

drawer

B,D,E

yO

0

Drawer

A

—o

,

Drawer

“7

open

—3

sensor

:

A

Fig.

405°

VPO{2}-—

In

case

an

optional

drawer

is

in

use,

drawers

are

driven

by

the

DR

signal

issued

from

the

35

of

the

SC1033C

and

MG1

through

MG4.

A

spark

killer

diode

is

contained

in

the

M54532P.

4-10.

Power

supply

circuit

VH1,

VH2

VDISP

VCC

VDD

GND

SOHOS

Converter

Joyeinbe

i

“‘BASLFT

NI-CD

Fig.

4-23

~

VPO

:

Drawer

+17.

6V~—19.

ov

VP

:

Printer

+18V

—

:

VH1,

VH2

:

Display

heater

+3.5V

(rms)

-VDISP>:

Display

tube

plate

and

grid

+34V

(+28.8V~+37.4V)

VCC

:

Circuit

drive

+5V

(+4.5V~+5.5V)

VB

:

Power

off

time

CPU

&

KDC

drive

+3.6V,

min.

VDD

-

Power

supply

to

CPU

and

KDC

+5V

(+4,5V~+5.5V)

C20

i

~

ggy—_|-

—_~Svre

t

C18

:

|

_§

Drawer

OV

a

ee

|

6)

As

Q10

turns

off,

VPO

then

starts

to

drop.

-

ER=2395

VPO

circuit:

VPO

Q10

2SD1191

TH

PO

vO

0

>

Mode

switch]

p11

C17].

vo

D10

si

C14:|C18.

1)

The

base

voltage

is

not

applied

to

Q10

when

VO

is

not

shorted

with

P-ON

within

the

mode

switch

(power.

of

Q10

is

atthe

OFF

state.

2)

When

VO

is

shorted

with

P-

ON,

base

voltage

is

;

added

to

Qto

so

that

it

goes

active.

_

3)

With

an

active

state

of

Q10,

the

voltage

VPO

starts

to

rise.

4)

When

the

voltage

at

point

@

@)

‘reaches:

TOV"

via

‘R27,

(202

then

comes

active.

5)

If

the

base

voltage

is

added

to

ag

in

this

moment

on

and

Q10.turns

off.

fee

;

98

i

is

turned

7)

As

VPO

starts

dropping,

it

also

causes

i

pase

>

voltage

to

decrease

and

Q9

turns

off,

finally...

si!

Hoary

8)

Q10

starts

to

rise.

again

and

VPO.

paging:

to

rise.

:

9)

.VPO

is

controlled

stable

by

repeating

the-above

eos,

ay

thru

18).

5.

Power

failure/motor

lock

mechanical

.

action

and

measures

|

5-1.

Action

at

power

failure

(power

off)

When

the

power

is

turned

off

in

a

middle

of

printing

operation

due

to

a

power

failure,

the

CPU

executes

the

power

failure

process.

(1)

When

a

power

failure

is

encountered

during

printing

operation,

power

failure

marks

(.....)

are

printed

on

a

upon

the

recovery

of

power,

and

the

printout

lost

at

the

time

of

power

failure

is

correctly

produced

on

a

:

(2)

If

power

failure

was

met

other

than

during

printing

operation,

the

operation

resumes

in

succession

to

the

operation

suspended

at

the

time

of

power-failure,

when

the

|

power

supply

is

recovered.

15-02-87

Printout

before

power

failure

—

Power

failure

marks

14999.

99

ee

Printout

of

the

data

immediately

_

before

the

power

failure.

1

@Q

*999.99TR

144)

000-0020

ER-2395

5-2.

Action

at

the

time

of

a

printer

motor

lock-up

When

the

motor

stops

rotating

due

to

a

paper

misfeed,

etc.,

the

power

supplied

to

the

motor

is

suspended

to

prevent

the

motor

coil

from

burning

out.

An

intermittent

peeping

will

occur

at

one

Secone

intervals.

;

Reset

method

©

a.

Turn

power

off.

ce

5

b.

Remove

the

cause

ae

motor

locked.

-

:

c.

Turn

poweron.

.

d.

Push

the

[7]

(receipt

feed)

key

and

i]

iguana

feed)

key

to

check

if

the

cause

has

been

removed.

e.

Push

the

[CL]

key.

6.

Adjustments

6-1.

Clock

adjustmentit

—

VR1

(100K),

TP1<—>GND

|

seek

to

pearagrapn:

4:

1.

6-2.

Error

adjlistnent

Trimmer

capacitor

C5,

TP1<—>GND.

'

Since

it

has

been

factory

adjusted,

no

adjustment

should

be

made.

6-3.

Printer

speed.

eee

|

VR2

(6.8KQ),

T

Race

2aNG:

|

‘VR2

adjustment

|

me

The

Q9

base

voltage

can

be

e

changed

using

VR2

to

aus

painter

cree.

|

=.

1)

Apply

the

aie

probes:

across

GND.

ape

the

test

TP2.

2)

Do

master

reset

and

feed

journal

paper

continuously.

3)

Observe

the

waveform

on

the

oscilloscope

and

adjust

it

as

shown

below.

rege

Paap

fe

koa:

tates

>|

T=370ms~384ms

7.

Test

fuinetlons

_(ER-

-1910/1

920/2385/2395)

-

7-1.

Prerequisite

This

test

function

operates

when

the

test

program

stored

in

the

SC1003C

CPU

internal

ROM.

The

following

are

required

in

order

to

execute

the

function.

a.

The

power

supply

to

the

logic

circuit

must

be

normal.

b.

Both

the

CPU

input

pins

and

CPU

internal

logic

circuits

are

functioning

normally

and

that

the

entire

KDC

(~PD7507),

and

its

“address

and

data

buses

are

operating

normally.

7-2.

Start

.of

test

function

3

The

following

key

operation

is

required

in

the

SRV1

mode

to

start

the

test.

XXxXX

3[TLor

Test

command

Master

reset

is

required

when

the

sete

is

to

be

started

for

the

first

time.

7-3.

List

of

test

commands

Test

No.

|

command

es

a

Clerk/Mode

switch

test

.

a

XXXxx02

Keyboardtest

Se

are

}

Test

description

Display

and

buzzertest

-

~

Receipt

ON/OFF

switch

test

Drawer

open

test

(The

code

6

to

8

are

for

optional

drawers)

5,6,7,8

oe

Continious

print

tes

eee

area

mons

14

|

Key

positon

sodetest

bo

ae

System

clock

test

Counter

clock

test

Sequential

test

-

1

Sequential

test

—

2

(drawer

al

sensor

disregarded)

ae

[eee

XXXX22

“4

Note:

*1

XXXX:

ER-1910—>

548

ER-1920->

916°

-

ER-2385->

815

ER-2395—

>

1062

Sum

check

data

for

standard

key

layout

Test

message

is

printed

on

both

the

receipt

and

journal.

The

contents

of

the

totalizer

and

the

preset

values

are

not

erased

by

the

test.

Clerk

switch

test

is

applicable

only

for

the

ER-

1920,

2395.

Ignore

the

test

for

the

ER-1910,

2385.

NOTE-1:

NOTE-2:

NOTE-3:

7-4.

Test

description.

|

Dy

Test

No.1:

Clerk

and

mode

switch

test

@

Key

operation

Push

the

clerk

switch—clerk

switch

E.

ak

:

Then,

push

the

clerk

and

mode

switches

in

the

following

¢

order.

Clerk

and

mode

switch

operation|

Display

_

Clerk

SW.

A

7

Clerk

Sw.

B

Clerk

SW.

D

|

Clerk

SW.

E

Mode

SW

PGM

or

VOID

|

_

With

clerk

switch:

|

model

only.

If

not,

skip

this

part.

a)

cl>

orOFF

OPX/Z

or

TIME

REG

X1

ZI

his

~

I3

OW

—

I

-

()

Description

©

As

the

clerk

and

mode

switch

position

number

is

displayed,

check

the

number.

|

@B)

Termination

.

The

mode

can

be

terminated

when

the

mode

switch

is

turned

to

the

SRV1

side

from

other

position.

Termination

print

at

error

Termination

print

at

normal

end

OY.

NOTE:Though

the

cisgiay

i

may

sway

y

ring

this

t

test,

it

i

is

not

a

Ratner:

2)

Test

No.2:

Keyboard

G@)

Key

operation

02

+[T]o

:

x

“KM

x*K

,

xX

a

Sum

check

data

Test

command

(1)

Enter

the

test

command

in

succession

to

the

sum

check

data

of

the

model.

ER-1910—

548

ER-1920—>

916

Mu

=a

fy

Mono51

a

foe

Li

rig

t

i

ER-2385->

815

it

_

ER-2395

—

1062

or

[CAAT

|

or

*(See

Note

“Sum

check

data”)

(2)

Next,

push

every

key

on

the

keyboard

except

for

the

receipt

_,

and

journal.

keys.

|

When

the

[TL]

or

[CA/AT]

key

is

depressed,

the

termination

~

printout

is

immediately

produced

assuming

that

all

keys

have

been

depressed.

There

is

no

order

in

which

the

keys

have

to

be

depressed.

[Keyboard

position

code

of

model

vs.

key

to

be

depressed]

[All

key

position

code]

|

ER-

2395

[ER-1920]

[ER-2385]

[ER-2395]

Fig.

7-5

@

Description

eee

re

ee

Until

the

depression

of

the

[TL]

or

[CA/AT]

key,

the

sum

of

key

position

codes

is

compared

with

the

sum

check

data,

except

for

the

[TL]

or

[CA/AT]

key.

|

@

Termination

=

ree

eon

The

test

terminates

with

the

depression

of

the

[TL]

or

[CA/AT]

key

and

the

termination

printout

is

produced.

|

Termination

printout

02

Termination

printout

with

error

NOTE:

Sum

check

data

The

sum

check

data

shown

in

the

example

is

based

on

the

standard

key

layout

for

the

each

model.

If

the

machine

has

a

key

layout

other

than

the

standard

layout,

the

sum

check

must

be

calculated

by

adding

all

the

_key

position

codes

to

be

depressed,

then

use

the

sum

as

its

sum

check

data.

(Refer

to

Fig.

7-1)

Sharp ER-1910 Bedienungsanleitung

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