2 | Spark-100 HW user manual v1.3
Contents
1 Scope..................................................................................................................................................... 4
1.1 SoM introduction ............................................................................................................................. 4
1.2 Block diagram................................................................................................................................... 5
2 Spark-100 Integration guide ................................................................................................................. 6
2.1 Power considerations ...................................................................................................................... 6
2.1.1 VCCBAT - FPGA Encryption Key power.................................................................................... 6
2.1.2 Spark Power scheme ............................................................................................................... 6
2.1.3 Bank 3B and 4A - Programmable Power levels ....................................................................... 7
2.1.4 Bank3A and Bank4A Vref ...................................................................................................... 10
2.2 Reset sources .................................................................................................................................10
2.3 HPS Interfaces................................................................................................................................ 12
2.3.1 USB ........................................................................................................................................ 12
2.3.2 Ethernet port......................................................................................................................... 13
2.3.3 UART...................................................................................................................................... 13
2.3.4 CAN........................................................................................................................................ 13
2.3.5 I2C overview.......................................................................................................................... 14
2.3.6 I2C Mapping ..........................................................................................................................15
2.3.7 SPI.......................................................................................................................................... 17
2.3.8 JTAG....................................................................................................................................... 17
2.4 Clocks scheme................................................................................................................................ 19
2.4.1 Basic clock architecture –SE SOC devices............................................................................. 19
2.4.2 Advance clock Configuration –SX SOC assembly only..........................................................19
2.5 FPGA............................................................................................................................................... 22
2.5.1 FPGA IOs variation................................................................................................................. 22
2.5.2 FPGA IOs................................................................................................................................ 23
2.5.3 Transceivers ..........................................................................................................................23
2.5.4 FPGA configuration ...............................................................................................................23
2.6 HPS Memories scheme .................................................................................................................. 24
2.6.1 QSPI NOR memory ................................................................................................................ 25
2.6.2 EEPROM.................................................................................................................................25
2.6.3 eMMC (iNAND)...................................................................................................................... 25
