Shugart SA100 Bedienungsanleitung

TABLE OF CONTENTS

1.0 Introduction

.......................................................................

1.1

General Description

..............................................................

1.2 Winchester Technology

............................................................

1.3 Specification Summary

............................................................

.3.1

Physical Specifications

..........................................................

1.3.2 Reliability Specifications

.........................................................

1.3.3 Performance Specifications

.......................................................

2.0 Theory ofOperation

.................................................................

2.1

Introduction

.....................................................................

2.2 Power

Reset Circuit

............................................................

2.3 Drive Ready (Control PCB/Stepper

PCB)

...............................................

2.4 Auto Recal (Stepper Logic

PCB)

.....................................................

2.5 Stepping

.......................................................................

2.5.1

Buffered Mode Stepping

..........................................................

2.5.2 Normal Stepping

................................................................

2.6 Stepper Driver(Control

PCB)

........................................................

2.7 Read (Control

PCB,

Refer to Figure

.................................................

2.8 Write

..........................................................................

2.9 Error Detection (Control

PCB)

.......................................................

LIST OF ILLUSTRATIONS

Figure

Typical Step Rate Ramp Curve

...................................................

Step Timing

..................................................................

Read Channel Block Diagram

....................................................

1.0 INTRODUCTION

1.1

GENERAL DESCRIPTION

The Shugart Model 1000 series disk drive is a random access storage device with one or two non-remoyable

disks as storage media. Each disk surface employs one movable head to service 256 data tracks. The

two models of the

1000 series are the

1002 and the

1004 with single and double platters respective-

ly.

The

1002 provides 5 megabytes accessed by 2 movable heads and the

1004 provides 10 megabytes

accessed by 4 movable heads.

Low cost and unit reliability are achieved through the use of a unique band actuator design. The inherent

simplicity of mechanical construction and electronic controls allows maintenance free operation throughout

the life of the drive. .

Mechanical and contamination protection for the head, actuator and disks are provided by

impact resis-

tant plastic and die cast aluminum enclosure. A self contained recirculating system supplies clean air

through a 0.3 micron absolute filter. Another 0.3 micron absolute filter allows pressure equalization with am-

bient air without chance of contamination.

The

SA1

000 fixed disk drive's interface

similar to the Shugart

family of floppy disk drives. The SA1000

designed to fit into the same physical space

the

floppies. However, existing floppy controllers are

not compatible with the

1000 due to differences

the data transfer rates.

Key Features:

Storage Capacity of 5.33 or 10.67 megabytes.

Winchester design reliability.

Same physical size and identical mounting configuration as the SA800/850 floppies.

Uses the same

D.C.

voltages as the SA800/850 floppies.

Proprietary Fas Flex III band actuator.

4.34 Mbits/second transfer rate.

Simple floppy-like interface.

1.2 WINCHESTER

TECHNOLOGY

The

1000 disk drive employs Winchester technology. The term Winchester refers to several unique

features about the drive. They are:

* Environmentally sealed chamber for heads and disks.

* Disk surface lubricated to facilitate magnetic head take off and landing without damage to the media

(The heads can land randomly anywhere

the surface of the media).

* A head that flies 19 micro inches above the surface of the media.

* Reduced head load force of 9.5 grams which allows the heads to rest

the surface of media prior to

take off

(The

spindle speed for head take off

approximately 500 rpm). .

The close proximity of the heads to the recording media permits recording densities of 6270 bits-per-inch.

This recording density allows 10 megabytes of data to

stored on

8-inch drive. Sealing the chamber that

houses the disk and head assemblies prevents contaminants from reaching the disk surface. The 0.3 micron

absolute breather and recirculating filters keep the environment inside the chamber free from undesirable

particulate contaminants.

UNDER

CONDITION MUST THE DRIVE

UNSEALED

THE

FIELD. A CLASS 100 CLEAN

ROOM

EN-

VIRONMENT

NEEDED

FOR

UNDER-THE-BUBBLE

REPAIR.

1.3 SPECIFICATION SUMMARY

1.3.1 PHYSICAL SPECIFICATIONS

Environmental Limits

Ambient Temperature =

Relative Humidity =

Maximum Wet Bulb =

50°

to 115°F

(10°

46°C)

BO/o

BO%

7BoF

non-condensing

Power Requirements

50/60 Hz ± 0.5Hz

100/115

VAC

Installations =

200/230

VAC

Installations = 90-127V at 0.75A typical

BO-253V

at 0.3BA typical

Voltage Requirements

+24VDC ± 10% 2.BA typical during stepping

(0.2A typical steady state, non stepping)

+5VDC ± 2.0A typical during stepping

(3.6A typical non-stepping)

-5VDC ±

(-7

to -16VDC optional) .2A typical

Mechanical Dimensions

Rack Mount Standard Mount

Height = 4.62

in.

(117.3mm) 4.62

in.

(117.3mm)

Width =

B.55

(217.2mm) 9.50 in. (241.3mm)

Depth = 14.25 in. (362.0mm) 14.25 in. (362.0mm)

Heat Dissipation =

511

BTU/Hr. typical (150 Watts)

1.3.2 RELIABILITY SPECIFICATIONS

MTBF:

B,OOO

POH

typical usage

PM:

None required

MTTR:

minutes

Component Life: 5 years

Error Rates: Soft Read Errors:

Hard Read Errors:

Seek Errors:

1 per 10

bits read

1 per

1012

bits read

1 per 106 seeks

1.3.3 PERFORMANCE SPECIFICATIONS

Capacity SA1002 SA1004

Unformatted

Per Drive 5.33 Mbytes 10.67 Mbytes

Per Surface 2.67 Mbytes 2.67 Mbytes

Per Track 10.4 Kbytes 10.4 Kbytes

Formatted

Per Drive 4.2 Mbytes

B.4

Mbytes

Per Surface

2.1

Mbytes

2.1

Mbytes

Per Track

B.2

Kbytes

B.2

Kbytes

Per Sector 256 bytes 256 bytes

Sectors/Track

Transfer Rate 4.34 Mbits/sec 4.34 Mbits/sec

Access Time

Track to Track

Average

Maximum

Average Latency

19 msec

msec

150 msec

9.6 msec

1.3.4 FUNCTIONAL SPECIFICATIONS

Rotational Speed

Recording Density

Flux Density

Track Density

Cylinders

Tracks

R/W

Heads

Disks

3125

rpm

6270

bpi

6270 fci

172 tpi

256

512

2.0 THEORY OF OPERATION

2.1

INTRODUCTION

19 msec

msec

150 msec

9.6 msec

3125 rpm

6270 bpi

6270 fci

172 tpi

256

1024

This section will functionally describe the major circuits of the

SA1

000. For interface timing, refer to

SA1

000

OEM

manual

39010.

2.2 POWER ON RESET CIRCUIT (POR)

order to generate a -paR (Power

Reset) signal, a simple switching circuit

the control

PCB

used.

This circuit utilizes capacitor

C4,

transistor

and two biasing resistors

R67

and

R68.

When initial

D.C.

voltages are applied to the drive,

charges

from 0 volts preventing

from turning on. This establishes

a low

the .output of

5C.

It takes approximately 50ms for

to charge

enough to turn

05.

Once

turned

on,

5C8 will remain high until power

removed.

The

following latches are cleared during the power-on phase:

Resets the fault latch,

the Control

PCB.

the stepper

PCB

paR

loads counter chip

with a hex count of

which

translated at the de-

coder chip

1 (phase

A).

Resets the seek complete latch

2A,

allows seek complete to

active at the interface if the

read/write heads are located at Track 000.

Sets the Auto-Recal latch

the stepper

PCB.

-Clears the step enable latch, 1C

the stepper

PCB.

-Loads track count buffer IC's

and 4B to a hex count of

the stepper

PCB.

After the reset initialization

completed the drive waits for the ready condition to occur.

2.3 DRIVE READY (CONTROL PCB/STEPPER PCB)

The

drive ready condition occurs when the disk spindle speed

above

of its nominal velocity

2968

RPM's).

The

ready circuit

derived by comparing the time between two successive index pulses to a fixed

time reference. The index detection circuit consists of

op amp differentiator and a one shot schmitt trig-

ger. A zero detection at the output of the differentiator circuit would generate a

10p,s

pulse at the output of

7B7. The frequency of the index pulse

depended upon the rated rotational velocity of the disk. The fre-

quency period

equal to 19.2ms when the disk

rotating at the rated speed

(312S

rpm).

At the Stepper

PCB

active low index signal presets the parallel inputs to counters 1E and

2E.

These

counters are clocked by a

271

Khz

signal. It takes approximately 20 ms for 1Eand

to overflow. A low, out

of counter 1

E14,

resets speed latches 1D and

SF.

The

speed latches will remain cleared if the time between

two index pulses

greater than 20.04 ms, indicating a not ready condition. When the disk

rotating above

of its nominal rotational speed, incoming indexes will preset 1E and

before they time out. The next

index signal will set latch

and

SF6

will go low indicating

active ready condition.

2.4 AUTO RECAL (STEPPER LOGIC P.C.B.)

Auto Recal

performed if two basic conditions are satisfied: One

that drive ready has to be

the ac-

tive state, and the other

that the heads must not be positioned over track zero. Assuming that these condi-

tions are met, the following logic functions are performed. The Index signal

gated through IC's

and 4F.

The

Step Enable signal is

the inactive state, which allows the index signal to be used

a pseudo step

signal.

The

Auto Recal latch

(3C)

currently

the set position, indicating the direction of motion of the

read/write heads will begin to recalibrate

the normal mode of operation until the track zero phase (phase

detected. The seek settle timer 1

Band

will time out

approximately 18ms, activating Seek Com-

plete at the interface.

The

drive

now ready for normal operation.

2.5 STEPPING

The

STEP

interface line is a control signal, which causes the read/write heads to move

the direction defin-

by the DIRECTION

line.

The

Direction

line must

stable at least 1

OOns

before the leading edge of

the Step pulse.

There are two basic modes of operation of stepping the read/write heads, the normal mode and the buffered

mode.

order to implement either of these two modes of operation, there are several conditions that must

initiated before stepping can

accomplished.

Write Gate must

inactive.

Drive Select must

active.

Ready must be active, and Seek Complete true.

2.5.1

BUFFERED MODE STEPPING

this mode, the step pulses are received at a high rate (pulse period separation between

3.0p,s

and

200p,s),

and buffered into step counters 4B and

SE.

Once all step pulses have been received,

s"'tep

rate timer

will output a low, which

gated through IC's

3D1

3ES

and

4FS.

This logic function

used to prevent any

more step pulses from being received.

The

actual stepping operation will now begin, depending upon the step count loaded into the step count buf-

fers, 4B and

SE.

For discussion, assume a

10 track seek operation.

Counters

and

will hold a count of 316 and 116 respectively. The count of

will be compared to the

count of

3A (this count currently equals zero). Since

48's

count is greater than the count of

3A,

4A,

5 will output a logical one. A high signal out of 4A will select the outputs from counters 3A through 38.

This particular count will

used

address to prom 58.

The

firmware control for each address

design-

to select the appropriate step rate time (see figure

1).

The

approximate time for the

rst step rate is 200l!s

(Prom address 1610)

.and

the second step rate time

approximately 560l!s (Prom address

10), The output

from

5A,

14, will clock the divide-by-2 flip flop at 1

The output (low to high transition) from the flip flop

(IC

9),

has several important functions:

Enables the

141!s

window generator circuit (step enable signal).

Enables sequencing from the phase counter.

The phase counter will either count up or down depending upon the direction line. (For phase

counter timing see figure

2).

Enables the down count from counter 48.

The

step count from counter

is continuously compared to the count of

3A,

until 3A becomes greater than

the count of 48. At this time data selector

will select the lower value step count of

48. Slower and

slower step times are selected (ramping down) until the step time

at the rate of the initial step.

For longer seeks, the step speed will increase (ramp up) during the first 15 steps, until the maximum step

speed

reached. The speed will

maintained until only 15 steps remain. Now the step speed is decreased

(ramp down) gradually down to the initial 1120 usec rate. The purpose of ramping up is to decrease the total

seek time, and the purpose of ramping down is to slow the stepper mass down

order that a settle time of

18 msec, can be maintained.

STEP

COUNT 8

____

o 100 200 300 400 500 600 700 800 900 1000 1100 1200

TIME IN MICRO SECONDS

FIGURE 1. TYPICAL STEP RATE RAMP CURVE

GENERAL STEP PHASE

TIMING

I I I I I I

081

I I I I I I I I L,/I

I I I I I I I

ocl

I I I I I I I I

Sf-

I I I I I I I I

1Yo U I I U I I U I I

I I I I I I I I

1YI I U I I U I U I

I I I I I I I I

I U I I U

LIT

I I

I I I I I I I I I

I I I U I I I U I U

I I I I I I I I I

-081 I I

I I I I I I

-082

I I I I I I I

·1

I I I I I

-OA2

I I I I I

I I I I

-OAI I I

(AI)

(AI81)(81)(A281)(A2)(A282)(82)

(AI82)

TRUTH TABLE FOR PHASE SEQUENCES

-OAI -081 -OM -082

a 0 a a 1 1

a 0 1 a a

a a a 1 1

r 1 a a

11~PHASEA

1 0 a a 1

1 0 1 a a

w 1 a 1 a

(/),

1 0 a

FIGURE

STEP TIMING

Inhaltsverzeichnis

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