SiFive FE310-G002 Bedienungsanleitung

SiFive FE310-G002 Manual

v19p05

SiFive FE310-G002 Manual

Proprietary Notice

Information in this document is provided “as is,” with all faults.

SiFive expressly disclaims all warranties, representations, and conditions of any kind, whether

express or implied, including, but not limited to, the implied warranties or conditions of mer-

chantability, fitness for a particular purpose and non-infringement.

SiFive does not assume any liability rising out of the application or use of any product or circuit,

and specifically disclaims any and all liability, including without limitation indirect, incidental, spe-

cial, exemplary, or consequential damages.

SiFive reserves the right to make changes without further notice to any products herein.

Release Information

Version Date Changes

v19p04 April 11, 2019 • Initial release

v19p05 May 08, 2019 • Correct UART1 pin assignment

Contents

1 Introduction .............................................................................................................. 8

1.1 F 310-G002 Overview ................................................................................................8

1.2 31 RISC‑V Core ..................................................................................................... 10

1.3 Interrupts ................................................................................................................. 10

1.4 On-Chip Memory System...........................................................................................11

1.5 Always-On (AON) Block ............................................................................................11

1.6 GPIO Complex ......................................................................................................... 11

1.7 Universal Asynchronous Receiver/Transmitter.............................................................11

1.8 Hardware Serial Peripheral Interface (SPI) ..................................................................11

1.9 Pulse Width Modulation.............................................................................................12

1.10 I²C ......................................................................................................................... 12

1.11 Debug Support ....................................................................................................... 12

2 List of Abbreviations and Terms .................................................................13

3 E31 RISC-V Core .................................................................................................. 15

3.1 Instruction Memory System........................................................................................15

3.1.1 I-Cache Reconfigurability ..................................................................................16

3.2 Instruction Fetch Unit ................................................................................................16

3.3 xecution Pipeline .................................................................................................... 16

3.4 Data Memory System................................................................................................17

3.5 Atomic Memory Operations........................................................................................17

3.6 Supported Modes ..................................................................................................... 18

3.7 Physical Memory Protection (PMP).............................................................................18

3.7.1 Functional Description ......................................................................................18

3.7.2 Region Locking ................................................................................................18

3.8 Hardware Performance Monitor..................................................................................19

4 emory ap ........................................................................................................... 21

5 Boot Process.......................................................................................................... 23

5.1 Reset Vector............................................................................................................. 23

5.1.1 Mask ROM (MROM).........................................................................................24

5.1.2 One-Time Programmable (OTP) Memory ...........................................................24

5.1.3 Quad SPI Flash Controller (QSPI)......................................................................24

6 Clock Generation .................................................................................................25

6.1 Clock Generation Overview .......................................................................................25

6.2 PRCI Address Space Usage ......................................................................................26

6.3 Internal Trimmable Programmable 72 MHz Oscillator (HFROSC) ..................................26

6.4 xternal 16 MHz Crystal Oscillator (HFXOSC).............................................................27

6.5 Internal High-Frequency PLL (HFPLL) ........................................................................28

6.6 PLL Output Divider.................................................................................................... 30

6.7 Internal Programmable Low-Frequency Ring Oscillator (LFROSC) ................................31

6.8 Alternate Low-Frequency Clock (LFALTCLK)...............................................................32

6.9 Clock Summary ........................................................................................................ 32

7 Power odes.......................................................................................................... 33

7.1 Run Mode ................................................................................................................ 33

7.2 Wait Mode................................................................................................................ 33

7.3 Sleep Mode.............................................................................................................. 33

8 Interrupts.................................................................................................................. 35

8.1 Interrupt Concepts .................................................................................................... 35

8.2 Interrupt Operation.................................................................................................... 36

8.2.1 Interrupt ntry and xit .....................................................................................36

8.3 Interrupt Control Status Registers...............................................................................37

8.3.1 Machine Status Register (mstatus)..................................................................37

8.3.2 Machine Trap Vector (mtvec)............................................................................37

8.3.3 Machine Interrupt nable (mie).........................................................................39

8.3.4 Machine Interrupt Pending (mip).......................................................................39

8.3.5 Machine Cause (mcause).................................................................................39

8.4 Interrupt Priorities ..................................................................................................... 40

8.5 Interrupt Latency....................................................................................................... 41

9 Core-Local Interruptor (CLINT).....................................................................42

9.1 CLINT Memory Map.................................................................................................. 42

9.2 MSIP Registers......................................................................................................... 42

9.3 Timer Registers ........................................................................................................ 43

10 Platform-Level Interrupt Controller (PLIC)...........................................44

10.1 Memory Map .......................................................................................................... 44

10.2 Interrupt Sources .................................................................................................... 45

10.3 Interrupt Priorities.................................................................................................... 46

10.4 Interrupt Pending Bits ..............................................................................................46

10.5 Interrupt nables..................................................................................................... 47

10.6 Priority Thresholds .................................................................................................. 48

10.7 Interrupt Claim Process ...........................................................................................48

10.8 Interrupt Completion................................................................................................49

11 Error Device ......................................................................................................... 51

12 One-Time Programmable emory (OTP) Peripheral......................52

12.1 Memory Map .......................................................................................................... 52

12.2 Programmed-I/O lock register (otp_lock)................................................................53

12.3 Programmed-I/O Sequencing...................................................................................54

12.4 Read sequencer control register (otp_rsctrl)........................................................54

12.5 OTP Programming Warnings....................................................................................54

12.6 OTP Programming Procedure ..................................................................................55

13 Always-On (AON) Domain ............................................................................56

13.1 AON Power Source.................................................................................................57

13.2 AON Clocking......................................................................................................... 57

13.3 AON Reset Unit ...................................................................................................... 57

13.4 Power-On Reset Circuit ...........................................................................................57

13.5 xternal Reset Circuit..............................................................................................58

13.6 Reset Cause........................................................................................................... 58

13.7 Watchdog Timer (WDT) ...........................................................................................58

13.8 Real-Time Clock (RTC)............................................................................................58

13.9 Backup Registers.................................................................................................... 58

13.10 Power-Management Unit (PMU) .............................................................................58

13.11 AON Memory Map.................................................................................................58

14 Watchdog Timer (WDT) ..................................................................................61

14.1 Watchdog Count Register (wdogcount)...................................................................61

14.2 Watchdog Clock Selection .......................................................................................62

14.3 Watchdog Configuration Register (wdogcfg).............................................................62

14.4 Watchdog Compare Register (wdogcmp)...................................................................63

14.5 Watchdog Key Register (wdogkey)..........................................................................63

14.6 Watchdog Feed Address (wdogfeed).......................................................................64

14.7 Watchdog Configuration ..........................................................................................64

14.8 Watchdog Resets.................................................................................................... 64

14.9 Watchdog Interrupts (wdogip0)...............................................................................64

15 Power- anagement Unit (P U).................................................................65

15.1 PMU Overview........................................................................................................ 66

15.2 Memory Map .......................................................................................................... 66

15.3 PMU Key Register (pmukey)....................................................................................67

15.4 PMU Program......................................................................................................... 67

15.5 Initiate Sleep Sequence Register (pmusleep)...........................................................68

15.6 Wakeup Signal Conditioning ....................................................................................68

15.7 PMU Interrupt nables (pmuie) and Wakeup Cause (pmucause)...............................69

16 Real-Time Clock (RTC) ...................................................................................71

16.1 RTC Count Registers (rtccounthi/rtccountlo)...................................................71

16.2 RTC Configuration Register (rtccfg)......................................................................72

16.3 RTC Compare Register (rtccmp)............................................................................72

17 General Purpose Input/Output Controller (GPIO) ............................74

17.1 GPIO Instance in F 310-G002.................................................................................76

17.2 Memory Map .......................................................................................................... 76

17.3 Input / Output Values ...............................................................................................76

17.4 Interrupts................................................................................................................ 77

17.5 Internal Pull-Ups ..................................................................................................... 77

17.6 Drive Strength......................................................................................................... 77

17.7 Output Inversion ..................................................................................................... 77

17.8 HW I/O Functions (IOF) ...........................................................................................77

18 Universal Asynchronous Receiver/Transmitter (UART)...............79

18.1 UART Overview ...................................................................................................... 79

18.2 UART Instances in F 310-G002...............................................................................79

18.3 Memory Map .......................................................................................................... 80

18.4 Transmit Data Register (txdata).............................................................................80

18.5 Receive Data Register (rxdata)..............................................................................80

18.6 Transmit Control Register (txctrl).........................................................................81

18.7 Receive Control Register (rxctrl)..........................................................................81

18.8 Interrupt Registers (ip and ie)................................................................................82

18.9 Baud Rate Divisor Register (div).............................................................................82

19 Serial Peripheral Interface (SPI) ................................................................84

19.1 SPI Overview.......................................................................................................... 84

19.2 SPI Instances in F 310-G002 ..................................................................................84

19.3 Memory Map .......................................................................................................... 85

19.4 Serial Clock Divisor Register (sckdiv).....................................................................86

19.5 Serial Clock Mode Register (sckmode).....................................................................87

19.6 Chip Select ID Register (csid)................................................................................87

19.7 Chip Select Default Register (csdef).......................................................................88

19.8 Chip Select Mode Register (csmode)........................................................................88

19.9 Delay Control Registers (delay0 and delay1).........................................................89

19.10 Frame Format Register (fmt).................................................................................89

19.11 Transmit Data Register (txdata)...........................................................................90

19.12 Receive Data Register (rxdata)............................................................................91

19.13 Transmit Watermark Register (txmark)..................................................................91

19.14 Receive Watermark Register (rxmark)...................................................................92

19.15 SPI Interrupt Registers (ie and ip)........................................................................92

19.16 SPI Flash Interface Control Register (fctrl)..........................................................93

19.17 SPI Flash Instruction Format Register (ffmt)..........................................................93

20 Pulse Width odulator (PW ) ...................................................................94

20.1 PWM Overview ....................................................................................................... 94

20.2 PWM Instances in F 310-G002 ...............................................................................95

20.3 PWM Memory Map .................................................................................................95

20.4 PWM Count Register (pwmcount)............................................................................96

20.5 PWM Configuration Register (pwmcfg).....................................................................97

20.6 Scaled PWM Count Register (pwms).........................................................................98

20.7 PWM Compare Registers (pwmcmp0–pwmcmp3)........................................................98

20.8 Deglitch and Sticky Circuitry.....................................................................................99

20.9 Generating Left- or Right-Aligned PWM Waveforms .................................................100

20.10 Generating Center-Aligned (Phase-Correct) PWM Waveforms ................................100

20.11 Generating Arbitrary PWM Waveforms using Ganging ............................................101

20.12 Generating One-Shot Waveforms .........................................................................102

20.13 PWM Interrupts................................................................................................... 102

21 Inter-Integrated Circuit (I²C) aster Interface ..................................103

21.1 I²C Instance in F 310-G002...................................................................................103

22 Debug .................................................................................................................... 104

22.1 Debug CSRs ........................................................................................................ 104

22.1.1 Trace and Debug Register Select (tselect)..................................................104

22.1.2 Trace and Debug Data Registers (tdata1-3)................................................105

22.1.3 Debug Control and Status Register (dcsr).....................................................106

22.1.4 Debug PC dpc .............................................................................................106

22.1.5 Debug Scratch dscratch.............................................................................106

22.2 Breakpoints .......................................................................................................... 106

22.2.1 Breakpoint Match Control Register mcontrol ................................................106

22.2.2 Breakpoint Match Address Register (maddress).............................................108

22.2.3 Breakpoint xecution ....................................................................................108

22.2.4 Sharing Breakpoints Between Debug and Machine Mode ................................109

22.3 Debug Memory Map..............................................................................................109

22.3.1 Debug RAM and Program Buffer (0x300–0x3FF)...........................................109

22.3.2 Debug ROM (0x800–0xFFF)........................................................................109

22.3.3 Debug Flags (0x100–0x110,0x400–0x7FF)................................................110

22.3.4 Safe Zero Address........................................................................................110

23 Debug Interface................................................................................................111

23.1 JTAG TAPC State Machine ....................................................................................111

23.2 Resetting JTAG Logic............................................................................................112

23.3 JTAG Clocking...................................................................................................... 112

23.4 JTAG Standard Instructions ...................................................................................113

23.5 JTAG Debug Commands .......................................................................................113

24 References.......................................................................................................... 114

Chapter 1

Introduction

The F 310-G002 is the second revision of the General Purpose Freedom 300 family.

The F 310-G002 is built around the 31 Core Complex instantiated in the Freedom 300 plat-

form and fabricated in the TSMC CL018G 180nm process. This manual serves as an architec-

tural reference and integration guide for the F 310-G002.

The F 310-G002 is compatible with all applicable RISC‑V standards, and this document should

be read together with the official RISC‑V user-level, privileged, and external debug architecture

specifications.

1.1 FE310-G002 Overview

Figure 1 shows the overall block diagram of the F 310-G002.

A feature summary table can be found in Table 1.

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