SiFive E300 Bedienungsanleitung

SiFive E300 Platform Reference Manual

Version 1.0.1

SiFive, Inc.

2SiFive E300 Platform Reference Manual, Version 1.0.1

SiFive E300 Platform Reference Manual

Proprietary Notice

Information in this document is provided “as is”, with all faults.

SiFive expressly disclaims all warranties, representations and conditions of any kind, whether ex-

press or implied, including, but not limited to, the implied warranties or conditions of merchantabil-

ity, ﬁtness for a particular purpose and non-infringement.

SiFive does not assume any liability rising out of the application or use of any product or circuit, and

speciﬁcally disclaims any and all liability, including without limitation indirect, incidental, special,

exemplary, or consequential damages.

SiFive reserves the right to make changes without further notice to any products herein.

Release Information

Version Date Changes

1.0.1 Dec 19, 2016 Minor clariﬁcations on PWM, SPI, AON register ﬁelds

1.0 November 29, 2016 Initial release for HiFive1 release.

ii SiFive E300 Platform Reference Manual, Version 1.0.1

Contents

SiFive E300 Platform Reference Manual i

1 Introduction 1

1.1 BlockDiagram .......................................... 1

1.2 Conﬁgurable E31 RISC-V Coreplex . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1

1.3 CustomAccelerators....................................... 2

1.4 On-ChipMemory......................................... 2

1.5 Execute-in-Place Quad-SPI Flash controller . . . . . . . . . . . . . . . . . . . . . . . . . . 2

1.6 PeripheralDevices........................................ 3

1.7 Platform-Level Interrupt Controller . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3

1.8 Always-On Block and Power Management . . . . . . . . . . . . . . . . . . . . . . . . . . . 3

1.9 DebugSupport.......................................... 3

1.10 SoftwareTools .......................................... 3

2 E300 Platform Memory Map 5

3 E300 Power Modes 7

3.1 RunMode............................................. 7

3.2 WaitMode ............................................ 7

3.3 SleepMode............................................ 7

4 E300 Clock Generation 9

4.1 ClockGenerationOverview................................... 9

4.2 Internal Trimmable Programmable 72 MHz Oscillator (HFROSC) . . . . . . . . . . . . . . 9

4.3 External 16 MHz Crystal Oscillator (HFXOSC) . . . . . . . . . . . . . . . . . . . . . . . . 11

4.4 Internal High-Frequency PLL (HFPLL) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11

4.5 PLLOutputDivider........................................ 13

4.6 Internal Low-Frequency Oscillator (LFRCOSC) . . . . . . . . . . . . . . . . . . . . . . . . 13

4.7 External 32.768 kHz Low-Frequency Crystal Oscillator (LFXOSC) . . . . . . . . . . . . . 13

iii

iv SiFive E300 Platform Reference Manual, Version 1.0.1

5 E300 Always-On (AON) Domain 15

5.1 AONPowerSource ....................................... 15

5.2 AON Clocking and Tilelink Slave Port . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15

5.3 AONResetUnit ......................................... 15

5.3.1 Power-OnResetCircuit ............................... 16

5.3.2 ExternalResetCircuit ................................ 16

5.3.3 ResetCause ..................................... 17

5.4 WatchdogTimer(WDT)..................................... 17

5.5 Real-TimeClock(RTC) ..................................... 17

5.6 BackupRegisters ........................................ 17

5.7 Power-Management Unit (PMU) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17

5.8 AONMemoryMap........................................ 17

6 E300 Power-Management Unit (PMU) 19

6.1 PMUOverview.......................................... 19

6.2 PMU Key Register (pmukey)................................... 19

6.3 PMUProgram .......................................... 19

6.4 Initiate Sleep Sequence Register (pmusleep) ......................... 20

6.5 WakeupSignalConditioning .................................. 21

6.6 PMU Interrupt Enables (pmuie) and Wakeup Cause (pmucause)............... 21

6.7 MemoryMap........................................... 22

7 E300 Power, Reset, Clock, Interrupt (PRCI) Control and Status Registers 23

7.1 PRCIAddressSpaceUsage .................................. 23

8 E300 Watchdog Timer (WDT) 25

8.1 Watchdog Count Register (wdogcount)............................. 25

8.2 WatchdogClockSelection.................................... 26

8.3 Watchdog Conﬁguration Register wdogcfg ........................... 26

8.4 Watchdog Compare Register (wdogcmp) ............................ 27

8.5 Watchdog Key Register (wdogkey) ............................... 27

8.6 Watchdog Feed Address (wdogfeed).............................. 27

8.7 WatchdogConﬁguration..................................... 27

8.8 WatchdogResets ........................................ 27

8.9 Watchdog Interrupts (wdogcmpip)................................ 28

9 E300 Real-Time Clock (RTC) 29

9.1 RTC Count Registers rtchi/rtclo ............................... 29

9.2 RTC Conﬁguration Register rtccfg .............................. 29

9.3 RTC Compare Register rtccmp ................................. 30

10 E300 Backup Registers 31

11 General Purpose Input/Output Controller (GPIO) 33

11.1 MemoryMap........................................... 33

11.2 Input/OutputValues ...................................... 33

11.3 Interrupts ............................................. 33

11.4 InternalPull-Ups......................................... 35

11.5 DriveStrength .......................................... 35

11.6 OutputInversion ......................................... 35

11.7 HWI/OFunctions(IOF) ..................................... 35

11.8 BehaviorDuringSleepMode .................................. 36

12 Universal Asynchronous Receiver/Transmitter (UART) 37

12.1 UARTOverview ......................................... 37

12.2 MemoryMap........................................... 37

12.3 Transmit Data Register (txdata) ................................ 38

12.4 Receive Data Register (rxdata) ................................ 38

12.5 Transmit Control Register (txctrl)............................... 38

12.6 Receive Control Register (rxctrl)............................... 39

12.7 Interrupt Registers (ip and ie) ................................. 39

12.8 Baud Rate Divisor Register (div)................................ 39

13 Serial Peripheral Interface (SPI) 41

13.1 SPIOverview........................................... 41

13.2 MemoryMap........................................... 41

13.3 Serial Clock Divisor Register (sckdiv)............................. 41

13.4 Serial Clock Mode Register (sckmode)............................. 42

13.5 Chip Select ID Register (csid) ................................. 43

13.6 Chip Select Default Register (csdef).............................. 43

13.7 Chip Select Mode Register (csmode).............................. 43

13.8 Delay Control Registers (delay0 and delay1)......................... 44

13.9 Frame Format Register (fmt) .................................. 44

13.10 Transmit Data Register (txdata) ................................ 45

13.11 Receive Data Register (rxdata) ................................ 45

13.12 Transmit Watermark Register (txmark)............................. 46

vi SiFive E300 Platform Reference Manual, Version 1.0.1

13.13 Receive Watermark Register (rxmark)............................. 46

13.14 Interrupt Registers (ie and ip) ................................. 46

13.15 SPI Flash Interface Control Register (fctrl) ......................... 47

13.16 SPI Flash Instruction Format Register (ffmt) ......................... 47

14 One-Time Programmable Memory (OTP) Peripheral 49

14.1 MemoryMap........................................... 49

14.2 Programmed-I/O lock register (otp lock) ........................... 49

14.3 Programmed-I/O Sequencing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 51

14.4 Read sequencer control register (otp rsctrl) ........................ 51

15 E300 Pulse-Width Modulation (PWM) Peripheral 53

15.1 PWMOverview.......................................... 53

15.2 PWMMemoryMap ....................................... 53

15.3 PWM Count Register (pwmcount)................................ 53

15.4 PWM Conﬁguration Register (pwmcfg)............................. 54

15.5 PWM Compare Registers (pwmcmp0–pwmcmp3)......................... 55

15.6 Deglitch and Sticky circuitry . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 56

15.7 Generating Left- or Right-Aligned PWM Waveforms . . . . . . . . . . . . . . . . . . . . . 56

15.8 Generating Center-Aligned (Phase-Correct) PWM Waveforms . . . . . . . . . . . . . . . 57

15.9 Generating Arbitrary PWM Waveforms using Ganging . . . . . . . . . . . . . . . . . . . . 58

15.10 Generating One-shot Waveforms . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 58

15.11 PWMInterrupts.......................................... 58

Chapter 1

Introduction

The E300 platform is the ﬁrst member of SiFive’s Freedom Everywhere family of customizable

RISC-V SoCs. By combining a highly conﬁgurable base platform with customer-speciﬁc hardware

extensions, the Freedom Everywhere family provides low-NRE and rapid time-to-market solutions

for performance, cost, and power-sensitive embedded and IoT markets.

Each E300 SoC includes a SiFive E3 series RISC-V Coreplex with integrated instruction and data

memories, a platform-level interrupt controller, on-chip debug unit, and an extensive selection of

peripheral devices. This manual should be read together with the E3 Coreplex manual.

All aspects of the base E300 platform can be ﬂexibly conﬁgured. In addition, the platform can be

readily extended with customer-speciﬁc instruction-set extensions, custom coprocessors, custom

accelerators, custom I/O, and custom always-on blocks. The resulting application-speciﬁc E300

SoC is optimized for manufacture in a TSMC 180nm process, and delivered as packaged tested

parts by SiFive.

Block Diagram

Figure 1.1 shows the top-level block diagram of the E300 platform. The heart of the current

E300 platform is an E31 Coreplex, which contains an E31 RISC-V processor, instruction and data

memories, the platform-level interrupt controller (PLIC), a central DMA controller, and a debug

module.

Conﬁgurable E31 RISC-V Coreplex

The conﬁgurable E31 RISC-V Coreplex provides a high-performance single-issue in-order 32-bit

execution pipeline, with a peak sustained execution rate of one instruction per clock cycle. The

Freedom E300 platform supports most conﬁguration options of the E31 core as described in the

E3 Coreplex manual, except for the following:

•Where present, the instruction cache line size is 32 bytes.

•The data cache is not supported.

The E3 Coreplex exports two TileLink attachments; a TileLink master port which can be used to

attach a custom accelerator, and a TileLink slave port to drive the platform bus. Both ports support

32-byte burst accesses over a 32-bit datapath.

2SiFive E300 Platform Reference Manual, Version 1.0.1

Freedom E300 Platform

Clock Generation

P-Bus: TileLink B32 D32

eFlash

E31 Coreplex

Platform-Level

Interrupt Control

TAPC

Debug Module

Debug SRAM

Instruction Fetch

RV32E/IMAFDCN

Branch Prediction

Integer Multiply/Divide

Inst. Decompressor

Memory Protection

Custom Instructions

Custom

Coprocessor

Instruction Buﬀer

MLoad/Store

dip

eip

lip

DMA

C-Bus

Instruction Cache

Instruction Fill/Prefetch M

Instruction SRAM

Mask ROM

Data SRAM

I-Bus

Quad SPI Flash

Custom Accelerator

Local Interrupts

Global Interrupts

EEPROM

Service

Requests

Always-On Block

Backup Registers

Real-Time Clock

Custom Always-On

Reset Unit

Watchdog Timer

GPIO Complex

PWM

Counter/Timer

UART

I2C

SPI

SRAM

OTP

FPU

Power Management

Figure 1.1: Top-Level Block Diagram of the E300 platform.

Custom Accelerators

Custom autonomous accelerators can be added to provide application-speciﬁc processing. The

custom accelerators can directly access on-chip memories and peripheral devices, and can gen-

erate and receive interrupts from the platform-level interrupt controller.

On-Chip Memory

The on-chip memory system can be ﬂexibly conﬁgured to include ROM, OTP, eFLASH,

NVM/EEPROM, and/or SRAM of various sizes.

Execute-in-Place Quad-SPI Flash controller

A dedicated Quad-SPI ﬂash controller can be added with support for a a memory-mapped burst-

read interface to support processor instruction cache or data cache reﬁlls from an external SPI

ﬂash memory. Memory burst writes are not supported. The external SPI ﬂash has a set of control

registers mapped into I/O space through which the external ﬂash can be written under software

control.

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