Silicon Laboratories C8051T620 Bedienungsanleitung

Full Speed USB EPROM MCU Family

C8051T620/1/6/7 & C8051T320/1/2/3

Analog Peripherals

-10-Bit ADC (‘T620/6/7 and ‘T320/1 only)

•Up to 500 ksps

•Up to 21 external inputs

•VREF from on-chip VREF, external pin, Internal 1.8 V

Regulator or VDD

•Internal or external start of conversion source

•Built-in temperature sensor

-Comparators

•Programmable hysteresis and response time

•Configurable as interrupt or reset source

•Low current (<0.5 µA)

USB Function Controller

-USB specification 2.0 compliant

-Full speed (12 Mbps) or low speed (1.5 Mbps) oper-

ation

-Integrated clock recovery; no external oscillator

required for full speed or low speed

-Supports eight flexible endpoints

-1 kB USB buffer memory

-Integrated transceiver; no external resistors

required

On-Chip Debug

-C8051F34A can be used as code development plat-

form; Complete development kit available

-On-chip debug circuitry facilitates full speed, non-

intrusive in-system debug

-Provides breakpoints, single stepping, 

inspect/modify memory and registers

Supply Voltage 1.8 to 5.25 V

-On-chip LDO for internal core supply

-Built-in supply voltage monitor

High-Speed 8051 µC Core

-Pipelined instruction architecture; executes 70% of

instructions in 1 or 2 system clocks

-Up to 48 MIPS throughput with 48 MHz clock

-Expanded interrupt handler

Memory

-Up to 3328 bytes internal data RAM (256 + up to

3072)

-Up to 64 kB byte-programmable EPROM code

memory

-EPROM can be programmed from firmware running

on the device

Digital Peripherals

-25 Port I/O with high sink current capability

-Hardware enhanced SPI™, SMBus™, and two

enhanced UART serial ports

-Four general purpose 16-bit counter/timers

-16-Bit programmable counter array (PCA) with five

capture/compare modules and enhanced PWM

functionality

Clock Sources

-Two internal oscillators:

•48 MHz: ±0.25% accuracy with clock recovery

enabled. Supports all USB and UART modes

•80/40/20/10 kHz low frequency, low power

-External oscillator: Crystal, RC, C, or CMOS Clock

-Can switch between clock sources on-the-fly; useful

in power saving modes

Package Options:

-5 x 5 mm QFN28 or QFN32

-9 x 9 mm LQFP32

Temperature Range: –40 to +85 °C

ANALOG

PERIPHERALS

64 kB

EPROM 3328 B SRAM

PORDEBUG CIRCUITRY

FLEXIBLE

INTERRUPTS

8051 CPU

(48 MIPS)

DIGITAL I/O

48 MHz PRECISION INTERNAL

OSCILLATOR

HIGH-SPEED CONTROLLER CORE

CROSSBAR

VOLTAGE

COMPARATORS

WDT

UART1

SMBus

PCA

Timer 0

Timer 1

Timer 2

Timer 3

Port 0

SPI

LOW FREQUENCY INTERNAL

OSCILLATOR

P3.0

10-bit

500 ksps

ADC

TEMP

SENSOR

VREF Port 1

Port 2

USB Controller /

Transceiver

UART0

C8051T620/1/6/7 & C8051T320/1/2/3

2 Rev. 1.2

Rev. 1.2 3

C8051T620/1/6/7 & C8051T320/1/2/3

Table of Contents

1. System Overview..................................................................................................... 15

2. Ordering Information............................................................................................... 21

3. Pin Definitions.......................................................................................................... 22

4. LQFP-32 Package Specifications........................................................................... 28

5. QFN-32 Package Specifications............................................................................. 30

6. QFN-28 Package Specifications............................................................................. 32

7. Electrical Characteristics........................................................................................ 34

7.1. Absolute Maximum Specifications..................................................................... 34

7.2. Electrical Characteristics................................................................................... 35

7.3. Typical Performance Curves............................................................................. 44

8. 10-Bit ADC (ADC0, C8051T620/6/7 and C8051T320/1 Only)................................. 45

8.1. Output Code Formatting.................................................................................... 46

8.2. 8-Bit Mode......................................................................................................... 46

8.3. Modes of Operation........................................................................................... 46

8.3.1. Starting a Conversion................................................................................ 46

8.3.2. Tracking Modes......................................................................................... 47

8.3.3. Settling Time Requirements...................................................................... 48

8.4. Programmable Window Detector....................................................................... 52

8.4.1. Window Detector Example........................................................................ 54

8.5. ADC0 Analog Multiplexer (C8051T620/6/7 and C8051T320/1 Only)................ 55

9. Temperature Sensor (C8051T620/6/7 and C8051T320/1 Only)............................. 57

9.1. Calibration ......................................................................................................... 58

10. Voltage Reference Options................................................................................... 59

11. Voltage Regulators (REG0 and REG1)................................................................. 61

11.1. Voltage Regulator (REG0)............................................................................... 61

11.1.1. Regulator Mode Selection....................................................................... 61

11.1.2. VBUS Detection...................................................................................... 61

11.2. Voltage Regulator (REG1)............................................................................... 64

12. CIP-51 Microcontroller........................................................................................... 66

12.1. Instruction Set.................................................................................................. 67

12.1.1. Instruction and CPU Timing.................................................................... 67

12.2. CIP-51 Register Descriptions.......................................................................... 73

13. Prefetch Engine...................................................................................................... 76

14. Comparator0 and Comparator1............................................................................ 77

14.1. Comparator Multiplexers ................................................................................. 84

15. Memory Organization............................................................................................ 87

15.1. Program Memory............................................................................................. 88

15.1.1. Derivative ID............................................................................................ 89

15.1.2. Temperature Offset Calibration............................................................... 89

15.1.3. Serialization............................................................................................. 89

15.2. Data Memory................................................................................................... 90

15.2.1. Internal RAM........................................................................................... 90

15.2.1.1. General Purpose Registers ............................................................ 90

C8051T620/1/6/7 & C8051T320/1/2/3

4 Rev. 1.2

15.2.1.2. Bit Addressable Locations.............................................................. 90

15.2.1.3. Stack ............................................................................................ 90

15.2.2. External RAM.......................................................................................... 91

15.2.3. Accessing USB FIFO Space................................................................... 91

16. Special Function Registers................................................................................... 95

17. Interrupts.............................................................................................................. 101

17.1. MCU Interrupt Sources and Vectors.............................................................. 102

17.1.1. Interrupt Priorities.................................................................................. 102

17.1.2. Interrupt Latency................................................................................... 102

17.2. Interrupt Register Descriptions...................................................................... 102

17.3. INT0 and INT1 External Interrupt Sources.................................................... 110

18. Program Memory (EPROM)................................................................................. 112

18.1. Programming the EPROM Memory............................................................... 112

18.1.1. EPROM Programming over the C2 Interface........................................ 112

18.1.2. EPROM In-Application Programming.................................................... 113

18.2. Security Options............................................................................................ 114

18.3. EPROM Writing Guidelines........................................................................... 114

18.3.1. VDD Maintenance and the VDD monitor .............................................. 114

18.3.2. PSWE Maintenance.............................................................................. 115

18.3.3. System Clock........................................................................................ 115

18.4. Program Memory CRC.................................................................................. 115

18.4.1. Performing 32-bit CRCs on Full EPROM Content ................................ 115

18.4.2. Performing 16-bit CRCs on 256-Byte EPROM Blocks.......................... 115

19. Power Management Modes................................................................................. 118

19.1. Idle Mode....................................................................................................... 118

19.2. Stop Mode..................................................................................................... 119

19.3. Suspend Mode .............................................................................................. 119

20. Reset Sources...................................................................................................... 121

20.1. Power-On Reset............................................................................................ 122

20.2. Power-Fail Reset / VDD Monitor ................................................................... 122

20.3. External Reset............................................................................................... 124

20.4. Missing Clock Detector Reset ....................................................................... 124

20.5. Comparator0 Reset....................................................................................... 124

20.6. PCA Watchdog Timer Reset ......................................................................... 125

20.7. EPROM Error Reset...................................................................................... 125

20.8. Software Reset.............................................................................................. 125

20.9. USB Reset..................................................................................................... 125

21. Oscillators and Clock Selection......................................................................... 127

21.1. System Clock Selection................................................................................. 128

21.2. USB Clock Selection ..................................................................................... 128

21.3. Programmable Internal High-Frequency (H-F) Oscillator.............................. 130

21.3.1. Internal Oscillator Suspend Mode......................................................... 130

21.4. Clock Multiplier.............................................................................................. 132

21.5. Programmable Internal Low-Frequency (L-F) Oscillator ............................... 133

21.5.1. Calibrating the Internal L-F Oscillator.................................................... 133

Rev. 1.2 5

C8051T620/1/6/7 & C8051T320/1/2/3

21.6. External Oscillator Drive Circuit..................................................................... 134

21.6.1. External Crystal Mode........................................................................... 134

21.6.2. External RC Example............................................................................ 136

21.6.3. External Capacitor Example.................................................................. 136

22. Port Input/Output................................................................................................. 138

22.1. Port I/O Modes of Operation.......................................................................... 139

22.1.1. Port Pins Configured for Analog I/O...................................................... 139

22.1.2. Port Pins Configured For Digital I/O...................................................... 139

22.1.3. Interfacing Port I/O to 5 V Logic............................................................ 140

22.2. Assigning Port I/O Pins to Analog and Digital Functions............................... 140

22.2.1. Assigning Port I/O Pins to Analog Functions ........................................ 140

22.2.2. Assigning Port I/O Pins to Digital Functions.......................................... 140

22.2.3. Assigning Port I/O Pins to External Digital Event Capture Functions ... 141

22.3. Priority Crossbar Decoder............................................................................. 142

22.4. Port I/O Initialization ...................................................................................... 146

22.5. Port Match..................................................................................................... 149

22.6. Special Function Registers for Accessing and Configuring Port I/O ............. 152

23. Universal Serial Bus Controller (USB0)............................................................. 160

23.1. Endpoint Addressing ..................................................................................... 161

23.2. USB Transceiver ........................................................................................... 161

23.3. USB Register Access.................................................................................... 163

23.4. USB Clock Configuration............................................................................... 168

23.5. FIFO Management ........................................................................................ 169

23.5.1. FIFO Split Mode.................................................................................... 170

23.5.2. FIFO Double Buffering.......................................................................... 170

23.5.1. FIFO Access ......................................................................................... 171

23.6. Function Addressing...................................................................................... 172

23.7. Function Configuration and Control............................................................... 173

23.8. Interrupts ....................................................................................................... 176

23.9. The Serial Interface Engine........................................................................... 181

23.10. Endpoint0 .................................................................................................... 181

23.10.1. Endpoint0 SETUP Transactions ......................................................... 182

23.10.2. Endpoint0 IN Transactions.................................................................. 182

23.10.3. Endpoint0 OUT Transactions.............................................................. 183

23.11. Configuring Endpoints1-3............................................................................ 185

23.12. Controlling Endpoints1-3 IN......................................................................... 186

23.12.1. Endpoints1-3 IN Interrupt or Bulk Mode.............................................. 186

23.12.2. Endpoints1-3 IN Isochronous Mode.................................................... 187

23.13. Controlling Endpoints1-3 OUT..................................................................... 189

23.13.1. Endpoints1-3 OUT Interrupt or Bulk Mode.......................................... 190

23.13.2. Endpoints1-3 OUT Isochronous Mode................................................ 190

24. SMBus................................................................................................................... 194

24.1. Supporting Documents.................................................................................. 195

24.2. SMBus Configuration..................................................................................... 195

24.3. SMBus Operation.......................................................................................... 195

C8051T620/1/6/7 & C8051T320/1/2/3

6 Rev. 1.2

24.3.1. Transmitter Vs. Receiver....................................................................... 196

24.3.2. Arbitration.............................................................................................. 196

24.3.3. Clock Low Extension............................................................................. 196

24.3.4. SCL Low Timeout.................................................................................. 196

24.3.5. SCL High (SMBus Free) Timeout ......................................................... 197

24.4. Using the SMBus........................................................................................... 197

24.4.1. SMBus Configuration Register.............................................................. 197

24.4.2. SMB0CN Control Register.................................................................... 201

24.4.2.1. Software ACK Generation ............................................................ 201

24.4.2.2. Hardware ACK Generation........................................................... 201

24.4.3. Hardware Slave Address Recognition .................................................. 203

24.4.4. Data Register........................................................................................ 206

24.5. SMBus Transfer Modes................................................................................. 207

24.5.1. Write Sequence (Master)...................................................................... 207

24.5.2. Read Sequence (Master)...................................................................... 208

24.5.3. Write Sequence (Slave)........................................................................ 209

24.5.4. Read Sequence (Slave)........................................................................ 210

24.6. SMBus Status Decoding................................................................................ 210

25. UART0................................................................................................................... 215

25.1. Enhanced Baud Rate Generation.................................................................. 216

25.2. Operational Modes........................................................................................ 217

25.2.1. 8-Bit UART............................................................................................ 217

25.2.2. 9-Bit UART............................................................................................ 218

25.3. Multiprocessor Communications ................................................................... 219

26. UART1................................................................................................................... 223

26.1. Baud Rate Generator .................................................................................... 223

26.2. Data Format................................................................................................... 225

26.3. Configuration and Operation ......................................................................... 226

26.3.1. Data Transmission................................................................................ 226

26.3.2. Data Reception ..................................................................................... 226

26.3.3. Multiprocessor Communications........................................................... 227

27. Enhanced Serial Peripheral Interface (SPI0)..................................................... 233

27.1. Signal Descriptions........................................................................................ 234

27.1.1. Master Out, Slave In (MOSI)................................................................. 234

27.1.2. Master In, Slave Out (MISO)................................................................. 234

27.1.3. Serial Clock (SCK)................................................................................ 234

27.1.4. Slave Select (NSS)............................................................................... 234

27.2. SPI0 Master Mode Operation........................................................................ 235

27.3. SPI0 Slave Mode Operation.......................................................................... 236

27.4. SPI0 Interrupt Sources.................................................................................. 237

27.5. Serial Clock Phase and Polarity.................................................................... 237

27.6. SPI Special Function Registers..................................................................... 239

Rev. 1.2 7

C8051T620/1/6/7 & C8051T320/1/2/3

28. Timers................................................................................................................... 246

28.1. Timer 0 and Timer 1...................................................................................... 248

28.1.1. Mode 0: 13-bit Counter/Timer............................................................... 248

28.1.2. Mode 1: 16-bit Counter/Timer............................................................... 249

28.1.3. Mode 2: 8-bit Counter/Timer with Auto-Reload..................................... 249

28.1.4. Mode 3: Two 8-bit Counter/Timers (Timer 0 Only)................................ 250

28.2. Timer 2 .......................................................................................................... 256

28.2.1. 16-bit Timer with Auto-Reload............................................................... 256

28.2.2. 8-bit Timers with Auto-Reload............................................................... 257

28.2.3. Low-Frequency Oscillator (LFO) Capture Mode................................... 258

28.3. Timer 3 .......................................................................................................... 262

28.3.1. 16-bit Timer with Auto-Reload............................................................... 262

28.3.2. 8-bit Timers with Auto-Reload............................................................... 263

28.3.3. Low-Frequency Oscillator (LFO) Capture Mode................................... 264

29. Programmable Counter Array............................................................................. 268

29.1. PCA Counter/Timer....................................................................................... 269

29.2. PCA0 Interrupt Sources................................................................................. 270

29.3. Capture/Compare Modules ........................................................................... 271

29.3.1. Edge-triggered Capture Mode............................................................... 272

29.3.2. Software Timer (Compare) Mode.......................................................... 273

29.3.3. High-Speed Output Mode ..................................................................... 274

29.3.4. Frequency Output Mode ....................................................................... 275

29.3.5. 8-bit, 9-bit, 10-bit and 11-bit Pulse Width Modulator Modes................. 276

29.3.5.1. 8-bit Pulse Width Modulator Mode................................................ 276

29.3.5.2. 9/10/11-bit Pulse Width Modulator Mode...................................... 277

29.3.6. 16-Bit Pulse Width Modulator Mode...................................................... 278

29.4. Watchdog Timer Mode.................................................................................. 279

29.4.1. Watchdog Timer Operation................................................................... 279

29.4.2. Watchdog Timer Usage ........................................................................ 280

29.5. Register Descriptions for PCA0..................................................................... 281

30. C2 Interface .......................................................................................................... 288

30.1. C2 Interface Registers................................................................................... 288

30.2. C2 Pin Sharing .............................................................................................. 295

Document Change List.............................................................................................. 296

Contact Information................................................................................................... 298

C8051T620/1/6/7 & C8051T320/1/2/3

8 Rev. 1.2

List of Figures

Figure 1.1. C8051T620/1 Block Diagram ................................................................ 16

Figure 1.2. C8051T626/7 Block Diagram ................................................................ 17

Figure 1.3. C8051T320/2 Block Diagram ................................................................ 18

Figure 1.4. C8051T321/3 Block Diagram ................................................................ 19

Figure 1.5. Typical Bus-Powered Connections ....................................................... 20

Figure 3.1. QFN-32 Pinout Diagram (Top View) ..................................................... 25

Figure 3.2. LQFP-32 Pinout Diagram (Top View) .................................................... 26

Figure 3.3. QFN-28 Pinout Diagram (Top View) ..................................................... 27

Figure 4.1. LQFP-32 Package Drawing ................................................................... 28

Figure 4.2. LQFP-32 Recommended PCB Land Pattern ........................................ 29

Figure 5.1. QFN-32 Package Drawing .................................................................... 30

Figure 5.2. QFN-32 Recommended PCB Land Pattern .......................................... 31

Figure 6.1. QFN-28 Package Drawing .................................................................... 32

Figure 6.2. QFN-28 Recommended PCB Land Pattern .......................................... 33

Figure 7.1. Normal Mode Digital Supply Current vs. Frequency (MPCE = 1) ......... 44

Figure 7.2. Idle Mode Digital Supply Current vs. Frequency (MPCE = 1) ............... 44

Figure 8.1. ADC0 Functional Block Diagram ........................................................... 45

Figure 8.2. 10-Bit ADC Track and Conversion Example Timing ............................. 47

Figure 8.3. ADC0 Equivalent Input Circuits ............................................................. 48

Figure 8.4. ADC Window Compare Example: Right-Justified Data ......................... 54

Figure 8.5. ADC Window Compare Example: Left-Justified Data ........................... 54

Figure 8.6. ADC0 Multiplexer Block Diagram .......................................................... 55

Figure 9.1. Temperature Sensor Transfer Function ................................................ 57

Figure 9.2. TOFFH and TOFFL Calibration Value Orientation ................................ 58

Figure 9.3. Temperature Sensor Error with 1-Point Calibration at 0 Celsius ........... 58

Figure 10.1. Voltage Reference Functional Block Diagram ..................................... 59

Figure 11.1. REG0 Configuration: USB Bus-Powered ............................................ 61

Figure 11.2. REG0 Configuration: USB Self-Powered ............................................ 62

Figure 11.3. REG0 Configuration: USB Self-Powered, Regulator Disabled ............ 62

Figure 11.4. REG0 Configuration: No USB Connection .......................................... 63

Figure 12.1. CIP-51 Block Diagram ......................................................................... 66

Figure 14.1. Comparator0 Functional Block Diagram ............................................. 77

Figure 14.2. Comparator1 Functional Block Diagram ............................................. 78

Figure 14.3. Comparator Hysteresis Plot ................................................................ 79

Figure 14.4. Comparator Input Multiplexer Block Diagram ...................................... 84

Figure 15.1. C8051T620/1 and C8051T320/1/2/3 Memory Map ............................. 87

Figure 15.2. C8051T626/7 Memory Map ................................................................. 88

Figure 15.3. Program Memory Map ......................................................................... 89

Figure 15.4. C8051T620/1 and C8051T320/1/2/3 USB FIFO Space and 

XRAM Memory Map with USBFAE Set to 1 ....................................................... 92

Figure 15.5. C8051T626/7 USB FIFO Space and XRAM Memory Map 

with USBFAE set to 1 ......................................................................................... 93

Figure 20.1. Reset Sources ................................................................................... 121

Rev. 1.2 9

C8051T620/1/6/7 & C8051T320/1/2/3

Figure 20.2. Power-On and VDD Monitor Reset Timing ....................................... 122

Figure 21.1. Oscillator Options .............................................................................. 127

Figure 21.2. External Crystal Example .................................................................. 135

Figure 22.1. Port I/O Functional Block Diagram .................................................... 138

Figure 22.2. Port I/O Cell Block Diagram .............................................................. 139

Figure 22.3. Priority Crossbar Decoder Potential Pin Assignments ...................... 143

Figure 22.4. Priority Crossbar Decoder Example 1—No Skipped Pins ................. 144

Figure 22.5. Priority Crossbar Decoder Example 2—Skipping Pins ...................... 145

Figure 23.1. USB0 Block Diagram ......................................................................... 160

Figure 23.2. USB0 Register Access Scheme ........................................................ 163

Figure 23.3. C8051T620/1 and C8051T320/1/2/3 USB FIFO Allocation ............... 169

Figure 23.4. C8051T626/7 USB FIFO Allocation .................................................. 170

Figure 24.1. SMBus Block Diagram ...................................................................... 194

Figure 24.2. Typical SMBus Configuration ............................................................ 195

Figure 24.3. SMBus Transaction ........................................................................... 196

Figure 24.4. Typical SMBus SCL Generation ........................................................ 198

Figure 24.5. Typical Master Write Sequence ........................................................ 207

Figure 24.6. Typical Master Read Sequence ........................................................ 208

Figure 24.7. Typical Slave Write Sequence .......................................................... 209

Figure 24.8. Typical Slave Read Sequence .......................................................... 210

Figure 25.1. UART0 Block Diagram ...................................................................... 215

Figure 25.2. UART0 Baud Rate Logic ................................................................... 216

Figure 25.3. UART Interconnect Diagram ............................................................. 217

Figure 25.4. 8-Bit UART Timing Diagram .............................................................. 217

Figure 25.5. 9-Bit UART Timing Diagram .............................................................. 218

Figure 25.6. UART Multi-Processor Mode Interconnect Diagram ......................... 219

Figure 26.1. UART1 Block Diagram ...................................................................... 223

Figure 26.2. UART1 Timing Without Parity or Extra Bit ......................................... 225

Figure 26.3. UART1 Timing With Parity ................................................................ 225

Figure 26.4. UART1 Timing With Extra Bit ............................................................ 225

Figure 26.5. Typical UART Interconnect Diagram ................................................. 226

Figure 26.6. UART Multi-Processor Mode Interconnect Diagram ......................... 227

Figure 27.1. SPI Block Diagram ............................................................................ 233

Figure 27.2. Multiple-Master Mode Connection Diagram ...................................... 235

Figure 27.3. 3-Wire Single Master and 3-Wire Single Slave Mode 

Connection Diagram ........................................................................................ 235

Figure 27.4. 4-Wire Single Master Mode and 4-Wire Slave Mode 

Connection Diagram ........................................................................................ 236

Figure 27.5. Master Mode Data/Clock Timing ....................................................... 238

Figure 27.6. Slave Mode Data/Clock Timing (CKPHA = 0) ................................... 238

Figure 27.7. Slave Mode Data/Clock Timing (CKPHA = 1) ................................... 239

Figure 27.8. SPI Master Timing (CKPHA = 0) ....................................................... 243

Figure 27.9. SPI Master Timing (CKPHA = 1) ....................................................... 243

Figure 27.10. SPI Slave Timing (CKPHA = 0) ....................................................... 244

C8051T620/1/6/7 & C8051T320/1/2/3

10 Rev. 1.2

Figure 27.11. SPI Slave Timing (CKPHA = 1) ....................................................... 244

Figure 28.1. T0 Mode 0 Block Diagram ................................................................. 249

Figure 28.2. T0 Mode 2 Block Diagram ................................................................. 250

Figure 28.3. T0 Mode 3 Block Diagram ................................................................. 251

Figure 28.4. Timer 2 16-Bit Mode Block Diagram ................................................. 256

Figure 28.5. Timer 2 8-Bit Mode Block Diagram ................................................... 257

Figure 28.6. Timer 2 Low-Frequency Oscillation Capture Mode Block Diagram ... 258

Figure 28.7. Timer 3 16-Bit Mode Block Diagram ................................................. 262

Figure 28.8. Timer 3 8-Bit Mode Block Diagram ................................................... 263

Figure 28.9. Timer 3 Low-Frequency Oscillation Capture Mode Block Diagram ... 264

Figure 29.1. PCA Block Diagram ........................................................................... 268

Figure 29.2. PCA Counter/Timer Block Diagram ................................................... 270

Figure 29.3. PCA Interrupt Block Diagram ............................................................ 271

Figure 29.4. PCA Capture Mode Diagram ............................................................. 273

Figure 29.5. PCA Software Timer Mode Diagram ................................................. 274

Figure 29.6. PCA High-Speed Output Mode Diagram ........................................... 275

Figure 29.7. PCA Frequency Output Mode ........................................................... 276

Figure 29.8. PCA 8-Bit PWM Mode Diagram ........................................................ 277

Figure 29.9. PCA 9, 10 and 11-Bit PWM Mode Diagram ...................................... 278

Figure 29.10. PCA 16-Bit PWM Mode ................................................................... 279

Figure 29.11. PCA Module 2 with Watchdog Timer Enabled ................................ 280

Figure 30.1. Typical C2 Pin Sharing ...................................................................... 295

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