Silicon Laboratories Si8410 Bedienungsanleitung

Si8410/20/21

ISOPRO LOW-POWER SINGLE AND DUAL-CHANNEL

DIGITAL ISOLATORS

Features

Applications

Safety Regulatory Approvals

Description

Silicon Lab's family of ultra-low-power digital isolators are CMOS devices

offering substantial data rate, propagation delay, power, size, reliability,

and external BOM advantages when compared to legacy isolation

technologies. The operating parameters of these products remain stable

across wide temperature ranges throughout their service life. For ease of

design, only VDD bypass capacitors are required.

Data rates up to 150 Mbps are supported, and all devices achieve worst-

case propagation delays of less than 10 ns. All products are safety

certified by UL, CSA, and VDE and support withstand voltages of up to

2.5 kVrms. These devices are available in an 8-pin narrow-body SOIC

package.

High-speed operation

DC to 150 Mbps

No start-up initialization required

Wide Operating Supply Voltage:

2.70–5.5 V

Ultra low power (typical)

5 V Operation:

< 2.1 mA per channel at 1 Mbps

< 6 mA per channel at 100 Mbps

2.70 V Operation:

< 1.8 mA per channel at 1 Mbps

< 4 mA per channel at 100 Mbps

High electromagnetic immunity

Up to 2500 VRMS isolation

60-year life at rated working

voltage

Precise timing (typical)

<10 ns worst case

1.5 ns pulse width distortion

0.5 ns channel-channel skew

2 ns propagation delay skew

6 ns minimum pulse width

Transient Immunity 25 kV/µs

Wide temperature range

–40 to 125 °C at 150 Mbps

RoHS-compliant packages

SOIC-8 narrow body

Industrial automation systems

Hybrid electric vehicles

Isolated switch mode supplies

Isolated ADC, DAC

Motor control

Power inverters

Communications systems

UL 1577 recognized

Up to 2500 VRMS for 1 minute

CSA component notice 5A

approval

IEC 60950-1, 61010-1

(reinforced insulation)

VDE certification conformity

IEC 60747-5-2

(VDE0884 Part 2)

Ordering Information:

See page 25.

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Si8410/20/21

2 Rev. 1.3

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Si8410/20/21

Rev. 1.3 3

TABLE OF CONTENTS

Section Page

1. Electrical Specifications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .4

2. Functional Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .17

2.1. Theory of Operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .17

2.2. Eye Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .18

2.3. Device Operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .19

2.4. Layout Recommendations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .20

2.5. Typical Performance Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .21

3. Errata and Design Migration Guidelines . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .23

3.1. Power Supply Bypass Capacitors (Revision C and Revision D) . . . . . . . . . . . . . . . .23

3.2. Latch Up Immunity (Revision C Only) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .23

4. Pin Descriptions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .24

5. Ordering Guide . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .25

6. Package Outline: 8-Pin Narrow Body SOIC . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .26

7. Land Pattern: 8-Pin Narrow Body SOIC . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .27

8. Top Marking . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .28

Document Change List . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .29

Contact Information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .30

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Si8410/20/21

4 Rev. 1.3

1. Electrical Specifications

Table 1. Recommended Operating Conditions

Parameter Symbol Test Condition Min Typ Max Unit

Ambient Operating Temperature* TA150 Mbps, 15 pF, 5 V –40 25 125 C°

Supply Voltage VDD1 2.70 — 5.5 V

VDD2 2.70 — 5.5 V

*Note: The maximum ambient temperature is dependent upon data frequency, output loading, the number of operating

channels, and supply voltage.

Table 2. Absolute Maximum Ratings1

Parameter Symbol Min Typ Max Unit

Storage Temperature2TSTG –65 — 150 C°

Operating Temperature TA–40 — 125 C°

Supply Voltage (Revision C)3VDD1, VDD2 –0.5 — 5.75 V

Supply Voltage (Revision D)3VDD1, VDD2 –0.5 — 6.0 V

Input Voltage VI–0.5 — VDD + 0.5 V

Output Voltage VO–0.5 — VDD + 0.5 V

Output Current Drive Channel IO——10mA

Lead Solder Temperature (10 s) — — 260 C°

Maximum Isolation Voltage (1 s) — — 3600 VRMS

Notes:

1. Permanent device damage may occur if the absolute maximum ratings are exceeded. Functional operation should be

restricted to conditions as specified in the operational sections of this data sheet.

2. VDE certifies storage temperature from –40 to 150 °C.

3. See "5. Ordering Guide" on page 25 for more information.

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Si8410/20/21

Rev. 1.3 5

Table 3. Electrical Characteristics

(VDD1 = 5 V ±10%, VDD2 = 5 V ±10%, TA=–40to125ºC)

Parameter Symbol Test Condition Min Typ Max Unit

High Level Input Voltage VIH 2.0 — — V

Low Level Input Voltage VIL ——0.8V

High Level Output Voltage VOH loh = –4 mA VDD1,VDD2 –0.4 4.8 — V

Low Level Output Voltage VOL lol = 4 mA — 0.2 0.4 V

Input Leakage Current IL——±10µA

Output Impedance1ZO—85—

DC Supply Current (All inputs 0 V or at Supply)

Si8410Ax, Bx

VDD1

VDD2

VDD1

VDD2

All inputs 0 DC

All inputs 1 DC

—

0.8

1.8

0.8

1.2

2.7

1.2

Si8420Ax, Bx

VDD1

VDD2

VDD1

VDD2

All inputs 0 DC

All inputs 1 DC

—

1.0

1.3

3.0

1.4

1.5

2.0

4.5

2.1

Si8421Ax, Bx

VDD1

VDD2

VDD1

VDD2

All inputs 0 DC

All inputs 1 DC

—

1.3

2.3

2.0

3.5

1 Mbps Supply Current (All inputs = 500 kHz square wave, CI = 15 pF on all outputs)

Si8410Ax, Bx

VDD1

VDD2

—

—1.3

0.9 2.0

1.4 mA

Si8420Ax, Bx

VDD1

VDD2

—

—2.0

1.6 3.0

2.4 mA

Si8421Ax, Bx

VDD1

VDD2

—

—1.9

1.9 2.9

2.9 mA

Notes:

1. The nominal output impedance of an isolator driver channel is approximately 85 , ±40%, which is a combination of

the value of the on-chip series termination resistor and channel resistance of the output driver FET. When driving loads

where transmission line effects will be a factor, output pins should be appropriately terminated with controlled

impedance PCB traces.

2. tPSK(P-P) is the magnitude of the difference in propagation delay times measured between different units operating at

the same supply voltages, load, and ambient temperature.

3. Start-up time is the time period from the application of power to valid data at the output.

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Si8410/20/21

6 Rev. 1.3

10 Mbps Supply Current (All inputs = 5 MHz square wave, CI = 15 pF on all outputs)

Si8410Bx

VDD1

VDD2

—

—1.3

1.2 2.0

1.8 mA

Si8420Bx

VDD1

VDD2

—

—2.0

2.1 3.0

3.2 mA

Si8421Bx

VDD1

VDD2

—

—2.2

2.2 3.3

3.3 mA

100 Mbps Supply Current (All inputs = 50 MHz square wave, CI = 15 pF on all outputs)

Si8410Bx

VDD1

VDD2

—

—1.4

4.6 2.1

5.8 mA

Si8420Bx

VDD1

VDD2

—

—2.2

9.2 3.3

11.5 mA

Si8421Bx

VDD1

VDD2

—

—5.8

5.8 7.3

7.3 mA

Timing Characteristics

Si8410Ax, Si8420Ax, Si8421Ax

Maximum Data Rate 0 — 1.0 Mbps

Minimum Pulse Width — — 250 ns

Propagation Delay tPHL, tPLH See Figure 1 — — 35 ns

Pulse Width Distortion

|tPLH -tPHL|PWD See Figure 1 — — 25 ns

Propagation Delay Skew2tPSK(P-P) — — 40 ns

Channel-Channel Skew tPSK — — 35 ns

Table 3. Electrical Characteristics (Continued)

(VDD1 = 5 V ±10%, VDD2 = 5 V ±10%, TA=–40to125ºC)

Parameter Symbol Test Condition Min Typ Max Unit

Notes:

1. The nominal output impedance of an isolator driver channel is approximately 85 , ±40%, which is a combination of

the value of the on-chip series termination resistor and channel resistance of the output driver FET. When driving loads

where transmission line effects will be a factor, output pins should be appropriately terminated with controlled

impedance PCB traces.

2. tPSK(P-P) is the magnitude of the difference in propagation delay times measured between different units operating at

the same supply voltages, load, and ambient temperature.

3. Start-up time is the time period from the application of power to valid data at the output.

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Si8410/20/21

Rev. 1.3 7

Figure 1. Propagation Delay Timing

Si8410Bx, Si8420Bx, Si8421Bx

Maximum Data Rate 0 — 150 Mbps

Minimum Pulse Width — — 6.0 ns

Propagation Delay tPHL, tPLH See Figure 1 3.0 6.0 9.5 ns

Pulse Width Distortion

|tPLH -tPHL|PWD See Figure 1 — 1.5 2.5 ns

Propagation Delay Skew2tPSK(P-P) —2.03.0ns

Channel-Channel Skew tPSK —0.51.8ns

All Models

Output Rise Time trCL= 15 pF — 3.8 5.0 ns

Output Fall Time tfCL= 15 pF — 2.8 3.7 ns

Common Mode Transient

Immunity CMTI VI=V

DD or 0 V — 25 — kV/µs

Start-up Time3tSU —1540µs

Table 3. Electrical Characteristics (Continued)

(VDD1 = 5 V ±10%, VDD2 = 5 V ±10%, TA=–40to125ºC)

Parameter Symbol Test Condition Min Typ Max Unit

Notes:

1. The nominal output impedance of an isolator driver channel is approximately 85 , ±40%, which is a combination of

the value of the on-chip series termination resistor and channel resistance of the output driver FET. When driving loads

where transmission line effects will be a factor, output pins should be appropriately terminated with controlled

impedance PCB traces.

2. tPSK(P-P) is the magnitude of the difference in propagation delay times measured between different units operating at

the same supply voltages, load, and ambient temperature.

3. Start-up time is the time period from the application of power to valid data at the output.

Typical

Input tPLH tPHL

Typical

Output trtf

90%

10%

90%

10%

1.4 V

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Si8410/20/21

8 Rev. 1.3

Table 4. Electrical Characteristics

(VDD1 = 3.3 V ±10%, VDD2 = 3.3 V ±10%, TA= –40 to 125 °C)

Parameter Symbol Test Condition Min Typ Max Unit

High Level Input Voltage VIH 2.0 — — V

Low Level Input Voltage VIL ——0.8V

High Level Output Voltage VOH loh = –4 mA VDD1,VDD2 –0.4 3.1 — V

Low Level Output Voltage VOL lol = 4 mA — 0.2 0.4 V

Input Leakage Current IL——±10µA

Output Impedance1ZO—85—

DC Supply Current (All inputs 0 V or at supply)

Si8410Ax, Bx

VDD1

VDD2

VDD1

VDD2

All inputs 0 DC

All inputs 1 DC

—

0.8

1.8

0.8

1.2

2.7

1.2

Si8420Ax, Bx

VDD1

VDD2

VDD1

VDD2

All inputs 0 DC

All inputs 1 DC

—

1.0

1.3

3.0

1.4

1.5

2.0

4.5

2.1

Si8421Ax, Bx

VDD1

VDD2

VDD1

VDD2

All inputs 0 DC

All inputs 1 DC

—

1.3

2.3

2.0

3.5

1 Mbps Supply Current (All inputs = 500 kHz square wave, CI = 15 pF on all outputs)

Si8410Ax, Bx

VDD1

VDD2

—

—1.3

0.9 2.0

1.4 mA

Si8420Ax, Bx

VDD1

VDD2

—

—2.0

1.6 3.0

2.4 mA

Si8421Ax, Bx

VDD1

VDD2

—

—1.9

1.9 2.9

2.9 mA

Notes:

1. The nominal output impedance of an isolator driver channel is approximately 85 , ±40%, which is a combination of the

value of the on-chip series termination resistor and channel resistance of the output driver FET. When driving loads

where transmission line effects will be a factor, output pins should be appropriately terminated with controlled

impedance PCB traces.

2. tPSK(P-P) is the magnitude of the difference in propagation delay times measured between different units operating at

the same supply voltages, load, and ambient temperature.

3. Start-up time is the time period from the application of power to valid data at the output.

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Si8410/20/21

Rev. 1.3 9

10 Mbps Supply Current (All inputs = 5 MHz square wave, CI = 15 pF on all outputs)

Si8410Bx

VDD1

VDD2

—

—1.3

1.2 2.0

1.8 mA

Si8420Bx

VDD1

VDD2

—

—2.0

2.1 3.0

3.2 mA

Si8421Bx

VDD1

VDD2

—

—2.2

2.2 3.3

3.3 mA

100 Mbps Supply Current (All inputs = 50 MHz square wave, CI = 15 pF on all outputs)

Si8410Bx

VDD1

VDD2

—

—1.3

3.3 2.0

4.9 mA

Si8420Bx

VDD1

VDD2

—

—2.0

6.5 3.0

8.1 mA

Si8421Bx

VDD1

VDD2

—

—4.4

4.4 5.5

5.5 mA

Timing Characteristics

Si8410Ax, Si8420Ax, Si8421Ax

Maximum Data Rate 0—1.0Mbps

Minimum Pulse Width ——250ns

Propagation Delay tPHL, tPLH See Figure 1 — — 35 ns

Pulse Width Distortion

|tPLH – tPHL|PWD See Figure 1 — — 25 ns

Propagation Delay Skew2tPSK(P-P) — — 40 ns

Channel-Channel Skew tPSK — — 35 ns

Table 4. Electrical Characteristics (Continued)

(VDD1 = 3.3 V ±10%, VDD2 = 3.3 V ±10%, TA= –40 to 125 °C)

Parameter Symbol Test Condition Min Typ Max Unit

Notes:

1. The nominal output impedance of an isolator driver channel is approximately 85 , ±40%, which is a combination of the

value of the on-chip series termination resistor and channel resistance of the output driver FET. When driving loads

where transmission line effects will be a factor, output pins should be appropriately terminated with controlled

impedance PCB traces.

2. tPSK(P-P) is the magnitude of the difference in propagation delay times measured between different units operating at

the same supply voltages, load, and ambient temperature.

3. Start-up time is the time period from the application of power to valid data at the output.

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Si8410/20/21

10 Rev. 1.3

Si8410Bx, Si8420Bx, Si8421Bx

Maximum Data Rate 0—150Mbps

Minimum Pulse Width ——6.0ns

Propagation Delay tPHL, tPLH See Figure 1 3.0 6.0 9.5 ns

Pulse Width Distortion

|tPLH – tPHL|PWD See Figure 1 — 1.5 2.5 ns

Propagation Delay Skew2tPSK(P-P) —2.03.0ns

Channel-Channel Skew tPSK —0.51.8ns

All Models

Output Rise Time trCL= 15 pF — 4.3 6.1 ns

Output Fall Time tfCL= 15 pF — 3.0 4.3 ns

Common Mode Transient

Immunity CMTI VI=V

DD or 0 V — 25 — kV/µs

Start-up Time3tSU —1540µs

Table 4. Electrical Characteristics (Continued)

(VDD1 = 3.3 V ±10%, VDD2 = 3.3 V ±10%, TA= –40 to 125 °C)

Parameter Symbol Test Condition Min Typ Max Unit

Notes:

1. The nominal output impedance of an isolator driver channel is approximately 85 , ±40%, which is a combination of the

value of the on-chip series termination resistor and channel resistance of the output driver FET. When driving loads

where transmission line effects will be a factor, output pins should be appropriately terminated with controlled

impedance PCB traces.

2. tPSK(P-P) is the magnitude of the difference in propagation delay times measured between different units operating at

the same supply voltages, load, and ambient temperature.

3. Start-up time is the time period from the application of power to valid data at the output.

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