Sino Wealth SH79F6441 Bedienungsanleitung

SH79F6441

Enhanced 8051 Microcontroller

1 V2.3

1. Features

8bits micro-controller with Pipe-line structured 8051

compatible instruction set

Flash ROM:64K Bytes

RAM:Internal 256 Bytes, external 2816 Bytes

EEPROM-Like:bulid-in 4096 Bytes(code option)

Operation Voltage:

- fOSC = 32.768kHz - 24MHz, VDD = 2.7V - 5.5V

Oscillator (code option):

- Crystal oscillator: 32.768kHz

- Crystal oscillator: 2MHz - 16MHz

- Ceramic oscillator: 2MHz - 16MHz

- Internal RC oscillator: 24MHz (±1%)/128K (±10%)

42/30/26 CMOS bi-directional I/O pins (44 pins/32

pins/28 pins)

Built-in pull-up resistor for input pin (30kΩ)

12 large current driver I/O (code option optional

enhanced or standardized or weakened)

P0 port can reduce the pull current capacity (code option

optional weakened or standardized)

One16-bit timer/counters T3

Three 16-bit PCA0, PCA1 and PCA2 each contain two

comparison/capture units

3 channels 12-bits PWM timer

Interrupt sources:

- Timer3, PCA0-2

- INT0-3

- INT4: 8 input

- ADC, EUART, SPI

- PWM, SCM, CRC, TWI, LPD

SPI (Master/Slave Mode)

TWI (Master/Slave Mode)

Internal Logic Configuration Module(LCM)

3 enhanced UART (3V/5V communication) (own

baudrate generator)

15 analog inputs 12-bit Analog Digital Converter

Built-in low voltage Reset (LVR) function (code option)

- LVR voltage1: 4.1V

- LVR voltage2: 3.7V

- LVR voltage3: 2.8V

Built-in CRC verification module, the verify size can be

selected

Low Power Detect (LPD) Module with 13 level optional

Support single line simulation and download

CPU Machine period: 1 oscillator clock

Built-in Watch Dog Timer (WDT)

Built-in oscillator Warm-up timer

Support Low power operation modes:

- Idle Mode

- Power-Down Mode

Flash Type

Package:

- LQFP44

- LQFP32

- QFN32

- SOP28

2. General Description

The SH79F6441 is high performance 8051 compatible micro-controller. The SH79F6441 can perform more fast operation

speed and higher calculation performance, if compare SH79F6441 with standard 8051 at same clock speed.

The SH79F6441 retains most features of the standard 8051. These features include internal 256 bytes RAM, Three UART and

INT0, INT1, INT2, INT3, INT4. In addition, SH79F6441 provides external 2816 bytes RAM. It also contains 64K bytes Flash

memory block for program storage.

The SH79F6441 not only include many standard communication modules, such as EUART, TWI, SPI and so on, but also

include 12bit ADC, PWM timer, ect.

In addition, the SH79F6441 also have CRC module, Logic configurable module (LCM) built in it.

For high reliability and low cost issues, the SH79F6441 builds in Watchdog Timer, Low Voltage Reset function and system clock

monitor. And SH79F6441 also supports two power saving modes to reduce power consumption.

SH79F6441

3. Block Diagram

64K Bytes

Flash ROM

Internal 256 Bytes

External 2816Bytes

(Exclude System

Oscillator

Pipelined 8051 architecture

Timer3 (16bit)

Reset circuit RST

XTAL2

XTAL1

External Interrupt

LPD

Power

Watch Dog

oscillator fail

detector

12-bit PWM0/1/2

Internal

Oscillator

Port 3

Configuration I/Os

Port 4

Configuration I/Os

P1.0 - P1.7

P2.0 - P2.7

P0.0 - P0.7

Port 2

Configuration I/Os

P3.0 - P3.7

EUART0/1/2

TWI

Jtag ports

(for debug)

Port 5

Configuration I/Os

Port 1

Configuration I/Os

P4.0 - P4.7

Port 0

Configuration I/Os

P5.0 - P5.1

SPI

SCM

CRC

PCA0

PCA1

PCA2

12-bit ADC

SH79F6441

4. Pin Configration

4.1 LQFP44 Package

1 2 3 4 5 6 7 8 9 10 11

25 24 2332 31 30 29 28 27 2633

P4.7

T3/AVREF/AN8/P1.6

AN11/P3.6

AN12/P3.7

AN13/P5.0

P5.1

RST/P1.7

XTAL2/P3.3

XTAL1/P3.4

VDD

VSS

P4.0

P4.1

P4.2

P4.3

P3.2/P1CEX0

P3.1/INT0/ECI1

P3.0/AN9/SS

P3.5/AN10

P2.0/SCK/P1CEX1

P2.1/MISO/TXD2

P2.2/MOSI/RXD2

P2.3/VIN

P2.4

P2.5/PWM2

P2.6/INT45

P2.7/INT46/P2CEX1

P4.4

P4.5

P4.6

P0.7/INT1/P2CEX0

P0.6/ECI2

P0.5/AN3

TCK/AN7/INT40/P1.5

TDI/AN6/INT41/P1.4

TMS/AN5/INT42/P1.3

SWE/TDO/AN4/INT43/P1.2

INT44/P1.1

INT47/P1.0

P0.0

INT3/P0.1

AN0/P0.2

AN1/P0.3

AN2/P0.4

SH79F6441

Note:

In pin designation, the pin function written on the outermost side has the highest priority and the innermost pin function has the

lowest priority (see the pin configuration diagram). When a pin is occupied by a high-priority function, it cannot be used as a pin

of a low-priority function even if the low-priority function is enabled. Only when the software disables the high-priority function of

the pin can the corresponding pin be released as a low-priority port.

SH79F6441

4.2 LQFP32 Package

P3.1/INT0/ECI1

TCK/AN7/INT40/P1.5

SH79F6441

P2.5/PWM2

P0.6/ECI2

P0.7/INT1/P2CEX0

P2.7/INT46/P2CEX1

P2.6/INT45

P0.5/AN3

P0.4/AN2

P0.3/AN1

AN0/P0.2

INT3/P0.1

P0.0

INT47/P1.0

INT44/P1.1

SWE/TDO/AN4/INT43/P1.2

TMS/AN5/INT42/P1.3

TDI/AN6/INT41/P1.4

1 2 3 4 5 6 7 8

24 23 1718

1922 21 20

T3/AVREF/AN8/P1.6

RST/P1.7

XTAL2/P3.3

XTAL1/P3.4

VDD

VSS

P1CEX0/P3.2

P3.0/AN9/SS

P3.5/AN10

P2.0/SCK/P1CEX1

P2.1/MISO/TXD2

P2.2/MOSI/RXD2

P2.3/VIN

P2.4

Note:

In pin designation, the pin function written on the outermost side has the highest priority and the innermost pin function has the

lowest priority (see the pin configuration diagram). When a pin is occupied by a high-priority function, it cannot be used as a pin

of a low-priority function even if the low-priority function is enabled. Only when the software disables the high-priority function of

the pin can the corresponding pin be released as a low-priority port.

SH79F6441

4.3 QFN32 Package

P3.1/INT0/ECI1

TCK/AN7/INT40/P1.5

SH79F6441

P2.5/PWM2

P0.6/ECI2

P0.7/INT1/P2CEX0

P2.7/INT46/P2CEX1

P2.6/INT45

P0.5/AN3

P0.4/AN2

P0.3/AN1

AN0/P0.2

INT3/P0.1

P0.0

INT47/P1.0

INT44/P1.1

SWE/TDO/AN4/INT43/P1.2

TMS/AN5/INT42/P1.3

TDI/AN6/INT41/P1.4

1 2 3 4 5 6 7 8

24 23 1718

1922 21 20

T3/AVREF/AN8/P1.6

RST/P1.7

XTAL2/P3.3

XTAL1/P3.4

VDD

VSS

P1CEX0/P3.2

P3.0/AN9/SS

P3.5/AN10

P2.0/SCK/P1CEX1

P2.1/MISO/TXD2

P2.2/MOSI/RXD2

P2.3/VIN

P2.4

Note:

In pin designation, the pin function written on the outermost side has the highest priority and the innermost pin function has the

lowest priority (see the pin configuration diagram). When a pin is occupied by a high-priority function, it cannot be used as a pin

of a low-priority function even if the low-priority function is enabled. Only when the software disables the high-priority function of

the pin can the corresponding pin be released as a low-priority port.

SH79F6441

4.4 SOP28 Package

ECI1/INT0/P3.1

TCK/AN7/INT40/P1.5

SH79F6441

P2.5/PWM2

P0.6/ECI2

P0.7/INT1/P2CEX0

P2.7/INT46/P2CEX1

P2.6/INT45

P0.5/AN3

P0.4/AN2

P0.3/AN1

SWE/TDO/AN4/INT43/P1.2

TMS/AN5/INT42/P1.3

TDI/AN6/INT41/P1.4

T3/AVREF/AN8/P1.6

RST/P1.7

XTAL2/P3.3

XTAL1/P3.4

VDD

VSS

P1CEX0/P3.2

SS/AN9/P3.0

AN10/P3.5 P2.0/SCK/P1CEX1

P2.1/MISO/TXD2

P2.2/MOSI/RXD2

P2.3/VIN

P2.4

P0.2/AN0

Note:

In pin designation, the pin function written on the outermost side has the highest priority and the innermost pin function has the

lowest priority (see the pin configuration diagram). When a pin is occupied by a high-priority function, it cannot be used as a pin

of a low-priority function even if the low-priority function is enabled. Only when the software disables the high-priority function of

the pin can the corresponding pin be released as a low-priority port.

SH79F6441

LCM (Logical Function Configuration Module) Pin Allocation Table

Function

UART0

UART1

TWI

PWM0

PWM1

INT2

PCA0

RXD0 TXD0 RXD1 TXD1 SCL SDA PWM0 PWM1 INT2 P0CEX0

P0CEX1

ECI0

P0.0

●●■

P0.1 ●●

P0.2

●●●●

P0.3 ●●●

P0.4

●■●

P0.5 ■●●●

P0.6

■●●

P0.7 ●■

P1.0

■●

P1.1 ●■

P1.2

P1.3

P1.4

P1.5

P1.6 ●●

P1.7 ●●

P2.0 ●●

P2.1 ●●●

P2.2 ●●●

P2.3 ■●

P2.4 ●●■

P2.5

●●

P2.6 ●●■●

P2.7

●●

P3.0 ●●■

P3.1

●●

P3.2 ●●

P3.3

●●●●●

P3.4 ●●●●

P3.5

●■●

P3.6 ●

P3.7

●

P4.0 ●

P4.1

●

P4.2 ●●●

P4.3

●●●

P4.4 ●

P4.5 ●●●

P4.6 ●●●

P4.7 ●

P5.0 ●●●

P5.1 ●●●

Note:

In Table, the black dots (

●

) respected the functions which can be configurated for the pin; The black square (



) respected the

default function pin of logic configuration module after reset. The black square (



) can be configurated to corresponding black

dots (

●

) pin through LCM.

The priority of LCM is lower than all the other function of the pin (except IO function).

SH79F6441

5. Pin Description

Pin No. Type Description

I/O PORT

P0.0-P0.7 I/O 8-bit bi-directional I/O port

P1.0-P1.7 I/O 8-bit bi-directional I/O port

P2.0-P2.7 I/O 8-bit bi-directional I/O port

P3.0-P3.7 I/O 8-bit bi-directional I/O port

P4.0-P4.7 I/O 8-bit bi-directional I/O port

P5.0-P5.1 I/O 2-bit bi-directional I/O port

Timer

T3 I Time3 external input

PWM Controller

PWM0 O 12-bit output pin for PWM0

PWM1 O 12-bit output pin for PWM1

PWM2 O 12-bit output pin for PWM2

EUART

RXD0/1/2 I EUART0/1/2 data input

TXD0/1/2 O EUART0/1/2 data output

TWI

SDA I/O TWI data input/output pin

SCL I/O TWICLK pin

SPI

MOSI I/O SPI master output slave input pin

MISO I/O SPI master input slave out pin

SCK I/O SPI serial clock pin

——— I SPI slave device select pin

ADC

AN0 - AN13 I ADC input pin

AVREF I ADC external analog reference voltage pin

Interrupt & Reset & Clock & Power

INT0 - INT3 I External interrupt 0-3 input source

INT40 - INT47 I External interrupt 40-47 input source

RST

———— I The device will be reset by a low voltage on this pin longer than 10us, an internal

resistor about 100kΩ to VDD, So using only an external capacitor to GND can cause

a PIN reset.

XTAL1 I Resonator input

XTAL2 O Resonator output

VSS P Ground

VDD P Power source (2.7 - 5.5V)

(to be continued)

SH79F6441

(continue)

PCA Controller

P0CEX0 I/O Input/output pin for PCA0 module 0

P0CEX1 I/O Input/output pin for PCA0 module 1

ECI0 I The external clock input for PCA0

P1CEX0 I/O Input/output pin for PCA1 module 0

P1CEX1 I/O Input/output pin for PCA1 module 1

ECI1 I The external clock input for PCA1

P2CEX0 I/O Input/output pin for PCA2 module 0

P2CEX1 I/O Input/output pin for PCA2 module 1

ECI2 I The external clock input for PCA2

LPD

VIN I LPD detection voltage input port

Single line simulation interface

SWE (P1.2) I/O Single-line simulation interface. If the chip VDD power-on or power-down slope is

greater than 500ms/V, it is recommended to connect 47K - 1M resistors to GND or

VDD to increase the stability of the chip.

Programming interface

TDO (P1.2) O Debug interface: Test data out

TMS (P1.3) I Debug interface: Test mode select

TDI (P1.4) I Debug interface: Test data input

TCK (P1.5) I Debug interface: Test clock input

Note: When P1.2-1.5 is used as a debugging interface, the original function of P1.2-1.5 is forbidden.

SH79F6441

6. SFR Mapping

The SH79F6441 contains a 256-byte direct-addressed register, including general-purpose data memory and special function

registers (SFR). The SH79F6441 has the following SFR:

CPU Core Registers: ACC, B, PSW, SP, DPL, DPH

Enhanced CPU Core Registers: AUXC, DPL1, DPH1, INSCON, XPAGE

Power and Clock Control Registers: PCON,SUSLO

Flash Registers: IB_OFFSET, IB_DATA, IB_CON1, IB_CON2, IB_CON3, IB_CON4, IB_CON5,

FLASHCON

Data Memory Register: XPAGE

Watchdog Timer Registers: RSTSTAT

System Clock Control Registers: CLKCON

Interrupt System Registers: IEN0, IEN1, IEN2, IENC, IPH0, IPL0, IPH1, IPL1, EXF0, EXF1, EXCON, TCON

I/O RegistersPort: P0, P1, P2, P3, P4, P5, P0CR, P1CR, P2CR, P3CR, P4CR, P5CR, P0PCR, P1PCR,

P2PCR, P3PCR, P4PCR, P5PCR, PIMS0, PIMS1, PIMS2

Timer Registers: T3CON, TH3, TL3

PCA Registers: PCACON, P0TOPL, P0TOPH, P0CMD, P0CF, P0CPM0, P0CPM1, P0CPL0, P0CPH0,

P0CPL1, P0CPH1, P0FORCE, P1TOPL, P1TOPH, P1CMD, P1CF, P1CPM0,

P1CPM1, P1CPL0, P1CPH0, P1CPL1, P1CPH1, P1FORCE, P2TOPL, P2TOPH,

P2CMD, P2CF, P2CPM0, P2CPM1, P2CPL0, P2CPH0, P2CPL1, P2CPH1, P2FORCE

EUART Registers: PCON, SCON, SBUF, SADEN, SADDR, SBRTL, SBRTH, SFINE, SCON1, SBUF1,

SADEN1, SADDR1, SBRTL1, SBRTH1, SFINE1, PCON2, SCON2, SBUF2, SADEN2,

SADDR2, SBRTL2, SBRTH2, SFINE2

SPI Register: SPCON, SPSTA, SPDAT

TWI Register: TWICON, TWIPCR, TWITOUT, TWISTA, TWTFREE, TWIBR, TWIADR, TWIDAT,

TWIAMR

ADC Register: ADCON1, ADCON2, ADT, ADCH1, ADCH2, ADDxL, ADDxH, SEQCON, SEQCHX

LCM Register: UART0CR, UART1CR, TWICR, PWMCR, CEXCR, ECICR

PWM Register: PWM0CON, PWM1CON, PWM2CON, PWM0PL, PWM0PH, PWM0DL, PWM0DH,

PWM1PL, PWM1PH, PWM1DL, PWM1DH, PWM2PL, PWM2PH, PWM2DL,

PWM2DH

LPD Register: LPDCON, LPDSEL

CRC Register: CRCCON, CRCDL, CRCDH, CRCSTAL, CRCSTAH, CRCSTOL, CRCSTOH

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