ST Teseo-LIV4FM Bedienungsanleitung
Introduction
The Teseo-LIV4F and Teseo-LIV4FM modules are an easy-to-use Global Navigation Satellite System (GNSS) standalone low
power module, embedding Teseo IV single die GNSS receiver IC working simultaneously on multiple constellations (GPS/
Galileo/Glonass/BeiDou/QZSS) able to provide positioning (Teseo-LIV4F) or raw measurement data (Teseo-LIV4FM).
Teseo-LIV4F and Teseo-LIV4FM hardware documentation
UM3004
User manual
UM3004 - Rev 3 - November 2023
For further information contact your local STMicroelectronics sales office.
www.st.com
1 Pin out
In the following figure, the pin out of the module:
Figure 1. Pin out
LIV4F/FM
GND RF
RF IN
GND RF
Reserved
VCC RF
Reserved
SDA
SCL
PRTRG
Main supply
Reset
GPIO
General ground pin
RF ground
RF ground
Antenna connexion (50 Ω)
Antenna supply
I2C (internal pull-up)
Backup supply
PPS
UART Rx from MCU
UART Tx to MCU
9
8
7
6
5
4
3
2
1
RESETn
VCC
VBATT
EXTINT
PPS
UART_RX
B0/UART_TX
GND
Reserved
10
11
12
13
14
15
16
17
18
Mode pin
UM3004
Pin out
UM3004 - Rev 3 page 2/17
2 Power
Teseo-LIV4F/FM is supplied by two power pins:
•VCC (pin 8)
VCC is the main supply: its range can be from 1.8 V to 3.3 V.
At startup or during low power application, current can change suddenly. It is important to use power device
able to provide this current variation. Use LDO above 200 mA current.
•VBAT (pin 6)
VBAT is the supply for the low power domain backup: RAM and RTC. Its range can be from 1.8 V to 3.3 V.
It can be either connected to VCC or it can be supplied by a dedicated supply always ON. VBAT supply can
be kept ON during low power mode to allow fast recovery of GNSS fix.
If no backup supply is available, leave VBAT pin floating.
2.1 VCC_RF (pin 14)
VCC_RF is an output supply for external active antenna. The current is limited below 35 mA.
2.2 Power supply design reference
For first PCB, it is recommended to plan to have some filtering components on Teseo-LIV4F/FM power supplies
as follows:
Figure 2. Power supply filtering
Note: Decoupling capacitor must be placed close to module pin.
UM3004
Power
UM3004 - Rev 3 page 3/17
2.3 Current consumption optimization
To optimize battery current consumption, it is possible to use a SMPS at 1.8 V to supply VCC.
Here is an application example with ST1S15J18R with an efficiency around 85%.
Figure 3. Example of SMPS to improve current consumption
1MΩ
4.7µF
VIN 2.3V – 5.5V
470nH
ST1S15J18R
MODE
A1
SW
B1
FB
C1
VIN
GND C2
4.7µF
LQM21PNR47MC0D
B2
A2
EN
UM3004
Power
UM3004 - Rev 3 page 4/17
3 Reserved (pin 7, pin 13 and pin 15)
In Teseo-LIV4F/FM, the pin 7, pin 13 and pin 15 are reserved. Let the pin floating.
UM3004
Reserved (pin 7, pin 13 and pin 15)
UM3004 - Rev 3 page 5/17
4 Interfaces
4.1 I2C (pin 16, pin 17)
I2C is in slave only.
Internal 4.7 kΩ pull-up resistor on VCC is present. It is important to avoid having other pull-up for current leakage
in low power mode.
4.2 UART (pin 2, pin 3)
UART is Universal Asynchronous Receiver/Transmitter that supports much of the functionality of the industry-
standard 16C650 UART.
These UARTs vary from industry-standard 16C650 on some minor points which are:
• Receive FIFO trigger levels.
• The internal register map address space, and the bit function of each register differ.
• The deltas of the modem status signals are not available.
• 1.5 stop bit is not supported.
• Independent receive clock feature is not supported.
UM3004
Interfaces
UM3004 - Rev 3 page 6/17
5 I/O pins
5.1 PPS (pin 4)
PPS is the time pulse every one second. It can be configured with different condition of pulses.
For firsts PCB, it is recommended to plan to have some filtering components on Teseo-LIV4F/FM PPS (pin 4).
5.2 EXTINT (pin 5)
It is a GPIO which, by default, is a trigger pin to external interrupt.
Leave it floating if not used.
5.3 RESETn (pin 9)
It can force a Teseo-LIV4F/FM under reset.
Reset signal is active low.
Host processor must have full control of this pin to guarantee the Teseo-LIV4F/FM’s firmware upgrade support.
Do not use pull-up or pull-down when connecting to MCU.
5.3.1 Reset minimum timing
Table 1. Reset minimum timing
Parameter Symbol Pin Condition Min. Typ. Max Unit
Reset input time tRSTL RESETn There is power supply and the oscillator is stable 100 - - mS
Figure 4. Reset (RESETn pin) minimum timing
tRSTL
5.4 RF_IN (pin 10)
It is the RF input.
DC (equals to VCC voltage) is present Teseo-LIV4F/FM version.
5.5 PRTRG (pin 18)
Keep PRTRG pin floating during system power-up or the external reset (RESETn from low to high), and the
module will enter User Normal Mode.
It’s a programming pin used to program the module in production line.
Leave PRTRG pin floating.
UM3004
I/O pins
UM3004 - Rev 3 page 7/17
6 Standby mode
Standby mode is the mode where only low power backup domain is running and VCC is OFF. It means VBAT
must be always maintained. It allows to have very low current consumption and fast GNSS reacquisition at the
end of the standby time due to RTC.
Teseo-LIV4F/FM offers 1 way of standby: HW standby.
As IO buffers are not supplied during standby mode, it is important to keep all IO without external voltage to avoid
any current leakage.
UM3004
Standby mode
UM3004 - Rev 3 page 8/17
7 Front ends management
RF input impedance is 50 Ω.
7.1 Passive antenna
A passive antenna can be directly connected to Teseo-LIV4F/FM. Take care that the antenna must be close to the
module. In addition, it could be possible that a matching component must be necessary to match the antenna.
As RF_IN provides supply for antenna, a DC cut capacitor could be necessary in case antenna presents a DC
GND short cut.
Figure 5. Passive antenna
LIV4F/FM
10
11
12
13
14
15
16
17
18
9
8
7
6
5
4
3
2
1
RESETn
VCC
VBATT
EXTINT
PPS
UART_RX
B0/UART_TX
GND
GND RF
RF IN
GND RF
Reserved
VCC RF
Reserved
SDA
SCL
PRTRG
Reserved
56 pF
UM3004
Front ends management
UM3004 - Rev 3 page 9/17
7.2 External LNA
External LNA means a passive antenna used with an LNA on the same PCB as Teseo-LIV4F/FM module.
There are built-in LNA and SAW in the GNSS module. It is recommended to use an LNA with gain less than 36
dB and noise figure less than 1.5 dB.
Here is a bloc diagram describing the connection:
Figure 6. External LNA control
LNA
VCC
LIV4F/FM
10
11
12
13
14
15
16
17
18
9
8
7
6
5
4
3
2
1
RESETn
VCC
VBATT
EXTINT
PPS
UART_RX
B0/UART_TX
GND
GND RF
RF IN
GND RF
Reserved
VCC RF
Reserved
SDA
SCL
PRTRG
Reserved
UM3004
Front ends management
UM3004 - Rev 3 page 10/17
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