3 Global Bus Resources
There are two main global bus resources available on this motherboard. These are
the bi-directional FIFO with itsHewlett Packard ‘Local Bus’ interface and thestatic
Dual Port RAM (DPR). Mutually exclusive access to these resources can be made
by either of the TIM sites which have a global bus connector (the two nearest the
VXI connectors, sites 1 and 5). TIM A can access the FIFO at the same time as TIM
B is accessing the DPR (or vice-versa). A VXI bus master can also access the on
board DPR at the same time as a TIM is accessing the FIFO.
The DPR is organised to allow the VXI to perform D8, D16 or D32 cycles, byte
swapping buffers are included for this purpose. The DPR access time is 20ns, and
the TIMs are connected to this DPR through fast (approximately 5ns) buffers. This
allows ‘C4x accesses to be performed with one- wait -state. The DPR is decoded at
TIM addresses 0xDF000000 and upward (on ‘C4x STRB1). Extra memory can be
added using the DPR expansion site. TIM access to this DPR can be zero- wait-
state if 12ns devices are used.
The bi-directional FIFO consists of two separate FIFOs, one for incoming and one
for outgoing data. The FIFOs can operate concurrently, although the Hewlett
Packard interface is not full duplex.
Access to the global resources is selected by arbitration state machines. Two
arbiters are present, one controlling access to the FIFO, and the other accesses to the
RAM and VXI bus and board control registers. The relevant resource is left granted
to the last resource master after the cycle has finished. Arbitration only occurs when
two (or more) possible bus masters are requesting the same resource. Arbitration
takes two ‘C4x cycles.
The other Global Bus Resources are VXI bus master access and the board control
registers. Because VXI bus arbitration and Global Bus Resource arbitration are
separate, a deadlock situation can occur. This deadlock isonlypossible when a TIM
starts a VXI bus master cycle around the same time that another VXI bus master
starts a cycle to access the SMT301. This situation is resolved by signaling ‘Bus
Error’ to the existing VXI bus master, which is forced to abort its’ VXI bus cycle.
Thiscycle may bere-tried after ashort delay(a few microseconds) to allow the TIM
VXI cycle to complete. This possibility must be taken into account when designing
system software.
3.1 ‘C4x Comm-port
The ‘C4x VXI interface, is designed to allow the VXI to perform D16 or D32
cycles, to access the comm-port interface register. These accesses are converted to
the correct protocol for communicating via a ‘C4x comm-port. This logic and
associated circuitry includes double buffering on reads and writes negating the need
SMT301 User Guide Sundance
-4- 10 April, 1997
