Terasic Altera Dual-XAUI Bedienungsanleitung
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CONTENTS
CHAPTER 1 INTRODUCTION.................................................................................................................................3
1.1 Features ..................................................................................................................................................................... 3
1.2 Getting Help.............................................................................................................................................................. 4
CHAPTER 2 ARCHITECTURE.................................................................................................................................5
2.1 Block Diagram .......................................................................................................................................................... 6
CHAPTER 3 PIN DESCRIPTION.............................................................................................................................8
3.1 HSMC Expansion Connector.................................................................................................................................... 8
CHAPTER 4 COMPONENTS..................................................................................................................................17
4.1 Featured Device: BCM8727 (U6) ........................................................................................................................... 17
4.2 General User Input/Output...................................................................................................................................... 22
4.3 Clocks ..................................................................................................................................................................... 23
4.4 Memory Devices ..................................................................................................................................................... 24
4.5 Power ...................................................................................................................................................................... 26
CHAPTER 5 BOARD SETUP AND TEST DESIGNS ............................................................................................27
5.1 Board Setup............................................................................................................................................................. 27
5.2 Test Designs Using Stratix IV GX FPGA Development Kit Platform .................................................................... 28
CHAPTER 6 APPENDIX .........................................................................................................................................35
6.1 Revision History ..................................................................................................................................................... 35
6.2 Copyright Statement................................................................................................................................................ 35
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Chapter 1
Introduction
This board is intended to be used by customers to implement and design 10G Ethernet systems
based on transceiver host boards that support XAUI interfaces. This mezzanine card is intended to
be part of an openly sold Development Kit and can be bundled with packages of Software and IP
Cores. It will have 2 full duplex 10G SFP+ channels with a XAUI backend interface. The XAUI to
SFP+ HSMC provides a hardware platform for developing embedded systems based on XAUI
based Altera “GX” based devices. At the time of this document the devices that support XAUI are
Arria GX, Arria II GX, Stratix II GX and Stratix IV GX.
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1.1
1.1
Features
Features
Figure 1-1 shows the photo of the Dual XAUI to SFP+ HSMC board. The important features are
listed below:
•Two independent XAUI interfaces from the HSMC to the BCM8727
•Two independent SFI interfaces from the BCM8727 to SFP+ cages
•MDIO interfaces
•I2C EEPROM for HSMC identification and user data
•Si5334C clock generator
•156.25MHz reference available on SMA connectors and through the HSMC connector
•4 user bi-color LEDS for each channel (8 total bi-color LEDs)
Figure 1-1 Picture of the Dual XAUI to SFP+ HSMC board
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1.2
1.2
Getting
Help
Getting Help
Here are some places to get help if you encounter any problem:
•Email to support@terasic.com
•Taiwan & China: +886-3-550-8800
•Korea : +82-2-512-7661
•Japan: +81-428-77-7000
Chapter 2
Architecture
This chapter describes the architecture of the Dual XAUI to SFP+ HSMC board including block
diagram and components.
Figure 2-1 The Dual XAUI to SFP+ HSMC PCB and component diagram
A photograph of the Dual XAUI to SFP+ HSMC board is shown in Figure 2-1. It depicts the layout
of the board and indicates the location of the connectors and key components.
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2.1
2.1
Block
Diagram
Block Diagram
Figure 2-2 shows the block diagram of the Dual XAUI to SFP+ HSMC board.
Figure 2-2 Block diagram of the Dual XAUI to SFP+ HSMC board
The XAUI interfaces will be attached to the HSMC side of the card and the SFI side of the interface
will be attached to the SFP+ optical modules on the opposite side of the board.
The lower HSMC channels (0 thru 3) are utilized for the XAUI connection for channel 0 and upper
HSMC channels (4 thru 7) are utilized for the XAUI connection for channel 1 of the 10GE channel
links.
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Two SFP+ connectors and cages combined with a SFP+ optical module (not provided with the
board) form the 10GE optical interface. The SFP+ modules communicate with the BCM8727 via
the serial SFI protocol. The SFP interface connector is 20 pins. Most SFP+ optical modules will
contain status and configuration registers accessible through an I2C port. Other signals will include
loss of signal (OPRXLOS[2:1]) and module absent (MOD_ABS[2:1] ).
An oscillator capable of generating 156.25MHz is supplied on the HSMC to provide the host board
with a clean low jitter reference clock. The clock also supplies the XAUI to SFI chip set for CMU
reference use.
Power for the SFP+ modules and the chipset will be provided from the 12V and 3.3V power
available on the HSMC connector.
Chapter 3
Pin Description
This chapter describes the detailed information of the connector interfaces, and the pin description
on the Dual XAUI to SFP+ HSMC board.
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3.1
3.1
HSMC
Expansion
Connector
HSMC Expansion Connector
The Dual XAUI to SFP+ HSMC board contains a HSMC connector. Figure 3-1, Figure 3-2 and
Figure 3-3 show the pin-outs of the HSMC connector on the Dual XAUI to SFP+ HSMC board.
Figure 3-1 Pin-outs of Bank 1 on the HSMC connector
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Figure 3-2 Pin-outs of Bank 2 on the HSMC connector
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