Texas Instruments TSW40RF8 Series Bedienungsanleitung

SLAU706A–January 2017–Revised September 2017

TSW40RF8x Evaluation Module

User's Guide

SLAU706A–January 2017–Revised September 2017

TSW40RF8x Evaluation Module

This user's guide describes the characteristics, operation, and use of the TSW40RF80 and TSW40RF82

Evaluation Module (EVM). A complete schematic diagram, printed-circuit board layouts, and bill of

materials are included in this document.

Contents

1 Introduction ................................................................................................................... 2

2 Software Control ............................................................................................................. 2

3 Basic Set-Up ................................................................................................................. 3

4 Quick Start Procedure....................................................................................................... 4

5 Optional Modes and Information........................................................................................... 7

Appendix A LMK Screen Shots With Quick-Start Configuration .......................................................... 10

Appendix B DAC Screen Shots With Quick-Start Configuration .......................................................... 11

Appendix C ADC Screen Shots With Quick-Start Configuration .......................................................... 12

Appendix D HSDC Pro Screen Shots With Quick-Start Configuration ................................................... 13

List of Figures

1 EVM Block Diagram......................................................................................................... 2

2 Test Set-Up Block Diagram ................................................................................................ 3

3 DAC Output Spectrum ...................................................................................................... 5

4 Captured Output Tone ...................................................................................................... 6

List of Tables

1 Configuration File Name.................................................................................................... 9

2 Configuration File Description.............................................................................................. 9

Trademarks

All trademarks are the property of their respective owners.

SysRef

CLK

SysRef

Ref

FMC Connector

LMK04828

VCXO

TSW40RF80

DAC38RF80

DAC

ADC32RF45

ADC

LMX2582

SysRef

CLK

SysRef

Ref

FMC Connector

LMK04828

VCXO

TSW40RF82

DAC38RF82

ADC32RF45

ADC

LMX2582

DAC

Introduction

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TSW40RF8x Evaluation Module

1 Introduction

1.1 Overview

The TSW40RF8x EVM is a 2T2R RF sampling solution. The board includes the dual 9-GSPS DAC

(DAC38RF8x) and a dual, 14-bit, 3-GSPS ADC (ADC32RF45). The TSW40RF80 uses the DAC38RF80

device with integrated balun and the TSW40RF82 uses the DAC38RF82 device with differential output.

The board includes the required clocking solution needed for sampling the data converters.

1.2 EVM Block Diagram

Figure 1 shows the configuration of the EVM.

Figure 1. EVM Block Diagram

2 Software Control

2.1 Installation Instructions

Use the following instructions to install the software:

• Open the folder named: TSW40RF8x GUI Installer

• Run Setup.exe

• Follow the on-screen instructions

TSW14J56 TSW40RF8x

Power

Supply Power

Supply

PC J15 J17

5 V

USB Spectrum Analyzer

Signal Generator

J12

ChB J4

ChA J3

ChA J9

ChB J10

10 MHz

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Basic Set-Up

SLAU706A–January 2017–Revised September 2017

TSW40RF8x Evaluation Module

3 Basic Set-Up

3.1 Test Block Diagram

Figure 2 shows the test set-up for general testing of the TSW40RF8x EVM.

Figure 2. Test Set-Up Block Diagram

3.2 Test Set-Up

The following steps describe the test set-up procedures:

1. Connect the TSW40RF8x EVM to the TSW14J56 EVM

2. Connect a 5-V supply to the power supply jack

NOTE: Set the current limit to 4.0 A. A 5-V supply with 4-A current capability is required.

3. Connect a 10-MHz signal to J12 at 10 dBm

4. Connect the USB cable to the programming computer

5. Connect an RF cable from J3 to the Spectrum Analyzer. Compensate for the cable loss in the

Reference Level Offset parameter of the instrument.

6. Spectrum Analyzer set up:

•anSet center frequency to: 1960 MHz

•anSet frequency span to: 50 MHz

•anRef Level: approximately 0 dBm

•anSet Reference Level Offset: RF output cable loss

•anRBW: 300 kHz

•anVBW: 3 kHz

•anAttn: 10 dB

7. Connect the signal generator through BPF and into J9 for the RX

•anSet the frequency to: 1960 MHz

•anSet amplitude to: 10 dB

Quick Start Procedure

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4 Quick Start Procedure

4.1 Initial Configuration and DAC Output

Use the following for initial configuration and DAC output:

• Engage the 5-V supply; the initial current should be 1.6 ±0.2 A

• Launch the TSW40RF8x EVM GUI:

– Go to Start →Texas Instruments →TSW40RF8x GUI

NOTE: USB connection is possible only when the power is engaged to the board.

– If needed, press the Connect FTDI? button to establish the USB connection; pressing this button

multiple times may be necessary to get it to engage

• Select the DAC38RF8x tab →Quick Start tab

• Press the LOAD DEFAULT button

NOTE: This loads the file:

2T2R_RevC_ConstInput_12xDec_18xInt_2949p12M_4915p2Gb.cfg

This also loads the proper registers but does not back-fill the values to the ADC tab front

panel. To complete this task go to Low Level tab and press the Read All icon.

Read All does not back-fill the DAC NCO frequency value. If desired, manually go to the

DAC38RF8x tab →DAC38RF8x tab →Digital(DAC A/B) to change NCO Frequency(MHz)

to: 1960.

Read All does not load the actual ADC NCO frequency (the NCO value is loaded). To see

the frequency go to ADC32RFxx tab →ADC32RFxx tab →DDC Configuration tab. Place

cursor in the numerical value and hit a space then enter; the NCO frequency is then

calculated.

This file engages the DAC constant input feature to easily see an output tone without pattern

generation; this must be disengaged when sending a digital pattern to the DAC.

• Press the PLL AUTO TUNE button

• Verify:

– LED D4 and D5 illuminate

– 5-V supply current increases to 3.6 ±0.4 A

• Verify tone output on the spectrum analyzer exists at 1960 MHz at:

– TSW40RF80: –2 ±2 dBm

– TSW40RF82: 0 ±2 dBm

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Quick Start Procedure

SLAU706A–January 2017–Revised September 2017

TSW40RF8x Evaluation Module

Figure 3. DAC Output Spectrum

4.2 ADC Output

Use the following to set ADC Output:

• Launch High-Speed Data Converter Pro (HSDC Pro) version 4.2, or later

• Load the ini file: ADC32RF80_LMF_8821.ini

– Confirm yes to load firmware

• Change to Complex FFT

• Change to Channel 1/8

• Toggle the ADC Output Setup icon

– Click Enable? and Remember for this session

– Change the ADC Sampling rate to: 2949.12M

– Change the ADC Input Frequency to: 1960M

– Change NCO to: –1890M

– Change Decimation to: 12

– Press the OK button

• Press the Capture button

• Verify that LED D4 on TSW14J56 is blinking

• Verify tone capture in HSDC Pro similar to Figure 4

Quick Start Procedure

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Figure 4. Captured Output Tone

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Optional Modes and Information

SLAU706A–January 2017–Revised September 2017

TSW40RF8x Evaluation Module

5 Optional Modes and Information

5.1 Software Manipulation

This section includes directions for software manipulation:

5.1.1 Enter ADC NCO Adjustment

• Select the ADC32RFxx tab →ADC32RFxx tab →DDC Configuration tab

• Adjust NCO frequency values as desired, and press enter; this will calculate the closest NCO

numerical value

• Place the cursor in the NCO numerical value, press the space bar then press the Enter key; this will

calculate the exact NCO frequency value.

5.1.2 DAC NCO Adjustment

• Select the DAC38RF8x tab →DAC38RF8x tab →Digital(DACA/B) tab

• Change the desired NCO value at: NCO →NCO Frequency(MHz) (for example, 1960)

• Select Update NCO

5.2 DAC Pattern Generation

DAC pattern generation is set up with the following:

• Select the DAC38RF8x tab →DAC38RF8x tab →Digital(DACA/B) tab

– Un-select Constant input

• Select the DAC tab on the HSDC Pro Software

• Load: DAC38RF8x_LMF_841_RevD.ini

• Change Data Rate (SPS) to: 491.52M

• Change the DAC Option to: 2’s Compliment

• Modify I/Q Multitone Generator

– Set Tone BW to: 1

– Set # to: 1

– Set Tone Center to: 0

– Set the Tone Selection to: Complex

– Press the Create Tones button

• Press the Send button; click OK if a window pops up

• Verify:

– LED D2 on the TSW14J56 flashes

– The tone output located at NCO frequency value (for example, 1960 MHz)

• The Reset DAC JESD Core & SYSREF TRIGGER button in the DAC38RF8x tab →Quick Start

tab may need to be pressed

5.3 HSDC Pro ini Files

HSDC Pro ini files are discussed in this section:

5.3.1 Transceiver Mode

• Transceiver mode allows TX and RX to operate simultaneously

• Transceiver mode is enabled when Transceiver Mode = 1 in the ini file for both DAC and ADC ini files

• Transceiver mode is limited to SerDes speeds of 5 Gbps or less

Optional Modes and Information

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5.3.2 ini File Modification

• DAC ini files are the same as used by the DAC38RF8x EVM; modify parameter Transceiver Mode = 1

for transceiver mode, if desired.

• ADC ini files are the same as used by ADC32RFxx EVM; modify parameter Transceiver Mode = 1 for

transceiver mode, if desired.

5.4 ADC Clocking Options

Use the following steps for ADC clocking options:

1. Default clock mode: JP3, JP7, JP8 = [111]

• LMX2582 is the clock source for the ADC

2. LMK Clock: JP3, JP7, JP8 = [131]

• Add jumper at JP5 to disable the LMX device

• LMX04028 serves as ADC clock source

3. DAC Output Clock: JP3, JP7, JP8 = [311]

• Divided down RF DAC output clock used as ADC input clock

• Add jumper at JP5 to disable the LMX device

• Modify DAC clock output

– Select DAC38RF8x tab →DAC38RF8x tab →Clocking tab

– Verify the CLKTX divider is set to: /3

– Set Peak to Peak Swing to maximum: 1.4V

– Un-select the Sleep check box

4. External clock: JP3, JP7, JP8 = [113]

• Feed external clock at J8

• Add jumper at JP5 to disable the LMX device

5.5 DAC External Clocking Options

The DAC clock may be injected from an outside source.

NOTE: The DAC SysRef is still generated from the LMK so it must be set up properly for the desired

clock frequency.

• Inject external DAC clock at J1; set amplitude to 10 dBm, or greater.

• Modify the GUI on DAC38RF8x tab →DAC38RF8x tab →Clocking

– Check External Clock Select to engage Single-Ended clock input

– Un-check DAC PLL Settings →PLL Enable

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Optional Modes and Information

SLAU706A–January 2017–Revised September 2017

TSW40RF8x Evaluation Module

5.6 Alternative Configuration File Options

Table 1 and Table 2 describe the available pre-created configuration file options. Check the

TSW40RF8xEVM product page for updated configuration files if desired.

Table 1. Configuration File Name

File # File Name

1 2T2R_RevC_ConstInput_12xDec_18xInt_2949p12M_4915p2Gb.cfg

2 2T2R_RevC_ConstInput_8xDec_12xInt_2949p12M_7372p8Gb.cfg

3 2T2R_RevC_ConstInput_12xDec_24xInt_2949p12M_5898p2_2IQ_4915p2Gb.cfg

4 2T2R_RevC_ADC-BypassLMFS82820_18xInt_2949p12.cfg

5 2T2R_RevC_ADC-Bypass-82820_DAC-Int18x-8847p36M_TxClkOut-Div3.cfg

6 2T2R_RevC_ConstInput_12xDec_18xInt_2949p12M_4915p2Gb_TXClkOut-Div3.cfg

7 2T2R_RevC_ConstInput_12xDec_12xInt_2949p12M_5898p2_4915p2Gb.cfg

8 2T2R_RevC_ConstInput_6xDec_18xInt_2949p12M_4915p2Gb_2ndNyquist.cfg

9 2T2R_RevC_ConstInput_6xDec_12xInt_2949p12M_5898p2_4915p2Gb.cfg

10 2T2R_RevC_ConstInput_4xDec_12xInt_2949p12M_7372p8G.cfg

Table 2. Configuration File Description

File # TCVR

Mode DAC

Clock

[MHz]

I/Q

Paths Int NCO

[MHz] Const

Input Mode ADC

Clock

[MHz]

ADC

Clock

Source

Dec NCO

[MHz]

1 Yes 8847.36 1 18 1960 Yes DDC 2949.12 LMX 12 1890

2 No 8847.36 1 12 1960 Yes DDC 2949.12 LMX 8 1890

3 Yes 5898.24 2 24 1960 Yes DDC 2949.12 LMX 12 1890

4 No 8847.36 1 18 1960 Yes Bypass 2949.12 LMX - -

5 No 8847.36 1 18 1960 Yes Bypass 2949.12 DAC - -

6 Yes 8847.36 1 18 1960 Yes DDC 2949.12 DAC 12 1890

7 Yes 5898.24 1 12 1960 Yes DDC 2949.12 LMX 12 1890

8 Yes 8847.36 1 18 1960 Yes DDC 2949.12 LMX 6 1890

9 Yes 5898.24 1 12 1960 Yes DDC 2949.12 LMX 6 1890

10 No 8847.36 1 12 1960 Yes DDC 2949.12 LMX 4 1890

5.7 Manual Software Adjustment

In general, the GUI software operates similar to the individual GUIs of the DAC38RF8x EVM and the

ADC32RFxx EVM. It is possible to operate in a manual mode following the procedure of the RF DAC and

RF ADC respectively; however, there are a few minor differences.

5.7.1 RF DAC Set-Up Conditions

The DAC PLL reference frequency is derived from the LMK VCO divided down outputs. This is the only

way to provide this reference; there is no option for external PLL reference.

5.7.2 RF ADC Set-Up Conditions

• ADC SysRef is generated through the LMK device so its VCO must be set to the desired clocking

frequency.

• Clock divider for the FPGA is calculated based on SerDes rate of the DAC.

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LMK Screen Shots With Quick-Start Configuration

Appendix A

SLAU706A–January 2017–Revised September 2017

LMK Screen Shots With Quick-Start Configuration

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