Texas Instruments TMS320DM357 Bedienungsanleitung

TMS320DM357 DMSoC Universal Serial Bus(USB) Controller

User's Guide

Literature Number: SPRUGH3November 2008

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Contents

Preface ....................................................................................................................................... 111 Introduction ....................................................................................................................... 141.1 Purpose of the Peripheral .............................................................................................. 141.2 Features .................................................................................................................. 141.3 Features Not Supported ................................................................................................ 141.4 Functional Block Diagram .............................................................................................. 151.5 Supported Use Case Examples ....................................................................................... 161.6 Industry Standard(s) Compliance Statement ........................................................................ 222 Peripheral Architecture ....................................................................................................... 232.1 Clock Control ............................................................................................................. 232.2 Signal Descriptions ...................................................................................................... 232.3 Indexed and Non-Indexed Registers .................................................................................. 232.4 USB PHY Initialization .................................................................................................. 242.5 Dynamic FIFO Sizing ................................................................................................... 243 USB Controller Host and Peripheral Modes Operation ............................................................ 243.1 USB Controller Peripheral Mode Operation .......................................................................... 263.2 USB Controller Host Mode Operation ................................................................................ 443.3 DMA Operation .......................................................................................................... 573.4 Interrupt Handling ........................................................................................................ 683.5 Test Modes ............................................................................................................... 703.6 Reset Considerations ................................................................................................... 743.7 Interrupt Support ......................................................................................................... 743.8 EDMA Event Support ................................................................................................... 743.9 Power Management ..................................................................................................... 744 Registers ........................................................................................................................... 754.1 Control Register (CTRLR) .............................................................................................. 824.2 Status Register (STATR) ............................................................................................... 834.3 RNDIS Register (RNDISR) ............................................................................................. 834.4 Auto Request Register (AUTOREQ) .................................................................................. 844.5 USB Interrupt Source Register (INTSRCR) .......................................................................... 854.6 USB Interrupt Source Set Register (INTSETR) ..................................................................... 864.7 USB Interrupt Source Clear Register (INTCLRR) ................................................................... 874.8 USB Interrupt Mask Register (INTMSKR) ............................................................................ 884.9 USB Interrupt Mask Set Register (INTMSKSETR) .................................................................. 894.10 USB Interrupt Mask Clear Register (INTMSKCLRR) ............................................................... 904.11 USB Interrupt Source Masked Register (INTMASKEDR) .......................................................... 914.12 USB End of Interrupt Register (EOIR) ................................................................................ 924.13 USB Interrupt Vector Register (INTVECTR) ......................................................................... 924.14 Transmit CPPI Control Register (TCPPICR) ......................................................................... 934.15 Transmit CPPI Teardown Register (TCPPITDR) .................................................................... 934.16 CPPI DMA End of Interrupt Register (CPPIEOIR) .................................................................. 94

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4.17 Transmit CPPI Masked Status Register (TCPPIMSKSR) .......................................................... 954.18 Transmit CPPI Raw Status Register (TCPPIRAWSR) ............................................................. 954.19 Transmit CPPI Interrupt Enable Set Register (TCPPIIENSETR) ................................................. 964.20 Transmit CPPI Interrupt Enable Clear Register (TCPPIIENCLRR) ............................................... 964.21 Receive CPPI Control Register (RCPPICR) ......................................................................... 974.22 Receive CPPI Masked Status Register (RCPPIMSKSR) .......................................................... 974.23 Receive CPPI Raw Status Register (RCPPIRAWSR) .............................................................. 984.24 Receive CPPI Interrupt Enable Set Register (RCPPIENSETR) ................................................... 984.25 Receive CPPI Interrupt Enable Clear Register (RCPPIIENCLRR) ............................................... 994.26 Receive Buffer Count 0 Register (RBUFCNT0) ..................................................................... 994.27 Receive Buffer Count 1 Register (RBUFCNT1) .................................................................... 1004.28 Receive Buffer Count 2 Register (RBUFCNT2) .................................................................... 1004.29 Receive Buffer Count 3 Register (RBUFCNT3) .................................................................... 1014.30 Transmit CPPI DMA State Word 0 (TCPPIDMASTATEW0) ..................................................... 1014.31 Transmit CPPI DMA State Word 1 (TCPPIDMASTATEW1) ..................................................... 1024.32 Transmit CPPI DMA State Word 2 (TCPPIDMASTATEW2) ..................................................... 1024.33 Transmit CPPI DMA State Word 3 (TCPPIDMASTATEW3) ..................................................... 1034.34 Transmit CPPI DMA State Word 4 (TCPPIDMASTATEW4) ..................................................... 1034.35 Transmit CPPI DMA State Word 5 (TCPPIDMASTATEW5) ..................................................... 1044.36 Transmit CPPI Completion Pointer (TCPPICOMPPTR) .......................................................... 1044.37 Receive CPPI DMA State Word 0 (RCPPIDMASTATEW0) ...................................................... 1054.38 Receive CPPI DMA State Word 1 (RCPPIDMASTATEW1) ...................................................... 1054.39 Receive CPPI DMA State Word 2 (RCPPIDMASTATEW2) ...................................................... 1074.40 Receive CPPI DMA State Word 3 (RCPPIDMASTATEW3) ...................................................... 1074.41 Receive CPPI DMA State Word 4 (RCPPIDMASTATEW4) ...................................................... 1094.42 Receive CPPI DMA State Word 5 (RCPPIDMASTATEW5) ...................................................... 1094.43 Receive CPPI DMA State Word 6 (RCPPIDMASTATEW6) ...................................................... 1104.44 Receive CPPI Completion Pointer (RCPPICOMPPTR) ........................................................... 1104.45 Function Address Register (FADDR) ................................................................................ 1114.46 Power Management Register (POWER) ............................................................................ 1114.47 Interrupt Register for Endpoint 0 Plus Transmit Endpoints 1 to 4 (INTRTX) ................................... 1124.48 Interrupt Register for Receive Endpoints 1 to 4 (INTRRX) ....................................................... 1124.49 Interrupt Enable Register for INTRTX (INTRTXE) ................................................................. 1134.50 Interrupt Enable Register for INTRRX (INTRRXE) ................................................................ 1134.51 Interrupt Register for Common USB Interrupts (INTRUSB) ...................................................... 1154.52 Interrupt Enable Register for INTRUSB (INTRUSBE) ............................................................. 1164.53 Frame Number Register (FRAME) .................................................................................. 1174.54 Index Register for Selecting the Endpoint Status and Control Registers (INDEX) ............................ 1174.55 Register to Enable the USB 2.0 Test Modes (TESTMODE) ..................................................... 1184.56 Maximum Packet Size for Peripheral/Host Transmit Endpoint (TXMAXP) ..................................... 1194.57 Control Status Register for Endpoint 0 in Peripheral Mode (PERI_CSR0) ..................................... 1204.58 Control Status Register for Endpoint 0 in Host Mode (HOST_CSR0) ......................................... 1214.59 Control Status Register for Peripheral Transmit Endpoint (PERI_TXCSR) .................................... 1224.60 Control Status Register for Host Transmit Endpoint (HOST_TXCSR) ......................................... 1234.61 Maximum Packet Size for Peripheral Host Receive Endpoint (RXMAXP) ..................................... 1244.62 Control Status Register for Peripheral Receive Endpoint (PERI_RXCSR) ..................................... 1254.63 Control Status Register for Host Receive Endpoint (HOST_RXCSR) ......................................... 1264.64 Count 0 Register (COUNT0).......................................................................................... 1284.65 Receive Count Register (RXCOUNT) ............................................................................... 128

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4.66 Type Register (Host mode only) (HOST_TYPE0) ................................................................ 1294.67 Transmit Type Register (Host mode only) (HOST_TXTYPE) ................................................... 1294.68 NAKLimit0 Register (Host mode only) (HOST_NAKLIMIT0) .................................................... 1304.69 Transmit Interval Register (Host mode only) (HOST_TXINTERVAL) .......................................... 1304.70 Receive Type Register (Host mode only) (HOST_RXTYPE) ................................................... 1314.71 Receive Interval Register (Host mode only) (HOST_RXINTERVAL) .......................................... 1314.72 Configuration Data Register (CONFIGDATA) ...................................................................... 1324.73 Transmit and Receive FIFO Register for Endpoint 0 (FIFO0) ................................................... 1344.74 Transmit and Receive FIFO Register for Endpoint 1 (FIFO1) ................................................... 1354.75 Transmit and Receive FIFO Register for Endpoint 2 (FIFO2) ................................................... 1354.76 Transmit and Receive FIFO Register for Endpoint 3 (FIFO3) ................................................... 1364.77 Transmit and Receive FIFO Register for Endpoint 4 (FIFO4) ................................................... 1364.78 OTG Device Control Register (DEVCTL) ........................................................................... 1374.79 Transmit Endpoint FIFO Size (TXFIFOSZ) ......................................................................... 1384.80 Receive Endpoint FIFO Size (RXFIFOSZ) ......................................................................... 1384.81 Transmit Endpoint FIFO Address (TXFIFOADDR) ................................................................ 1394.82 Receive Endpoint FIFO Address (RXFIFOADDR) ................................................................. 1394.83 Transmit Function Address (TXFUNCADDR) ...................................................................... 1404.84 Transmit Hub Address (TXHUBADDR) ............................................................................. 1404.85 Transmit Hub Port (TXHUBPORT) .................................................................................. 1404.86 Receive Function Address (RXFUNCADDR) ...................................................................... 1414.87 Receive Hub Address (RXHUBADDR) .............................................................................. 1414.88 Receive Hub Port (RXHUBPORT) ................................................................................... 141Appendix A Revision History ..................................................................................................... 143

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List of Figures

1 Functional Block Diagram ................................................................................................. 152 Interrupt Service Routine Flow Chart .................................................................................... 253 CPU Actions at Transfer Phases ......................................................................................... 294 Sequence of Transfer ...................................................................................................... 305 Service Endpoint 0 Flow Chart ........................................................................................... 326 IDLE Mode Flow Chart .................................................................................................... 337 TX Mode Flow Chart ....................................................................................................... 348 RX Mode Flow Chart ....................................................................................................... 359 Setup Phase of a Control Transaction Flow Chart ..................................................................... 4510 IN Data Phase Flow Chart ................................................................................................ 4711 OUT Data Phase Flow Chart ............................................................................................. 4812 Completion of SETUP or OUT Data Phase Flow Chart ............................................................... 4913 Completion of IN Data Phase Flow Chart ............................................................................... 5114 Tx Queue Flow Chart ...................................................................................................... 6015 Rx Queue Flow Chart ...................................................................................................... 6516 Control Register (CTRLR) ................................................................................................. 8217 Status Register (STATR) .................................................................................................. 8318 RNDIS Register (RNDISR) ................................................................................................ 8319 Auto Request Register (AUTOREQ) ..................................................................................... 8420 USB Interrupt Source Register (INTSRCR) ............................................................................. 8521 USB Interrupt Source Set Register (INTSETR) ........................................................................ 8622 USB Interrupt Source Clear Register (INTCLRR) ...................................................................... 8723 USB Interrupt Mask Register (INTMSKR)............................................................................... 8824 USB Interrupt Mask Set Register (INTMSKSETR) .................................................................... 8925 USB Interrupt Mask Clear Register (INTMSKCLRR) .................................................................. 9026 USB Interrupt Source Masked Register (INTMASKEDR) ............................................................. 9127 USB End of Interrupt Register (EOIR) ................................................................................... 9228 USB Interrupt Vector Register (INTVECTR) ............................................................................ 9229 Transmit CPPI Control Register (TCPPICR) ........................................................................... 9330 Transmit CPPI Teardown Register (TCPPITDR) ...................................................................... 9331 CPPI DMA End of Interrupt Register (CPPIEOIR) ..................................................................... 9432 Transmit CPPI Masked Status Register (TCPPIMSKSR) ............................................................ 9533 Transmit CPPI Raw Status Register (TCPPIRAWSR) ................................................................ 9534 Transmit CPPI Interrupt Enable Set Register (TCPPIIENSETR) .................................................... 9635 Transmit CPPI Interrupt Enable Clear Register (TCPPIIENCLRR) .................................................. 9636 Receive CPPI Control Register (RCPPICR) ............................................................................ 9737 Receive CPPI Masked Status Register (RCPPIMSKSR) ............................................................. 9738 Receive CPPI Raw Status Register (RCPPIRAWSR)................................................................. 9839 Receive CPPI Interrupt Enable Set Register (RCPPIENSETR) ..................................................... 9840 Receive CPPI Interrupt Enable Clear Register (RCPPIIENCLRR) .................................................. 9941 Receive Buffer Count 0 Register (RBUFCNT0) ........................................................................ 9942 Receive Buffer Count 1 Register (RBUFCNT1) ...................................................................... 10043 Receive Buffer Count 2 Register (RBUFCNT2) ...................................................................... 10044 Receive Buffer Count 3 Register (RBUFCNT3) ...................................................................... 10145 Transmit CPPI DMA State Word 0 (TCPPIDMASTATEW0) ........................................................ 10146 Transmit CPPI DMA State Word 1 (TCPPIDMASTATEW1) ........................................................ 10247 Transmit CPPI DMA State Word 2 (TCPPIDMASTATEW2) ........................................................ 10248 Transmit CPPI DMA State Word 3 (TCPPIDMASTATEW3) ........................................................ 10349 Transmit CPPI DMA State Word 4 (TCPPIDMASTATEW4) ........................................................ 10350 Transmit CPPI DMA State Word 5 (TCPPIDMASTATEW5) ........................................................ 10451 Transmit CPPI Completion Pointer (TCPPICOMPPTR) ............................................................. 10452 Receive CPPI DMA State Word 0 (RCPPIDMASTATEW0) ........................................................ 105

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53 Receive CPPI DMA State Word 1 (RCPPIDMASTATEW1) ........................................................ 10654 Receive CPPI DMA State Word 2 (RCPPIDMASTATEW2) ........................................................ 10755 Receive CPPI DMA State Word 3 (RCPPIDMASTATEW3) ........................................................ 10756 Receive CPPI DMA State Word 4 (RCPPIDMASTATEW4) ........................................................ 10957 Receive CPPI DMA State Word 5 (RCPPIDMASTATEW5) ........................................................ 10958 Receive CPPI DMA State Word 6 (RCPPIDMASTATEW6) ........................................................ 11059 Receive CPPI Completion Pointer (RCPPICOMPPTR) ............................................................. 11060 Function Address Register (FADDR) .................................................................................. 11161 Power Management Register (POWER) .............................................................................. 11162 Interrupt Register for Endpoint 0 Plus Tx Endpoints 1 to 4 (INTRTX) ............................................. 11263 Interrupt Register for Receive Endpoints 1 to 4 (INTRRX) .......................................................... 11364 Interrupt Enable Register for INTRTX (INTRTXE).................................................................... 11365 Interrupt Enable Register for INTRRX (INTRRXE) ................................................................... 11466 Interrupt Register for Common USB Interrupts (INTRUSB) ......................................................... 11567 Interrupt Enable Register for INTRUSB (INTRUSBE) ............................................................... 11668 Frame Number Register (FRAME) ..................................................................................... 11769 Index Register for Selecting the Endpoint Status and Control Registers (INDEX) ............................... 11770 Register to Enable the USB 2.0 Test Modes (TESTMODE) ........................................................ 11871 Maximum Packet Size for Peripheral/Host Transmit Endpoint (TXMAXP) ........................................ 11972 Control Status Register for Endpoint 0 in Peripheral Mode (PERI_CSR0) ....................................... 12073 Control Status Register for Endpoint 0 in Host Mode (HOST_CSR0) ............................................. 12174 Control Status Register for Peripheral Transmit Endpoint (PERI_TXCSR) ....................................... 12275 Control Status Register for Host Transmit Endpoint (HOST_TXCSR) ............................................ 12376 Maximum Packet Size for Peripheral Host Receive Endpoint (RXMAXP) ........................................ 12477 Control Status Register for Peripheral Receive Endpoint (PERI_RXCSR) ....................................... 12578 Control Status Register for Host Receive Endpoint (HOST_RXCSR) ............................................. 12679 Count 0 Register (COUNT0) ............................................................................................ 12880 Receive Count Register (RXCOUNT) .................................................................................. 12881 Type Register (Host mode only) (HOST_TYPE0) .................................................................... 12982 Transmit Type Register (Host mode only) (HOST_TXTYPE) ....................................................... 12983 NAKLimit0 Register (Host mode only) (HOST_NAKLIMIT0) ........................................................ 13084 Transmit Interval Register (Host mode only) (HOST_TXINTERVAL) .............................................. 13085 Receive Type Register (Host mode only) (HOST_RXTYPE) ....................................................... 13186 Receive Interval Register (Host mode only) (HOST_RXINTERVAL) .............................................. 13187 Configuration Data Register (CONFIGDATA) ......................................................................... 13288 Transmit and Receive FIFO Register for Endpoint 0 (FIFO0) ...................................................... 13489 Transmit and Receive FIFO Register for Endpoint 1 (FIFO1) ...................................................... 13590 Transmit and Receive FIFO Register for Endpoint 2 (FIFO2) ...................................................... 13591 Transmit and Receive FIFO Register for Endpoint 3 (FIFO3) ...................................................... 13692 Transmit and Receive FIFO Register for Endpoint 4 (FIFO4) ...................................................... 13693 OTG Device Control Register (DEVCTL) .............................................................................. 13794 Transmit Endpoint FIFO Size (TXFIFOSZ) ............................................................................ 13895 Receive Endpoint FIFO Size (RXFIFOSZ) ............................................................................ 13896 Transmit Endpoint FIFO Address (TXFIFOADDR) ................................................................... 13997 Receive Endpoint FIFO Address (RXFIFOADDR) ................................................................... 13998 Transmit Function Address (TXFUNCADDR) ......................................................................... 14099 Transmit Hub Address (TXHUBADDR) ................................................................................ 140100 Transmit Hub Port (TXHUBPORT) ..................................................................................... 140101 Receive Function Address (RXFUNCADDR) ......................................................................... 141102 Receive Hub Address (RXHUBADDR) ................................................................................ 141103 Receive Hub Port (RXHUBPORT) ..................................................................................... 141

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List of Tables

1 USB Pins .................................................................................................................... 232 PERI_TXCSR Register Bit Configuration for Bulk IN Transactions ................................................. 373 PERI_RXCSR Register Bit Configuration for Bulk OUT Transactions .............................................. 394 PERI_TXCSR Register Bit Configuration for Isochronous IN Transactions ........................................ 415 PERI_RXCSR Register Bit Configuration for Isochronous OUT Transactions ..................................... 436 Transmit Buffer Descriptor Word 0 ....................................................................................... 587 Transmit Buffer Descriptor Word 1 ....................................................................................... 588 Transmit Buffer Descriptor Word 2 ....................................................................................... 589 Transmit Buffer Descriptor Word 3 ....................................................................................... 5810 Receive Buffer Descriptor Word 0 ....................................................................................... 6311 Receive Buffer Descriptor Word 1 ....................................................................................... 6312 Receive Buffer Descriptor Word 2 ....................................................................................... 6313 Receive Buffer Descriptor Word 3 ....................................................................................... 6414 Interrupts Generated by the USB Controller ............................................................................ 6815 USB Interrupt Conditions .................................................................................................. 6816 Universal Serial Bus (USB) Registers ................................................................................... 7517 Control Register (CTRLR) Field Descriptions .......................................................................... 8218 Status Register (STATR) Field Descriptions............................................................................ 8319 RNDIS Register (RNDISR) Field Descriptions ......................................................................... 8320 Auto Request Register (AUTOREQ) Field Descriptions .............................................................. 8421 USB Interrupt Source Register (INTSRCR) Field Descriptions ...................................................... 8522 USB Interrupt Source Set Register (INTSETR) Field Descriptions .................................................. 8623 USB Interrupt Source Clear Register (INTCLRR) Field Descriptions ............................................... 8724 USB Interrupt Mask Register (INTMSKR) Field Descriptions ........................................................ 8825 USB Interrupt Mask Set Register (INTMSKSETR) Field Descriptions .............................................. 8926 USB Interrupt Mask Clear Register (INTMSKCLRR) Field Descriptions ............................................ 9027 USB Interrupt Source Masked Register (INTMASKEDR) Field Descriptions ...................................... 9128 USB End of Interrupt Register (EOIR) Field Descriptions ............................................................ 9229 USB Interrupt Vector Register (INTVECTR) Field Descriptions...................................................... 9230 Transmit CPPI Control Register (TCPPICR) Field Descriptions ..................................................... 9331 Transmit CPPI Teardown Register (TCPPITDR) Field Descriptions ................................................ 9332 CPPI DMA End of Interrupt Register (CPPIEOIR) Field Descriptions .............................................. 9433 Transmit CPPI Masked Status Register (TCPPIMSKSR) Field Descriptions ...................................... 9534 Transmit CPPI Raw Status Register (TCPPIRAWSR) Field Descriptions .......................................... 9535 Transmit CPPI Interrupt Enable Set Register (TCPPIIENSETR) Field Descriptions .............................. 9636 Transmit CPPI Interrupt Enable Clear Register (TCPPIIENCLRR) Field Descriptions ........................... 9637 Receive CPPI Control Register (RCPPICR) Field Descriptions...................................................... 9738 Receive CPPI Masked Status Register (RCPPIMSKSR) Field Descriptions ....................................... 9739 Receive CPPI Raw Status Register (RCPPIRAWSR) Field Descriptions .......................................... 9840 Receive CPPI Interrupt Enable Set Register (RCPPIENSETR) Field Descriptions ............................... 9841 Receive CPPI Interrupt Enable Clear Register (RCPPIIENCLRR) Field Descriptions ............................ 9942 Receive Buffer Count 0 Register (RBUFCNT0) Field Descriptions .................................................. 9943 Receive Buffer Count 1 Register (RBUFCNT1) Field Descriptions ................................................ 10044 Receive Buffer Count 2 Register (RBUFCNT2) Field Descriptions ................................................ 10045 Receive Buffer Count 3 Register (RBUFCNT3) Field Descriptions ................................................ 10146 Transmit CPPI DMA State Word 0 (TCPPIDMASTATEW0) Field Descriptions .................................. 10147 Transmit CPPI DMA State Word 1 (TCPPIDMASTATEW1) Field Descriptions .................................. 10248 Transmit CPPI DMA State Word 2 (TCPPIDMASTATEW2) Field Descriptions .................................. 10249 Transmit CPPI DMA State Word 3 (TCPPIDMASTATEW3) Field Descriptions .................................. 103

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50 Transmit CPPI DMA State Word 4 (TCPPIDMASTATEW4) Field Descriptions .................................. 10351 Transmit CPPI DMA State Word 5 (TCPPIDMASTATEW5) Field Descriptions .................................. 10452 Transmit CPPI Completion Pointer (TCPPICOMPPTR) Field Descriptions....................................... 10553 Receive CPPI DMA State Word 0 (RCPPIDMASTATEW0) Field Descriptions .................................. 10554 Receive CPPI DMA State Word 1 (RCPPIDMASTATEW1) Field Descriptions .................................. 10655 Receive CPPI DMA State Word 2 (RCPPIDMASTATEW2) Field Descriptions .................................. 10756 Receive CPPI DMA State Word 3 (RCPPIDMASTATEW3) Field Descriptions .................................. 10757 Receive CPPI DMA State Word 4 (RCPPIDMASTATEW4) Field Descriptions .................................. 10958 Receive CPPI DMA State Word 5 (RCPPIDMASTATEW5) Field Descriptions .................................. 10959 Receive CPPI DMA State Word 6 (RCPPIDMASTATEW6) Field Descriptions .................................. 11060 Receive CPPI Completion Pointer (RCPPICOMPPTR) Field Descriptions ....................................... 11061 Function Address Register (FADDR) Field Descriptions ............................................................ 11162 Power Management Register (POWER) Field Descriptions ........................................................ 11163 Interrupt Register for Endpoint 0 Plus Transmit Endpoints 1 to 4 (INTRTX) Field Descriptions ............... 11264 Interrupt Register for Receive Endpoints 1 to 4 (INTRRX) Field Descriptions ................................... 11365 Interrupt Enable Register for INTRTX (INTRTXE) Field Descriptions ............................................. 11366 Interrupt Enable Register for INTRRX (INTRRXE) Field Descriptions ............................................. 11467 Interrupt Register for Common USB Interrupts (INTRUSB) Field Descriptions .................................. 11568 Interrupt Enable Register for INTRUSB (INTRUSBE) Field Descriptions ......................................... 11669 Frame Number Register (FRAME) Field Descriptions ............................................................... 11770 Index Register for Selecting the Endpoint Status and Control Registers (INDEX) Field Descriptions ........ 11771 Register to Enable the USB 2.0 Test Modes (TESTMODE) Field Descriptions .................................. 11872 Maximum Packet Size for Peripheral/Host Transmit Endpoint (TXMAXP) Field Descriptions ................. 11973 Control Status Register for Endpoint 0 in Peripheral Mode (PERI_CSR0) Field Descriptions ................. 12074 Control Status Register for Endpoint 0 in Host Mode (HOST_CSR0) Field Descriptions ....................... 12175 Control Status Register for Peripheral Transmit Endpoint (PERI_TXCSR) Field Descriptions ................. 12276 Control Status Register for Host Transmit Endpoint (HOST_TXCSR) Field Descriptions ...................... 12377 Maximum Packet Size for Peripheral Host Receive Endpoint (RXMAXP) Field Descriptions .................. 12478 Control Status Register for Peripheral Receive Endpoint (PERI_RXCSR) Field Descriptions ................. 12579 Control Status Register for Host Receive Endpoint (HOST_RXCSR) Field Descriptions ....................... 12680 Count 0 Register (COUNT0) Field Descriptions ...................................................................... 12881 Receive Count Register (RXCOUNT) Field Descriptions ........................................................... 12882 Type Register (Host mode only) (HOST_TYPE0) Field Descriptions ............................................. 12983 Transmit Type Register (Host mode only) (HOST_TXTYPE) Field Descriptions ................................ 12984 NAKLimit0 Register (Host mode only) (HOST_NAKLIMIT0) Field Descriptions ................................. 13085 Transmit Interval Register (Host mode only) (HOST_TXINTERVAL) Field Descriptions ....................... 13086 Receive Type Register (Host mode only) (HOST_RXTYPE) Field Descriptions ................................. 13187 Receive Interval Register (Host mode only) (HOST_RXINTERVAL) Field Descriptions ........................ 13288 Configuration Data Register (CONFIGDATA) Field Descriptions .................................................. 13289 Transmit and Receive FIFO Register for Endpoint 0 (FIFO0) Field Descriptions ................................ 13490 Transmit and Receive FIFO Register for Endpoint 1 (FIFO1) Field Descriptions ................................ 13591 Transmit and Receive FIFO Register for Endpoint 2 (FIFO2) Field Descriptions ................................ 13592 Transmit and Receive FIFO Register for Endpoint 3 (FIFO3) Field Descriptions ................................ 13693 Transmit and Receive FIFO Register for Endpoint 4 (FIFO4) Field Descriptions ................................ 13694 OTG Device Control Register (DEVCTL) Field Descriptions ....................................................... 13795 Transmit Endpoint FIFO Size (TXFIFOSZ) Field Descriptions ..................................................... 13896 Receive Endpoint FIFO Size (RXFIFOSZ) Field Descriptions ...................................................... 13897 Transmit Endpoint FIFO Address (TXFIFOADDR) Field Descriptions............................................. 13998 Receive Endpoint FIFO Address (RXFIFOADDR) Field Descriptions ............................................. 13999 Transmit Function Address (TXFUNCADDR) Field Descriptions .................................................. 140100 Transmit Hub Address (TXHUBADDR) Field Descriptions .......................................................... 140

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101 Transmit Hub Port (TXHUBPORT) Field Descriptions ............................................................... 140102 Receive Function Address (RXFUNCADDR) Field Descriptions ................................................... 141103 Receive Hub Address (RXHUBADDR) Field Descriptions .......................................................... 141104 Receive Hub Port (RXHUBPORT) Field Descriptions ............................................................... 141A-1 Document Revision History .............................................................................................. 143

List of Tables10 SPRUGH3 – November 2008Submit Documentation Feedback

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