Texas Instruments DAC8881 Bedienungsanleitung

User's Guide

SLAU257A–September 2008–Revised November 2009

DAC8881 Evaluation Module

This user’s guide describes the characteristics, operation, and the use of the DAC8881 evaluation module.

It covers all pertinent areas involved to properly use this EVM board along with the devices that it

supports. The physical PCB layout, schematic diagram, and circuit descriptions are included.

Contents

1 EVM Overview ............................................................................................................... 2

1.1 Features ............................................................................................................. 2

1.2 Power Requirements .............................................................................................. 2

1.3 EVM Basic Functions .............................................................................................. 3

2 PCB Design and Performance ............................................................................................ 4

2.1 PCB Layout ......................................................................................................... 4

2.2 EVM Performance ................................................................................................. 8

2.3 Bill of Materials ..................................................................................................... 9

3 EVM Operation ............................................................................................................ 10

3.1 Factory Default Settings ......................................................................................... 10

3.2 Host Processor Interface ........................................................................................ 11

3.3 Digital Control Interface .......................................................................................... 12

3.4 Analog Output ..................................................................................................... 13

3.5 Jumper Settings .................................................................................................. 14

3.6 Schematics ........................................................................................................ 16

4 Using the DAC8881EVM with DXP ..................................................................................... 16

4.1 Hardware .......................................................................................................... 17

4.2 MMB0 Power Supplies ........................................................................................... 17

4.3 Software – Running DXP ........................................................................................ 18

4.4 DAC Output Update Options .................................................................................... 20

4.5 Data Input Format ................................................................................................ 20

5 Information ................................................................................................................. 21

5.1 Related Documentation from Texas Instruments ............................................................ 21

5.2 Questions About This or Other Data Converter EVMs? ..................................................... 21

List of Figures

1 Block Diagram............................................................................................................... 4

2 Top Silkscreen............................................................................................................... 5

3 Layer 1 (Top Signal Plane) ................................................................................................ 6

4 Layer 2 (Ground Plane).................................................................................................... 6

5 Layer 3 (Power Plane) ..................................................................................................... 7

6 Layer 4 (Bottom Signal Plane) ............................................................................................ 7

7 Bottom Silkscreen........................................................................................................... 8

8 Drill Drawing ................................................................................................................. 8

9 INL and DNL Characteristic Plots......................................................................................... 9

10 DAC8881 EVM Default Jumper Configuration......................................................................... 11

11 MMB0 with DAC8881EVM Installed .................................................................................... 17

12 Loading the DAC8881EVM INI file...................................................................................... 19

13 DAC8881 – Frequency/Amplitude and GPIO Control Options ...................................................... 19

SLAU257A–September 2008–Revised November 2009 DAC8881 Evaluation Module

EVM Overview

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14 DAC Output Update Options............................................................................................. 20

15 Data Format Options...................................................................................................... 20

List of Tables

1 Parts List ..................................................................................................................... 9

2 Factory Default Jumper Settings ........................................................................................ 10

3 Digital Control Interface Signal Mapping for J2/P2 Header/Socket Connectors .................................. 12

4 Bipolar Output Operation Jumper Settings............................................................................. 13

5 Gain of Two Output Jumper Settings................................................................................... 14

6 Capacitive Load Drive Output Jumper Settings ....................................................................... 14

7 Jumper Setting Functions ................................................................................................ 14

8 DXP GPIO Controlled DAC Functions.................................................................................. 19

9 Output Update Features.................................................................................................. 20

1 EVM Overview

This chapter provides a general overview of the DAC8881 evaluation module (EVM) and describes some

of the factors that must be considered in using this module.

1.1 Features

This EVM features the DAC8881 digital-to-analog converter. The DAC8881 EVM is a simple evaluation

module designed for a quick and easy way to evaluate the functionality and performance of the 16-bit high

resolution, voltage output, single channel, and serial input DAC. This EVM features a high-speed serial

interface of up to 50MHz to communicate with any host microprocessor or DSP-based system.

The DAC8881 is designed for unipolar output operation (default mode), but it can also be configured for

bipolar output operation with the addition of an external amplifier and some resistors. The option for

bipolar mode of operation is included in the EVM with just some minor jumper configuration.

A +5V precision voltage reference is provided on-board via U3 (REF02) to supply the necessary external

reference voltage to set the DAC8881 output range. The footprint of U3 is compatible with many SO-8

package type reference devices, so the user has the flexibility to select the reference supply to set the

output range of the DAC8881 other than what is provided on-board. The family of REF50xx precision

reference sources works well with this EVM. In addition, the provision of test points, TP1 and TP8, allows

the user to use their own external reference supply. Typically, TP1 (VREFL) should be connected to ground,

but it can accept up to ±0.2V if necessary. The test point, TP8 (VREFH), is typically set to +5V, but can

accept a minimum of +1.25V and up to a maximum of +5.5V.

The voltage reference configuration implemented on this EVM utilizes the Kelvin connection feature of the

DAC8881 device. This connection helps minimize the internal errors caused by the changing reference

current and its associated circuit impedances.

1.2 Power Requirements

The following sections describe the power requirements of this EVM.

1.2.1 Supply Voltage

The dc power supply requirement for this DAC8881 EVM (AVDD and DVDD) is selectable between +3.3VA

and +5VA via the W1 jumper. The +3.3VA comes from the J6-8 terminal and the +5VA comes from the

J6-3 terminal. These power supply voltages are referenced to analog ground through the J6-5 and J6-6

terminals.

The logic voltage, IOVDD, is selectable between +1.8VD, +3.3VD, and +5VD via the J3 jumper.

VCC and VSS range from +15V to –15V maximum and connect through the J6-1 and J6-2 terminals

respectively. All analog power supplies are referenced to analog ground through the J6-5 and J6-6

terminals.

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EVM Overview

CAUTION

To avoid potential damage to the EVM board, make sure the correct cables are

connected to their respective terminals as labeled on the EVM board.

Stresses above the maximum listed voltage ratings may cause permanent

damage to the device.

1.2.2 Reference Voltage

The DAC8881 requires an external reference source to set the DAC operating voltage output range.

Applying the desired voltage in the range of 1.25V to AVDD to the VREFH pin sets the positive range of the

DAC8881 output. Applying the desired voltage in the range of –0.2V to +0.2V to the VREFL pin sets the

negative range of the DAC8881 output, although the VREFL pin should nominally be set to 0V. The

voltages applied to the VREFH and VREFL pins set the DAC8881 full output voltage swing.

For optimum performance, the DAC8881 supports a set Kelvin connection to the external reference via

the VREFHF and VREFHS pins as well as VREFLF and VREFLS pins. This optional reference configuration

minimizes internal errors caused by the changing reference current and its associated circuit impedances.

A +5V precision voltage reference is provided for the external reference source of the DAC through

REF02, U3. The power supply for the reference device, U3, is selectable between VCC and +5VA via the

W11 jumper to ensure that the correct voltage range of U3 can be set. As mentioned earlier, a device from

the family of REF50xx reference devices can be easily selected and the one installed on the EVM can be

replaced to provide the desired voltage range that is required for evaluation of the DAC8881.

The reference voltages, VREFH and VREFL, are selectable via jumpers W8 and W4. When shorting pins 1

and 2 of both jumpers, the on-board +5V reference via U3 is selected. Shorting pins 2 and 3 of both

jumpers selects the reference voltages that are applied via J4 pins 18 and 20 respectively. These voltages

normally come from the host platform that is interfaced with the DAC8881EVM.

The test points TP1 and TP8 are also provided to allow the user to connect another external reference

source if the on-board reference circuit is not desired. The external voltage reference should not exceed

the applied power supplies (AVDD and DVDD) of the DAC under test.

CAUTION

When applying an external voltage reference through TP8 or J4-20, make sure

that it does not exceed the applied AVDD. Otherwise, this can permanently

damage the DAC8881, U1, device under test.

1.3 EVM Basic Functions

This EVM is designed primarily as a functional evaluation platform to test certain functional characteristics

of the DAC8881 digital-to-analog converter. Functional evaluation of the installed DAC device can be

accomplished with the use of any microprocessor, DSP, or signal/waveform generator.

The headers J2 (top side) and P2 (bottom side) are pass-through connectors provided to allow the control

signals and data required to interface a host processor or waveform generator to the DAC8881 EVM using

a custom built cable.

An adapter interface card (5-6k adapter interface card) is also available to fit and mate with TI’s C5000

and C6000 DSP Starter Kit (DSK). This card alleviates the problems involved in building a custom cable.

In addition, the Precision Analog Application group of Texas Instruments has other interface boards that

are designed to connect to and interface with this EVM as well. For more details or information regarding

the 5-6k adapter interface board or the other interface platforms, call Texas Instruments Inc. or send an

email to [email protected].

SLAU257A–September 2008–Revised November 2009 DAC8881 Evaluation Module

DAC Module

VCC

VSS

VCC

GND

VDD

(J6)

(P 6 )

(J3)

SCLK

VSS

SDI

(J4)

(P4)

(W9)

(W3)

(W12)

VSS

±5 VA

+3.3 VD

U4A

TP2

TP8

LDAC

RST

+1.8 VD

+3.3 VA

U4B

TP1

+5 VA

W11 W1 + 3.3 VA

VCC +5 VA

TP3

SDO

(J2)

(P 2 )

(W 6 )

(W 10 )

REF5050

OPA277

V H

REF

V L

REF

IOVDD

V L

REF

V H

REF AVDD

DVDD

IOVDD

VOUT

RFB DGND AGND

PCB Design and Performance

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The DAC output can be monitored through pins 2 and 6 of the J4 header connector. The DAC output can

be switched through the W2 jumper for stacking the EVM for daisy-chaining purposes.

A block diagram of the EVM is shown in the Figure 1.

Figure 1. Block Diagram

2 PCB Design and Performance

This chapter describes the layout design of the PCB, the physical and mechanical characteristics of the

EVM, and the EVM test performance procedure performed. The list of components on this evaluation

module is also included in this section.

2.1 PCB Layout

The DAC8881 EVM is designed to preserve the performance quality of the DAC, device under test, as

specified in the datasheet. Carefully analyzing the physical restrictions of the EVM and the given or known

elements that contribute to performance degradation of the EVM is key to a successful design

implementation. These obvious attributes that diminish the performance of the EVM can be addressed

during the schematic design phase by selecting appropriate components and building a correct circuit. The

circuit should include adequate bypassing, identifying and managing analog and digital signals, and

knowing or understanding the mechanical attributes of the components.

The critical part of the design is the layout process. The main concern is primarily the placement of

components and the proper routing of signals. The bypass capacitors should be placed as close as

possible to the pins, and the analog and digital signals should be properly separated from each other. The

power and ground plane is very important and should be carefully considered in the layout process. A

solid plane is ideally preferred but sometimes impractical, so when a solid plane is not possible, a split

plane is an acceptable alternative. When considering a split plane design, analyze component placement

and carefully split the board into its analog and digital sections starting from the device under test. The

ground plane plays an important role in controlling noise and other effects that otherwise contribute to the

error of the DAC output. To ensure that the return currents are handled properly, route the appropriate

signals only in their respective sections, meaning the analog traces should only lay directly above or below

the analog section and the digital traces in the digital section. Minimize the length of the traces but use the

largest possible trace width allowable in the design. These design practices can be seen in the following

figures.

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PCB Design and Performance

The DAC8881 EVM board is constructed on a four-layer printed circuit board using a copper-clad FR-4

laminate material. The printed circuit board has dimensions of 43,1800 mm (1.7000 inch) × 82,5500 mm

(3.2500 inch), and the board thickness is 1,5748 mm (0.062 inch). Figure 2 through Figure 8 show the

individual artwork layers.

Figure 2. Top Silkscreen

Figure 3. Layer 1 (Top Signal Plane)

SLAU257A–September 2008–Revised November 2009 DAC8881 Evaluation Module

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Figure 4. Layer 2 (Ground Plane)

Figure 5. Layer 3 (Power Plane)

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PCB Design and Performance

Figure 6. Layer 4 (Bottom Signal Plane)

Figure 7. Bottom Silkscreen

SLAU257A–September 2008–Revised November 2009 DAC8881 Evaluation Module

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Figure 8. Drill Drawing

2.2 EVM Performance

The EVM performance test is performed using a high density DAC bench test board, an Agilent 3458A

digital multimeter, and a PC running LabVIEW software. The EVM board is tested for all codes of 65535,

and the device under test (DUT) is allowed to settle for 1ms before the meter is read. This process is

repeated for all codes to generate the measurements for INL and DNL.

Figure 9 shows the INL and DNL characteristic plots.

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PCB Design and Performance

Figure 9. INL and DNL Characteristic Plots

2.3 Bill of Materials

Table 1. Parts List

Item Qty. Designators Description Manufacturer Mfg. Part Number

1 1 N/A Printed wiring board Texas Instruments 6489896

2 3 C8 C12 C14 1000 pF, 0805, ceramic cap, COG, 50V, TDK C2012C0G1H102J

3 3 C5 C11 C16 10 μF, 1210, ceramic cap, X7R, 16V TDK C3225B63X7R1C106Z

4 7 C1 C2 C3 C4 C7 C15 C17 0.1 μF, 0805, ceramic cap, X7R, 50V, 10% TDK C2012X7R1H104K

5 2 C9 C10 1 μF, 0805, ceramic cap, X7R, 16V, 10% TDK C3216X7R1C105K

6 2 C6 C13 2200 pF, 0805 ceramic cap, COG, 50V, TDK C2012C0G1H222J

7 1 J1 7 × 2 × 2mm terminal strip Samtec TMM-107-01-T-D

8 1 J3 3 × 2 × 2mm terminal strip Samtec TMM-103-01-T-D

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Table 1. Parts List (continued)

Item Qty. Designators Description Manufacturer Mfg. Part Number

9 2 J2 J4 (Top Side)(1) 10 pin, dual row, TH header (20 pos.) Samtec TSM-110-01-T-DV-P

10 1 J6 (Top Side)(1) 5 pin, dual row, TH header (10 pos.) Samtec TSM-105-01-T-DV-P

11 2 P2 P4 (Bottom Side)(1) 10 pin, dual row, TH header (20 pos.) Samtec SSW-110-22-F-D-VS-K

12 1 P6 (Bottom Side)(1) 5 pin, dual row, TH header (10 pos.) Samtec SSW-105-22-F-D-VS-K

13 1 R13 Resistor, 100 Ω, 0603, 1/4 W Yageo America 9C06031A1000JLHFT

14 6 R1 R2 R3 R4 R8 R20 Resistor, 0 Ω, 0603 Yageo America 9C06031A0R00JLHFT

15 2 R23 R26 Resistor, 49.9 Ω1/10W 1% 0603 SMD Panasonic ERJ-3EKF49R9V

16 2 R21 R24 Resistor, 2 kΩ, 0603, Yageo America 9C06031A2001JLHFT

17 1 R9 Resistor, 20 kΩ, 32X4W Bourns 3214W-1-203E

18 10 R6 R10 R11 R12 R14 R15 Resistor, 10 kΩ, 0603 Yageo America 9C06031A1002JLHFT

R16 R17 R18 R19

19 1 R22 Resistor, 95.3 Ω, 0603 SMD Panasonic ERJ-3EKF95R3V

20 8 TP1 TP2 TP3 TP4 TP5 Test point turret Mill-Max 2348-2-00-01-00-00-07-

TP6 TP7 TP8 0

21 1 U1 16-bit, buffered voltage output DAC Texas Instruments DAC8881SRGET

22 1 U2 High precision op-amp Texas Instruments OPA211AIDR

23 1 U3 5V precision voltage reference Texas Instruments REF5050AID

24 1 U4 High precision dual op-amp Texas Instruments OPA2277UA

25 1 U5 High precision, op-amp Texas Instruments OPA277UA

26 10 W1 W2 W4 W5 W6 W7 W8 3 pin mini header Samtec TMMH-103-01-T-T

W9 W10 W11

27 2 W3 W12 2 pin mini header Samtec TMMH-102-01-T-T

28 10 Shunt 2mm shunt – black Samtec 2SN-BK-G

29 0 R5 R7 R25(2) DNP – –

30 1 Shunt 0.100 shunt – black Samtec SNT-100-BK-T

(1) P2, P4, and P6 parts are not shown in the schematic diagram. All P designated parts are installed on the bottom side of the PC board

opposite the J designated counterpart. Example, J2 is installed on the top side while P2 is installed on the bottom side opposite of J2.

(2) Do NOT install the following: R5, R7, and R25.

3 EVM Operation

This chapter describes in detail the operation of the EVM to provide guidance to the user in evaluating the

on-board DAC and how to interface the EVM to a specific host processor.

Refer to the DAC8881 data sheet, (SBAS422) for information about its serial interface and other related

topics.

The EVM board is factory tested and configured to operate in the unipolar output mode.

3.1 Factory Default Settings

The EVM board is set to its default configuration from the factory to operate in unipolar +5V mode of

operation as described in Table 2.Figure 10 shows the default jumper configuration as described in

Table 2 for the DAC8881.

Table 2. Factory Default Jumper Settings

Jumper

Reference Function

Position

W1 1-2 The +5VA is used for AVDD and DVDD to power the analog and digital supplies of the DAC8881.

W2 1-2 Routes VOUT of the DAC8881 to J4-2 for analog output monitoring.

W3 OPEN Disconnects VREFH from the inverting input of U2 for other output mode of configuration.

W4 2-3 Connects the VREFL pin of the DAC8881 to ground.

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